GB1383981A - Electrically alterable floating gate device and method for altering same - Google Patents

Electrically alterable floating gate device and method for altering same

Info

Publication number
GB1383981A
GB1383981A GB196072A GB196072A GB1383981A GB 1383981 A GB1383981 A GB 1383981A GB 196072 A GB196072 A GB 196072A GB 196072 A GB196072 A GB 196072A GB 1383981 A GB1383981 A GB 1383981A
Authority
GB
United Kingdom
Prior art keywords
floating gate
gate
substrate
gate device
jan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB196072A
Inventor
D Frohman-Bentchkowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB1383981A publication Critical patent/GB1383981A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

1383981 Semi-conductor devices INTEL CORP 14 Jan 1972 [15 Jan 1971] 1960/72 Heading H1K Fig. 5 shows a plan view of an insulated gate device having source and drain regions 30, 31 formed in a substrate of P-type silicon covered with silicon oxide insulation (not shown) and bearing a P<+> floating gate 25 of polycrystalline silicon. Two metallic gates 26, 27 are insulated from one another, from the floating gate 25, and from the substrate. In variants (in which the shapes of source, drain, and floating gate differ somewhat from those shown) either gate 26 or gate 27 is omitted. Fig. 6 shows another form, in which the two metal gates 50, 52 are each over part of the channel region. All the devices function as memory devices in which charge is or is not stored on the floating gate. Charge is applied to the floating gate by avalanche injection from the substrate and is removed by avalanche injection from the floating gate to a metal gate. Various combinations of potentials may be used to achieve these changes.
GB196072A 1971-01-15 1972-01-14 Electrically alterable floating gate device and method for altering same Expired GB1383981A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10664371A 1971-01-15 1971-01-15

Publications (1)

Publication Number Publication Date
GB1383981A true GB1383981A (en) 1974-02-12

Family

ID=22312502

Family Applications (1)

Application Number Title Priority Date Filing Date
GB196072A Expired GB1383981A (en) 1971-01-15 1972-01-14 Electrically alterable floating gate device and method for altering same

Country Status (8)

Country Link
JP (1) JPS5146382B1 (en)
BE (1) BE777996A (en)
CA (1) CA946524A (en)
DE (1) DE2201028C3 (en)
FR (1) FR2121824B1 (en)
GB (1) GB1383981A (en)
IT (1) IT962050B (en)
NL (1) NL7200562A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2845328A1 (en) * 1978-10-18 1980-04-30 Itt Ind Gmbh Deutsche MEMORY TRANSISTOR
WO2001024268A1 (en) * 1999-09-24 2001-04-05 Intel Corporation A nonvolatile memory device with a high work function floating-gate and method of fabrication
US6518618B1 (en) 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3797000A (en) * 1972-12-29 1974-03-12 Ibm Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information
US3836992A (en) * 1973-03-16 1974-09-17 Ibm Electrically erasable floating gate fet memory cell
JPS5613029B2 (en) * 1973-09-21 1981-03-25
DE2525062C2 (en) 1975-06-05 1983-02-17 Siemens AG, 1000 Berlin und 8000 München N-channel memory FET array
DE2812049C2 (en) * 1974-09-20 1982-05-27 Siemens AG, 1000 Berlin und 8000 München n-channel memory FET
DE2445079C3 (en) * 1974-09-20 1981-06-04 Siemens AG, 1000 Berlin und 8000 München Storage field effect transistor
DE2513207C2 (en) * 1974-09-20 1982-07-01 Siemens AG, 1000 Berlin und 8000 München n-channel memory FET
DE2643987C2 (en) * 1974-09-20 1984-03-29 Siemens AG, 1000 Berlin und 8000 München n-channel memory FET
DE2638730C2 (en) * 1974-09-20 1982-10-28 Siemens AG, 1000 Berlin und 8000 München N-channel memory FET, method of discharging the memory gate of the n-channel memory FET and using the n-channel memory FET
DE2505816C3 (en) * 1974-09-20 1982-04-22 Siemens AG, 1000 Berlin und 8000 München Method for operating an n-channel memory FET, n-channel memory FET for carrying out the method and applying the method to the n-channel memory FETs of a memory matrix
DE2560220C2 (en) * 1975-03-25 1982-11-25 Siemens AG, 1000 Berlin und 8000 München n-channel memory FET
JPS5554415A (en) * 1978-10-16 1980-04-21 Nippon Gakki Seizo Kk Method and device for space set averaging for reverberation waveform
JPS6162824A (en) * 1985-06-22 1986-03-31 Nippon Gakki Seizo Kk Method and apparatus for compressive intake of reverberation data

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3500142A (en) * 1967-06-05 1970-03-10 Bell Telephone Labor Inc Field effect semiconductor apparatus with memory involving entrapment of charge carriers
CA813537A (en) * 1967-10-17 1969-05-20 Joseph H. Scott, Jr. Semiconductor memory device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2845328A1 (en) * 1978-10-18 1980-04-30 Itt Ind Gmbh Deutsche MEMORY TRANSISTOR
WO2001024268A1 (en) * 1999-09-24 2001-04-05 Intel Corporation A nonvolatile memory device with a high work function floating-gate and method of fabrication
US6518618B1 (en) 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6943071B2 (en) 1999-12-03 2005-09-13 Intel Corporation Integrated memory cell and method of fabrication

Also Published As

Publication number Publication date
FR2121824B1 (en) 1977-04-01
DE2201028B2 (en) 1979-01-18
CA946524A (en) 1974-04-30
FR2121824A1 (en) 1972-08-25
DE2201028C3 (en) 1981-07-09
BE777996A (en) 1972-05-02
IT962050B (en) 1973-12-20
DE2201028A1 (en) 1972-08-31
JPS5146382B1 (en) 1976-12-08
NL7200562A (en) 1972-07-18

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years