DE2505816C3 - Method for operating an n-channel memory FET, n-channel memory FET for carrying out the method and applying the method to the n-channel memory FETs of a memory matrix - Google Patents

Description

The invention relates to a method for operating an η-channel memory FET which is a semiconductor substrate with a source region and a drain region and a

v> has a memory gate arranged above the channel area between the source zone and the drain zone, surrounded on all sides by an insulator, and a control gate that acts capacitively on the memory gate, the memory gate being either uncharged or negatively charged during operation, with the negative The storage gate is charged by supplying electrons from the channel region through the insulator to the storage gate, and the charge state of the storage gate is determined by applying a potential positive to the source * zone to the drain zone and at the same time to such a potential to the control gate the source zone is supplied so that the channel is conductive when the memory gate is uncharged and non-conductive when the memory gate is negatively charged (reading)

positive potential is placed that electrons in the channel region reach such an energy that they the Penetrate the insulator and get to the storage gate (charging by channel injection).

Such a method is the subject of patent 2,445,137. The invention also relates to one n-channel memory FET for carrying out the method according to the invention and the application of the method according to the invention on the n-channel memory FETs of a memory matrix.

In the method according to the patent, an n-channel memory FET is used with negative instead of such as widely used, operated with a positive charge of its memory gate in the programmed state. the negative charging of the memory gate causes the source-drain path, so the main path of this r.-channel memory FET is controlled in the blocking state. If the n-channel memory FET was originally has an enhancement channel that is already blocked in its unprogrammed state, then So this is blocked even more strongly by the programming, so to speak in an excess strongly locking state controlled in, as is also specified in detail in the main application.

In order to discharge the charged, i.e. programmed, memory gate of known memory FETs, the Prior art optical means described. In addition, the one effected by electrical means Discharge, namely either by means of the avalanche effect or by means of a special form of channel injection, described - i.e. by means of compensating charge carriers, either with the avalanche effect from the breakdown-loaded pn junction between the channel and drain or source, or during channel injection z. B. from extremely low-charge areas within the controlled almost in the blocking state Channel are emitted, see z. B. IEEE J. Sol. St. Circ. SC7, No. 5, Oct. 1972, p. 370, Figs. 1 and 2 with associated Description. These emitted charge carriers penetrate with these two known types of discharge Direction to the memory gate through the isolator.

When using the avalanche effect, however, the energy losses, namely those in the breaking through Heat loss resulting from the pn junction, uncomfortably high, i.e. the degree of efficiency during extinction is low. The electrical extinction can only take place slowly. The same applies to the use of canal injection to delete. With these two known discharges, high losses occur in the source-drain path on. Because of the high heat loss in this main route, simultaneous extinguishing is particularly important a large number of or even all programmed memory FETs in the memory, if not difficult even impossible, since this can result in malfunctions and even destruction of such memory FETs can.

There are also other, well-known electrical discharge options for programmed memory FETs:

In the publication J. Appl. Phys. 40 (1969) 278-283 describes the Fowler * North Rhine> tunnel effect. After that, certain isolators such. B. S1O2, electric charge carriers, especially electrons, penetrate, at least with layer thicknesses between some ten apparently linear only up to 150 nm Dependency between the SiCV layer thickness and the necessary driving voltage is present. The driving voltage can be a direct voltage, wherein the memory gate passes through both a metal layer and a semiconductor, in particular durrh polycrystalline silicon, can be formed.

Through the publication Proc. 4th Conf. Sol. St Dev. Tokyo 1972, Suppl. J. Japan Soc. Appl. Phys. 42 (1973), P. 163 left column, penultimate and last paragraph is the application of this effect for deletion, so Discharge of memory gates indicated by p-channel memory FETs, with the discharge of the memory gate to the control gate. Pulse-shaped erase voltages are used accordingly in this publication high stress values are recommended, which, however, in addition to the Fowler-Nordheim tunnel effect intended here presumably also the gate surface effect described below as an erase mechanism trigger.

The "gate surface effect" is described by the publication 11th Annual ReL Phys. 1973, pages 163 to 169 as a further line mechanism known that for Discharge of a storage gate is suitable. Under "gate surface effect" an avalanche breakdown is used here understood in the area of the silicon gate surface, which is there when pulse-shaped, Tensions acting perpendicular to the gate surface arise: with heated on this surface Charge carriers are injected into the insulator. So these are storage gates Semiconductor material, in particular made of polycrystalline silicon, which can also be completely or partially p-doped can. A gate current through the isolator is in this case essentially with the aid of Voltage pulses generated

The gate surface effect and perhaps also the Fowler-Nordheim tunnel effect is used in the DE-OS 23 56 275 = US Patent 37 97 000 described statute of limitations for the operation of a p-channel Spei rather-FET exploited with both effects in the general overlay and where in this pressure

• »0 these two effects are neither described nor is a distinction made between them. About the size of the heat loss with such electrical erasure is also not disclosed in this document

Our own investigations on n-channel memory FETs with memory gate and control gate have shown that especially during the steepest possible leading edge of the supplied erase voltage pulse of corresponding polarity in the memory gate that is sufficiently thick, e.g. 1000 nm thick, a separation of the existing there is free moving, negative and positive charges occurs. The positive holes, which are particularly numerous with p-dot generation, flow to the memory gate surface facing away from the channel, i.e. facing the control gate, and the negative electrons flow to other, opposite, memory gate surface facing the channel. This very rapid separation of the charge carriers initially compensates imperfectly for the high field strength within the memory gate semiconductor layer, in particular on the memory gate surface facing the channel, on which a depletion zone arises with regard to holes. This uncompensated field strength there can be so strong, given a sufficient amplitude of the erasing voltage pulses - or the slope of these pulses, as will be described - that free electrons present there on this surface in

Direction away from this surface through the insulator to the main route, i.e. to the channel or to the drain or to the source, are accelerated so that they leave the memory gate and penetrate the insulator can. Because the exit energy required for the electrons to flow away is significantly smaller than the exit energy is for holes, electrons can exit the memory gate more easily than holes. Therefore is suitable this gate surface effect is preferred for discharging a previously negatively charged memory gate. Usually even during the erasing voltage pulse, e.g. B. shortly after the leading edge of this pulse, however, breaks automatically the previously uncompensated field strength in the storage gate together, apparently there in the storage gate soon enough more new free charge carriers arise, which the field strength more or less compensate. Because of this rapid collapse of the field strength so generally occurs only in the area the leading edge of the erasure voltage pulse a brief drainage of parts of the stored Charge carriers, in the direction from the memory gate to the channel or to the drain or to Source.

The object of the invention is to improve the above-mentioned method for operating an n-channel memory FET in such a way to design that the electrically effected erasure of the programmed n-channel memory FET (Discharging the storage gate) required power loss is as small as possible. Even if a variety of n-channel memory FETs mounted in an on-board memory are intended to be erased at the same time a majority of or even all programmed n-channel memory FETs in this memory, the energy losses and thus the harmful heat loss and therefore the minimum time allowed for extinguishing be particularly low. The circuit and manufacturing costs required for this should be as low as possible.

In the method mentioned at the beginning, this object is achieved according to the invention by means of the characteristics of claim I mentioned measure solved.

This measure, through which a discharge of the storage gate by means of the Fowler-Nordheim tunnel effect and / or gate surface effect to the source zone or to the drain zone or to the channel region is effected, has the advantage that heat losses essentially only through the penetrating the insulator, comparatively small currents are generated.

With electrical extinguishing by means of the avalanche effect or the channel injection, however, were also in addition to the heat loss generated in the insulator still comparatively extraordinarily high heat losses generated in the main line. With these two The last-mentioned effects must namely be comparative in addition to the currents discharging the memory gate Very high currents are generated within the main line to prevent the discharge of the To effect memory gate, with high channel currents triggering erase voltages especially between Drain and source or between drain or source on the one hand and channel on the other hand are to be applied, so that At least in parts of the main line, currents flow which are extraordinarily much larger than those in the case of the Invention provided currents.

The method according to the invention allows not only repeated electrical programming and erasure of the n-channel memory FET, but also in particular to reduce the time required for the electrical erasure of the n-channel memory FET, so that many at the same time because of the entangled Veflustwäfme or even all n-channel memory FETs of a memory, e.g. As can be electrically erased within milliseconds, this utld also with particularly s low energy consumption. The additional effort required to carry out the method according to the invention is particularly low.

The invention is explained in more detail using exemplary embodiments, for which FIG. 1 and 2 serve, where

to Fig. 1 an embodiment of a single n-channel memory FET and

Fig. 2 shows an example of an insulator thickness erasing chip n- diagram when using the Fowler · Nordheim tunnel effect shows.

The n-channel memory FET shown in FIG. 1 is programmable using channel injection. To enable channel injection, somewhere in channel K between drain D and source S, preferably in the vicinity of the drain, see V in FIG of the channel, e.g. B. is formed by a narrowing of the channel or by a thickening of the insulator over this point of the channel. The provision of such acceleration sections in an n-channel of an n-channel memory FET and the use of such acceleration sections for programming has already been proposed by the patent 24 45 079. The current Ke charging the memory gate G I, cf. I indicated acceleration path at point V of the channel.

This current Ke is a current of electrons, which is normally the case with channel injections, so that the isolated floating memory gate G 1 is negatively charged during programming. The insulator Is with the thickness Ai between the memory gate G 1 and the channel forms a barrier which must also be overcome when the n-channel memory FET is electrically erased. According to the invention is provided in that the negatively charged, ie, programmed memory gate G 1 is discharged by the fact that on the one hand between the control gate G 2 and on the other hand, the channel region K

■ * 5 or the source region S and drain region D, an erase voltage is applied, wherein the control gate G 2 is negative relative to the respective other area is thereby effected that stored in the storage gate G 1 electrons produced by the erase voltage

accelerated in the direction away from the memory gate into the area * of the insulator, through the insulator χ or Fs to the channel K or to the drain D or to the source S. In this case, especially when the substrate is floating, essentially only this current between the memory gate and the main line generates the heat loss, since no significant additional heat loss is required for erasure by currents flowing along the main line.

The in F i g. The n-channel memory FET shown in FIG. 1 can form a single memory cell of a memory. Because of the low energy losses, a large number or even all of the n-channel memory FETs can be used at the same time this memory can be quickly erased by electrical means, without the memory or the individual n-channel memory FET overheat. The measure according to the invention is therefore particularly with low expenditure of heat loss and time z. B.

within a millisecond, even a very large number the memory's n-channel memory FETs simultaneously erasable, and additionally with a particularly low expenditure of energy. The invention thus represents a Advantageous further development of the method described in the main application for operating an n-carial memory FETdar.

It was found that it is particularly advisable in the deletion of the Speititergate G 1 in general, to that of main track area, for the data stored previously in the storage gate G 1 Elektrohen. B. Source S to drain, via which originally no programming of the memory gate took place. In the case of the in FIG. 1, the programming takes place within the channel, specifically in the vicinity of the drain D by the discharge current Ke. The discharge of the storage tank Gl programmed negatively with electrons takes place, as indicated in FIG. 1 by the discharge current Kc /. therefore advantageously towards the source i> , that is to say in a region of the insulator which is far removed from the region of the current Ke . This measure has the effect that the insulator / 5 in its area .y between the memory gate G 1 and channel is less poisoned with each new programming and discharge of the memory gate than when the programming and erasure or discharge of the memory gate in each case over the same area in Isolator / 5 would be done. The measures to allow the electrons to flow away during erasure to that main route area through which the programming of the memory gate is not carried out, so has the advantage that the memory gate and thus the n-channel memory FET more often than without this measure on electrical engineering Way can be reprogrammed.

The erase voltage can be, for. B. be a DC voltage which is applied between the control gate G 2 on the one hand and the channel K or the drain D or the source S on the other hand. The erase voltage can, however, also be a sequence of pulses which is applied between the control gate on the one hand and the channel K or the drain D or the source S on the other hand. Whether a direct voltage or an alternating voltage is applied depends in particular on it. whether primarily the Fowler-Nordheim tunnel effect or the gate surface effect should be used for the solution. When using the Fowler-Nordheim tunnel effect, both types of voltages, preferably direct voltages, can be used, with the discharge currents flowing from the memory gate G 1 to the main line during the entire selected duration of the application of the erasing voltage until all electrons that can be caused to flow away by this direct voltage are removed from the Storage gate Gi have drained. However, it has also been observed that by using pulse sequences of similar high amplitudes, the discharge could occasionally be accelerated with the aid of the Fowler-Nordheim tunnel effect - presumably because of the simultaneous occurrence of the gate surface effect. Therefore, even when using this Fowler-Nordheim tunnel effect, erasing voltage pulse trains or a direct erasing voltage with superimposed pulse trains between control gate G 2 on the one hand and channel K or drain D or source 5 on the other hand can often be advantageously applied.

As described, the discharge can also be far-sighted take place with the help of the gate surface effect, i.e. by applying erase voltage pulses with sufficiently steep leading edges and sufficient amplitude, e.g. at pulse repetition frequencies of 100 kHz up to 1 MHz with duty cycle I: I, between the control gate G 2 and that area of the main line, ι where the previously loaded in the storage gate G1 Electrons should flow away. The memory gate is made of polycrystalline silicon that is p-doped. By applying such erase voltage pulses, as indicated in FIG. 1 and already indicated above

to is described, the charge carriers in the storage channel G 1 are separated. However, this separation is not sufficient to completely compensate for the field strength originally generated by the erasing voltage pulse in the storage tank G 1. Especially on the one facing the sewer

(5th. Enriched with the stored electrons On the gate surface, a correspondingly deep depletion zone remains with respect to the majority charge carriers. so a remaining uncompensated field strength, through which this can be removed from the memory gate-

load . Electrons previously stored there are accelerated in the direction of the relevant area of the main line so that they leave the storage gate G 1 and penetrate the insulator Is in the area ν and into the relevant area of the main line

2s can flow off. Because of the rapid collapse the remaining uncompensated field strength at the memory gate surface must be completely discharged of the memory gate G 1 as a rule not just an erase voltage pulse. but a bigger consequence such impulses are inflicted.

The application of the Fowler-Nordheim tunnel effect has compared to the application of the gate surface effect the advantage that the deletion of the previously charged memory gate because of the applicability of DC quenching voltages can be done in a single process. When using the gate surface effect on the other hand, if the leading edges of the pulses are steep, the erase voltages are often lower sufficient. This is particularly useful in many integrated memories, since their edge electronics are often only can supply relatively low voltages for operating the memory with relatively little effort.

When using direct voltages to erase the programmed n-channel memory FET and applying ground potential to the control gate G 2, the memory gate G 1 can be discharged approximately to the extent that it will later approximately be at ground potential such a mode of operation approximates either such a complete discharge or an excessive discharge of the storage gate G 1 going beyond such a discharge. In general, one would like to have a defined potential after the discharge on the storage gate, B. is identical to the potential at control gate G 2, source S, drain D and channel K if the control gate G 2, source S. drain D. and channel K each have the same potential

w) not only would such a complete discharge of the Storage gate G t. but, so to speak, a new charging of the storage gate Gl with a potential! reverse polarity, which, at least in general, is undesirable Dadarch. that at

* 5 Apply the DC voltage of the appropriate magnitude and duration as the erase voltage, the control gate G 2 approximates the ground potential is such excessive discharge, i.e. charging with reverse

Polarity, largely avoidable - with a slight deviation from the desired ideal discharge of the storage gate is often harmless or only slightly harmful.

On the other hand, by applying a DC voltage as the erase voltage with a potential of the control gate G 2 deviating from the Efdpolential sta ^ k potential of the control gate G 2, a different end state of discharge of the storage device G 1 can be achieved, if such a different discharge state is sought.

The same also applies to the use of the gate surface effect to erase the memory gate. Here, too, the unprogrammed state of the memory gate C i can be defined differently in the same way as required. Depending on which potential is fed to the control gate G 2 and how the steepness of the leading edge and the number, duration and amplitude of the erase voltage pulses are selected, a different discharge state of the memory gate is achieved. Atsu can also use the gate surface effect to achieve any desired discharge state of the memory gate G 1. In particular, it is possible to reduce the erase voltage by a constant potential supplied to the control gate G 2 - in particular ground potential - and by z. B. to generate voltage pulses applied to the source. The resulting 1 erasing voltage pulse sequence causes the selected erasure of the memory gate, namely by flowing away the previously stored charge carriers, here to the source S.

If the source 5 is supplied with a very long-lasting sequence of such positive erasing chip manure pulses and the control galepotential is selected accordingly, e.g. B. identical to the drain potential at ground potential, because of the very high number of erase voltage pulses, a final state of the potential of the memory file G 1 can be achieved, which is fairly easily reproducible and, moreover, depending on the choice of the control gate potential and the erase voltage present at the same time. ungsimpulsamplitude can be specified almost arbitrarily.

Especially about the Fowler-Nordheim tunnel effect to use advantageously, it is advisable to choose a certain • ptimaie insulator thickness Ar:

This thickness λ: should often _{exceed a lower limit value x mm in} order to avoid disturbances, e.g. B. so that the charged memory gate is not partially discharged again due to the galvanic connection of the drain of this n-channel memory FET with the drain of another n-channel memory FET that has just been programmed. If you choose z. If, for example, SiCh is used as an insulator, then in the example shown it is usually favorable to choose the fcolator thickness χ greater than approximately 40 to 500 nm.

F i g. 2 illustrates the lower limit value for the insulator thickness x. This Figure 2 shows a graph on the abscissa the logarithm of the insulator thickness is registered χ in the ordinate is the logarithm of the effectively active erase voltage U, which must be exceeded during erasure, between the memory gate G 1 and that main line region, for. B. S or D, entered where the electrons of the memory gate GX are to flow. The curve Fi illustrated because of their slope of about 45 °, that in this insulator, here S1O2, the Fowler-Nordheim tunneling effect χ an approximately linear relationship between the insulator thickness and the Mmdest-LöschspaJ ^ ung U is present This curve Fi is at lower limit value, here at x _mm = 45 nm, intersected by curve F3. The curve FI corresponds to z. B. Uo = 15V, Ug = -10V at an unselected, already programmed cell Z1 of a special embodiment when programming the neighboring cell Z2, which was connected to the same column line connected to the drain. As long as Fl is below F3, i.e. when x <Xmin , cell Z1 is partially erased when programming cell Z2. The optimal insulator thickness

in χ is therefore greater than this lower limit value.

It turns out that the insulator thickness χ often also has an upper limit value, v _mar , so that the insulator thickness χ should be selected to be smaller than this upper limit value. The insulator thickness χ should namely fall below that upper limit value at which a strong avalanche breakthrough sets in between the source and the biased substrate, in which acu z. B., under the respectively selected values for the DC voltage supply, which by means of the Fowler

"· Nuidneiiii-Tumieieffekies outflowing electron currents Kd from the storage gas are about the same size as the hole currents flowing between drain D and channel K to storage gate G 1 because of the avalanche effect in the blocked pn transition. With SiOj as an insulator

■ 25 Yes is this upper limit value x _max generally about 110 or 120 nm. This upper limit value of the main flow path at the same time strong heating of the same number of holes Ke due to the avalanche effect to the previously loaded memory gate G 1 as

3ö due to the Fowler-Nordheim tunnel effect at the same time from this memory gate G 1 to the main route of the n-channel memory FET, in particular to the source, electrons Kd flow away. By making the insulator thickness A ^- greater than this upper limit value x _m3 x, then exceeds this example, the current generated by the avalanche effect, see Ke, of holes of the respective pn-junction between the drain and the channel to the memory gate Gi flows, respectively. due to the Fowler-Nordheim tunnel effect from the storage gas

■ to te Gi outflowing electron current Kd. Instead of achieving a discharge Kd of the storage gate with the help of the Fowler-Nordheim tunnel effect in the desired η manner, the previously negatively charged storage gate G 1 is discharged by the compensating hole current Ke generated with the help of the avalanche effect with high heat loss.

The curve FZ, which is inclined approx. 22 ° to the abscissa in accordance with the mostly quadratic dependence of the relevant function, corresponds to the dependence of the minimum value of the voltage U between the memory gate Gi and the drain D (ordinate) on the layer thickness α (abscissa) with regard to the generation of the hole current Ke generated by the avalanche effect. The intersection of curves F1 and F2 results in the upper limit value x _{mlx of} the layer thickness χ: above this, the Avalancheeffeki Lfcher current Ke exceeds the desired discharge current Kd

In addition, it is generally advisable to use the Isolatordik- {ce A 'should be selected as small as possible, so that the extinguishing voltage amplitude required for the deletion as possible is small. z. B. is about 40V - so low If necessary, voltages can be more easily supplied by the peripheral electronics that control the memory.

The layer thickness should then be only a little more than the lower limit value x _m a of this thickness in order to enable low erasing voltages.

The optimal insulator thickness * is therefore in general

mögÜEhst x far below this critical upper limit value x _ma x for the layer thickness, in which mutually intersect the curves Fl and F2. In the example shown in FIG. 2, according to the specific numerical values given there, the optimal layer thickness χ is about 60 nm, see "opt." In FIG to leave the optimum clearly.

To erase the n-channel memory FETs with the aid of the gate surface effect, it is advisable, as already stated, to construct the memory gate G 1 from a semiconductor which is doped in the opposite direction to the type of charges that are stored on it during programming. Since negative charges are stored on the memory gate, the semiconductor memory gate G 1 should be p-doped.

As with the application of the Fowler-Nordheim tunnel effect, there is generally an upper and lower limit value for the layer thickness χ of the insulator Is when using the Gaieoberfiächeneifektes. The curves F1, FZ then had approximately the same course in one example as in Fig . The curve F \ , however, has a different shape and position than in FIG. 2. The course of the curve F I is then additionally dependent on the steepness of the erasing voltage pulse leading edge and on the duration of the individual pulses. For low values of χ, higher field strengths are necessary than for higher values of χ , see J. Elektrochem. Soc. Sol. St. Science and Techn. 119 (1972) 598 Fig. 3. The lower and upper limit values that can be determined in this way, as well as the optimal value of the insulator thickness

but often do not differ too much from those for Fowler-Nordheim tunnel effect, so that in an n-channel memory FET example also about 60 nm was found to be the optimal thickness Ar.

As already mentioned, the heat loss is particularly low if the stored. Electron electrons can flow to the drain or to the source when the substrate is floating. But even if the substrate is on a bias, z. B. because of the edge electronics, are the losses generated in the main line low compared to extinction using the avanlanche effect or channel injection, as can be seen from the Explanations of the upper limit values for the insulator thickness are given.

Our own investigations have shown that the electron discharge current / Wein further hole discharge current - Kd 'is often superimposed in the opposite direction, at least temporarily. This superimposed hole current - Kd also has a de facto discharging effect on the memory gate G 1. This superimposed hole current does not require a strong current along the main line to generate it, so it arises without any significant generation of heat loss in the main line. Therefore, this superimposed hole current would rarely be explicitly mentioned in the description, but would be regarded as part of the electron current Kd flowing away from the memory gate - also in order not to have to describe the essence of the invention and its developments in too complicated a manner. If necessary, the description should be supplemented accordingly.

1 sheet of drawings

Claims (13)

Patent claims: 1. A method for operating an n-channel memory FET, which has a semiconductor substrate with a source zone and a drain zone and a channel region located between the source zone and the drain zone and surrounded on all sides by an insulator Storage gate and a control gate capacitively acting on the storage gate, the storage gate being either uncharged or negatively charged during operation, the negative charging of the storage gate also being effected by supplying electrons from the channel region through the insulator to the storage gate and the charge state of the storage gate thereby It is established that a potential positive relative to the source zone is applied to the drain zone and at the same time the control gate is supplied with such a potential relative to the source Ζοπ.ί that the channel is conductive when the memory gate is uncharged and non-conductive when the memory gate is negatively charged (Reading), being used to supply electrons to the store gate, a positive potential is applied to the drain zone with a channel that is conductively controlled by means of the control gate, so that electrons in the channel area reach such an energy that they penetrate the insulator and reach the storage gate (charging by channel injection), according to patent 24 45 137 , characterized in that when the memory gate (Ci) is discharged, an erase voltage is applied between on the one hand Jem S euergate (G 2) and on the other hand the Kaialbereich (K) or the source zone (S) or the D ain zone (D), in which the Steuerga-Ie (G 2) is negative compared to the other area (7C S, D) . 1. The method according to claim 1, characterized in that the other region is the source (S) \ st 3. The method according to any one of the preceding claims, characterized in that the deletion »Voltage is a direct voltage. 4. The method according to claims 2 and 3, characterized in that the erase voltage is formed by a control gate (G 2) fed to the ground potential and by another constant potential supplied to the source. 5. The method according to claim 1 or 2, characterized in that the erase voltage is a consequence of pulses is. 6. The method according to claims 2 and 5, characterized in that the erase voltage is formed by a constant potential supplied to the control gate (G 2) and by the source (S) »ugeleguided pulses. 7. The method according to any one of the preceding claims, characterized in that the potential of the substrate floats during discharge. 8. The method according to any one of claims I to 6, characterized in that the substrate during the discharge is a bias voltage (-5V). 9. The method according to any one of the preceding claims, characterized in that when discharging, the potential of the source zone (S) or that of the drain zone (D) floats so that no electrons flow away there. 10. n-channel memory FET, which is a semiconductor sub- strat with a source region and a drain region and one above between the source region and the The memory gate located in the drain zone and surrounded on all sides by an insulator and a control gate, which acts capacitively on the memory gate, for carrying out the method according to claim 5 or 6, characterized in that the memory gate is made of p-doped polycrystalline Silicon is made of 11. n-channel memory FET according to claim 10, or for a method according to one of claims 1 to 9, characterized in that the insulator thickness (x) between the memory gate (G 1) and the channel region (K) has that value ( 45 nm), in which the charged memory gate (Gi) - due to a galvanic connection of the drain (D) of this n-channel memory FET with the drain of another n-channel memory FET that has just been programmed - at least partially is discharged again. 12. n-channel memory FET according to claim 10 or 11, for a method according to one of claims 1 to 9, characterized in that the insulator thickness (x) between the memory gate (G 1) and the channel region (K) that value (120 nm), at which the electron currents flowing away from the memory gate (Gi) during erasure (KdJ equal to the - due to an avalanche effect occurring during erasure from a blocked pn transition of the main route of this n-channel memory FET to its memory gate (G 1) - flowing hole currents (Ke) smd. 13. Application of the n-channel memory FET according to one of claims 10 to 12, or of the method according to one of claims 1 to 9, to the n-channel memory FETs of a memory matrix, in particular a program memory of a telephone switching system in which each memory cell consists of an n-channel memory FET and in which the drain zones of the n-channel memory FETs column by column and their control gates are connected by rows.