CA1070427A - N-channel storage field effect transistors - Google Patents

N-channel storage field effect transistors

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Publication number
CA1070427A
CA1070427A CA235,230A CA235230A CA1070427A CA 1070427 A CA1070427 A CA 1070427A CA 235230 A CA235230 A CA 235230A CA 1070427 A CA1070427 A CA 1070427A
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Prior art keywords
storage
gate
channel
fet
drain
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Expired
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CA235,230A
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French (fr)
Inventor
Bernward Rossler
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Siemens AG
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Siemens AG
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Publication date
Priority claimed from DE2445137A external-priority patent/DE2445137C3/en
Priority claimed from DE19752505816 external-priority patent/DE2505816C3/en
Priority claimed from DE2513207A external-priority patent/DE2513207C2/en
Priority claimed from DE19752525097 external-priority patent/DE2525097C3/en
Priority claimed from DE19752525062 external-priority patent/DE2525062C2/en
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of CA1070427A publication Critical patent/CA1070427A/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

ABSTRACT OF THE DISCLOSURE

An n-channel storage FET is described having a source and a drain formed in a substrate and a floating storage gate entirely surrounded by an insulator on said substrate, wherein in use said storage gate is programmed by negatively charging it by channel injection using electrons heated in the channel between said source and said drain, and wherein the negative charge on said storage gate, after charging and in particular at the time of read-out, acts inductively on the channel between said source and said drain in such a way as to inhibit the drain-source current of the transistor. Details are given of the electrical discharge of such FETs by the Fowler-Nordheim tunnel effect and/or the gate surface effect.

Description

The present invention relates to an electronic component with storage properties in the form of a storage field effect transistor (FET) which has been developed for use in a programme store belonging to a telephone exchange system but which is also suitable for use in other types of store, e.g. program~e stores in data processing systems.
Storage FETs having a source and a drain formed in a substrate with a channel therebetween and an electrically floating storage gate which is surrounded on all sides by an insulator have been described in a wide range of publi-cations, and a review of the properties of storage FETs of the type which have previously been described, together with a discussion of the state of the art generally will now be given.
Storage FETs of this kind can be programmed by using the avalanche effect, ~see for example Sol. St. Electronics 17 (1974) 517-529). The floating storage gate in these stor-age FETs is thus charged by charges which are heated due to the avalanche effect at the interface between the drain and the remainder of the substrate, when the blocking p-njunction breaks down, and which, because of their increased energy, penetrate through the insulator, especi-ally if a voltage which tends to accelerate these charges is applied between the substrate and the storage gate. For example, in United States Patent Specification No. 3,660,~19 Figure 1 illustrates how storage FETs of this kind uith a floating : - 2 -4.~

storage gate 14 can also be provided with a controllable control gate 18 which acts capacitively upon the storage gate 14 and the potential of which therefore influences the potential on the storage gate 14 and consequently the drain-source current also. Storage FETs of this kind with a floating storage gate and a controllable control gate are widely known from other publications.
The charges heated up by the avalanche effect and injected into the storage gate consist either of electrons or ho]es; in n-channel storage FETs we are, of course, as those skilled in the art will realise, dealing with holes, and in p-channel storage FETs, with electrons, as described in the prior art already referred to. The charge carriers which charge the gate and are heated by the avalanche effect thus have the same polarity as the minority charge carriers in the drain.
Accordingly, in the known storage FETs, the storage gate is negatively charged if a p-channel storage FET is in question, but positively charged if the FET concerned is an n-channel storage FET. The storage gates of both storage FET types which are charged up by the avalanche effect therefore drive the relevant FET into its conductive state in all cases, because the storage gate, irrespective of the channel type, by virtue of the particular charges injected acts by induction into the substrate zone between the drain and source in such a way that, as compared with 10~ '7 uncharged storage gates, the flow of a drain-source current is not inhibited but instead assisted. The injected charges thus act upon this substrate zone in such a way that, by induction, free charges are collected there which have the same polarity as the majority charge carriers in the drain and source.
Figures 1 to 6, and 8 to 17 of the accompanying drawings show embodiments of the invention and their behaviour, enumerated later ~on page 13, line 18 to page 15, line 6) and explained afterwards in detail. But Figure 6 shows a state diagram of known FETs with floating storage gates, namely of SAMOS-FETs, which are FETs, the storage gate of which is charged by avalanche effect. In general, such SAMOS storage FETs ("stacked gate avalanche injection MOS-FET"), described in the prior art, are FETs of the enrichment type, because only in this type of FET is the resistance between the drain and the source very high in the unprogrammed condition (i.e. the discharged state) of the storage gate, and comparatively very low in the programmed state, i.e. the ratio between the two resistances is very great;
this is illustrated by Figure 7 of the accompanying drawings which is a graph illustrating the dependence of the drain-source current I-DS upon the control gate source voltage U-G2 for a known n-channel storage FET. Reference may also be made to Figures 2 and 5 appearing in IEEE J. Sol. St. Circ. SC7, No. 5, October 1972, pages 369-375. The curve GO of Figure 7 applies to the uncharged storage gate of an enrichment type FET and the curve G1 belongs to the storage gate of the same FET after being charged by the avalanche effect. Because of the charging of the storage gate Isee 1 in Figure 73 this known FET also con-ducts when U-G2=0. This enrichment type FET, therefore, after programming~
with respect to its control gate G2, possesses the properties of a depletion `~
,,~S

1~'7~ 7 type FET. Only after erasure, i.e. after discharge of the storage gate, is the resistance of the storage FET again very high when U-G2=O, because for this FET, the curve GO then again applies exactly or at least approximately.
The FET thus then once again has approximately enrichment type properties, considered in relation to its control gate G2.
If, instead of this, the known storage FET were to have been provided with a depletion type channel, then the storage gate when charged by the avalanche effect would have the unfavourable effect of making the channel, which anyway exists there, even more conductive than it is in the unprogrammed state of the storage gate; this, too, has been illustrated in Figure 7. The curve Gl represents the dependence of the drain-source current I-DS upon the control gate source voltage U-G2, in an n-channel storage FET of depletion type, when the storage gate is in the unprogrammed state. If the storage gate of this FET is charged by means of the avalanche effect, then the curve G2 is obtained for the dependence of the drain-source current I-DS upon the control gate source voltage U-G2. Through the charging of the storage gate of this FET ~see 1' in Figure 7) i.e.
with the storage gate in the programmed sta~e, the FET conducts when U-G2=0.
In this condition, this depletion type FET, as regards its control gate G2, thus continues to exhibit depletion type properties as it did in the unpro-grammed state. The conductivity of this storage FET is only increased to a relatively minor extent by programming, for example, by a factor of 2, when this depletion type FET is programmed by the avalanche effect; this is indicated in Figure 7 by the point of intersection of the curve G2 with the I-DS axis.
The ratio of the resistance between the drain and the source in the unprogrammed state to the resistance between the drain and the source in the programmed state is thus considerably smaller in the depletion type of storage FET than in the enrichment type of storage FET. Consequently, generally speaking only enrichment type storage FETs have hitherto been used.
Storage FETs with a floating storage gate can, as those skilled in the art will be aware, be erased by the use of optical means, for example, by irradiation with ultra-violet light. This radiation enables holes or electrons to be heated to such an extent that they can penetrate through the insulator and thus discharge the storage gate.
A method of erasing storage FETs of this kind with a floating storage gate using electrical means is also known. For this purpose, the charged storage gate of a first storage FET is subsequently discharged by charges of opposite polarity produced by a second avalanche effect which is generated in a second storage FET connected in parallel with the first ~see the article in IEEE, previously referred to, Figures 1 and 4, and the associated description). The storage FET thus forms part of a parallel arrangement of a p-channel storage FET and an n-channel storage FET, with a single, common storage gate (see also Figure 6 (b) of the article in question). This known storage FET parallel arrangement in accordance with Figure 1 of the article, thus has two different p-n junctions which can selectively be loaded to break-do~Jn in order to generate heated electrons or holes. The parallel arrangement of storage FETs corresponds in the un-programmed state (see Figure 4 "as grown"), to an enrichment type storage FET and is therefore non-conducting if no voltage is applied to its con-trol gate. By means of the first avalanche effect, the parallel arrangement is driven by electrons injected into the storage gate into the programmed, i.e. into its conductive state ~see i'l state" in Figure 4). By means of the second avalanche effect, the parallel arrangement is discharged again by the holes ~see "0 state~)in the same Figure 4).

All these known FETs are accordingly enrichment type FETs in the unprogrammed state relative to their control gates. In the programmed state, however, they always behave like depletion type FETs relative to their control gates. Because discharge, generally unintentionally does not take place without certain disturbances, a certain number of residual charges remain on the storage gate or at trapping centres in the insulator between the storage gate and the substrate, so that the parallel arrangement of storage FETs does not exhibit after discharge precisely the same properties as prevailed before programming (in this connection, see the spread in the measurement points in Figures 4 and 5 of the article referred to above).
After discharge, the parallel arrangement of these storage FETs nevertheless behaves like an enrichment type FET (as before) which after fresh programm-ing, goes conductive again like a depletion type FET.
Disturbances of this kind during the electrical erasure of stor-age FETs also occur in a known electrically erasable FET with a channel about 10 microns long and a p-substrate of resistance about 10 ohm. cm, in which drain and source construction is otherwise normal (see Figures 2 and 5 o~ the cited IEEE pulbication). In this case, we are concerned with an n-channel storage FET with an insulated floating storage gate Gl and an externally controllable control gate G2. The storage FET, as is usual in the prior art, is obviously of the enrichment type in the unprogrammed state. Thus, with no voltage on the control gate G2 the FET blocks after manufacutre but prior to programming (see also the "as grown" curve in Figure 5 of the article~. This storage FET is programmed by holes using the avalanche effect, and is therefore ~as is usual in the prior art) driven into its conductive state (see the "1 state" in 1070~2~

Figure 5). Thuss with programming, this enrichment type s~orage FET acquires properties resembling those of a depletion type FET, referred to its control gate. To that extent, this storage FET does not differ from the other known n-channel storage FETs with a floating storage gate.
Erasing is carried out, however, using neither optical means nor by means of a second avalanche effect in the way used in the parallel arrangement of two storage FETs shown in Figure 1 of the article. The erasing of the positively charged storag0 gate, as shown in Figure 5, is performed electrically by means of a very rare physical effect, one indeed which is only described by these authors, namely that of "channel injection". For this purpose, according to this publication, the storage FET in question is driven via its control gate into a condition in which it virtually ceases to conduct, so that in a small part of the channel there is a considerably reduced charge carrier density, i.e. electron density, than in the rest of the channel.
In this charge-depleted zone, higher longitudinal field strengths develop between the drain and the source than are present in the rest of the channel which has a larger charge carrier population. The free charges flowing through this charge-depleted region, are therefore more highly heated than in the remainder of the channel. If suf-ficient heating occurs in this charge-depleted region, these charges can penetrate through the insulator and charge the floating storage gate Gl. The charges produced by this channel injection phenomenon and penetrating through the insulator are in this case electrons and the electrons charge up the storage gate of the n-channel stor-age FET This storage gate is therefore supplied with electrons heated by channel injection for erasing purposesJ
whilst for programming it is supplied with holes heated up by avalanche effect.
After the discharge produced by channel injection (and this phenomenon takes place extremely slowly according to the publication referred to), the storage FET has approxi-mately the same enrichment type properties as it had before programming. If the control gate carries no voltage, therefore, the drain-source region does not conduct or hardly conducts at all. Here again, after discharge, small disturbances are usually observed, residual charges being left on the storage gate or at trapping centres in the insulator between the storage gate and the substrate.
Because of these residual charges which are left behind, the storage FET, after erasing, does not have exactly the same properties as it had prior to programming, but instead ones which are only generally similar.
To sum up, the various known storage F~Ts with insulated, floating storage gates are thus so programmed using the avalanche effect that they are driven into the conductive state, i.e. so that the charging up of the storage gate acts _9_ 1 0 70~Z7 upon the drain-source region by induction in a manner which promotes the drain-source current. Programming imparts depletion type properties to the storage FET. Both optical and two different electrical erasing methods are known, the electrical erasing technique being performed either by means of a second storage FET or by means of channel injection.
It is an object of the invention to provide a storage FET with an insulated floating storage gate in which the charged storage gate acts to inhibit the drain-source current rather than assisting it as in known FETs.
According to the invention, there is provided an n-channel zone storage FET comprising:
a p-doped semiconductor substrate having formed therein source and drain regions of n-doped materials, a region of said substrate between said source and drain regions forming said channel zone therebetween, a layer of insulating material adjacent said substra~e, a floating storage gate entirely surrounded by said insulating material and arranged so as to have at least a portion of said insulating material disposed between said channel zone and said floating storage gate located so as to be able to receive electrons from said channel zone through said insulating material, means for producing channel injection to charge said gate comprising means for applying a potential to said source and said drain regions to produce a longitudinal field strength and a source-drain current of electrons between said source and drain regions and to accelerate said electrons by said longitud-inal field streng~:h to a sufficiently great d~gree that at ~ -10--~,1)'~042'7 least a portion of them penetrate said portion of said insulat-ing material and charge said floating storage gate, and the negative charge so produced on said floating storage gate can act, by electrostatic induction, to reduce or inhibit the source-drain current of electrons between said source and drain.
The inhibiting of the drain-source current is thus not achieved in the present invention by the parallel arrangement of two storage FETs with different channels and a common float-ing storage gate. All the charges which charge and discharge the storage gate, are generated in the single -lOa-1~70~Z7 storage FET of the invention itself by heating. The invention, therefore, relates to a completely new type of storage FET
with an insulated, floating storage gate, and with a con-struction which in comparison with the known parallel arrangements, involves less expense and is less critical in terms of manufacturing tolerances. Moreover, the invent-ion makes it possible to effect electrical erasing by means of free charges heated up in the storage FET itself.
The invention also makes possible storage FETs of the kind in which the channel is completely non-conducting, both in the programmed and in the non-programmed state, so that extremely unusual properties are achieved, carrying with them special advantages.
The invention is based upon the consideration that for programming purposes, the storage gate is charged up not with charge carriers whose polarity corresponds to thæt of the minority charge carriers of the drain, but with charges, whose polarity corresponds to that of the majority charge carriers of the drain. The invention moreover depends on the novel recognition that, by means of channel inj~ction, electrons are heated up but virtually no holes, so that it is the electrons which charge up the storage gate. The invention furthermore offers the possibility of using processes which have not hitherto been so employed;
embodiments of the storage FET in accordance with the in-vention can surprisingly be programmed extremely quickly, 10'704Z7 e.g. ~ithin a millisecond, by electrons produced by channel injection. Merely by virtue of the fact that the invention has an n-type channel, the time required for programming is substantially shorter than if a p-type channel had been used, probably because the high electrons density in the n-type channel means that the number of heated ele~trons available for channel injection is greater than with p-channel storage FETs.
Preferably storage FETs in accordance with the in-vention have-~he shortest possible channel, e.g. 3 microns or even less, and a relatively highly-ohmic substrate, e.g.
one with a resistance of 3 to 10 ohm-cm. Preferably, the channel exhibits an acceleration zone, constituted by a localised spatial inhomogeneity which makes it possible to heat the electrons for charging the storage gate by channel injection to a particularly high degree.
In the present invention, therefore, the phenomenon of channel injection which has hitherto been almost dis-regarded is utilised, not for erasing, but for programming the n-channel FET. The electrons which charge the storage gate control the drain-source region, driving it into the blocking state, because these charges injected into the gate result through the mechanism of induction in the collection of holes between the drain and the source so that the resistance between the drain and the source is increased. If the storage FET of the invention exhibits 1070~27 an enrichment type channel in the unprogrammed state, i.e.
a channel which is normally blocked, then programming will block this storage FET to an extent even greater than that to which it was blocked in the unprogrammed state.
If the storage FET of the invention has a depletion type channel, (which is not usual in the known storage FETs) then because of the electrons generated in the channel of the FET itself as a consequence of channel injection, in the programmed state the channel will block or at least be high-ohmic in nature.
If the storage FET of the invention is to be erased again, then its blocking drain-substate p-n junction can be driven into the breakdown condition so that heated charges produced in the storage PET itself, discharge the storage gate.
The invention will now be further described with reference to the drawing, in which:-Figure 1 is a schematic side-sectional view of a storage FET in accordance with the invention;
Figure 2 is a state diagram pertaining to embodiments of the invention which, in the unprogrammed condition, are partially of depletion type and partially of enrichment type;
Figure 3 is a state diagram relating to an embodiment of the invention, which in the unprogrammed condition is of deplétion type;

J

~0'7()~27 Figure 4 is a circuit diagram of a two-dimensional store matrix with storage FETs in accordance with the in-vention serving as storage elements;
Figure 5 is a state diagram relating to an embodiment of the invention with a "blocking channel";
Figure 6 is a schematic side-sectional view of a storage FET in accordance with the invention, with a blocking channel in the unprogrammed state;
Figure 7 is a state diagram of known FETs with floating storage gates;
Figure 8 is a schematic side-sectional view of a FET in accordance with the invention to illustrate erasing operations;
Figure 9 is a graph iilustrating the relationship between the storage gate voltage and the insulator dimensions for a FET in accordance with the invention;
Figure 10 is a schematic side-sectional view of another embodiment of the invention;
Figure 11 is a schematic plan vi~w of the embodiment of Figure 10;
Figure 12 is a schematic plan view of part of a further embodiment of the invention;
Figure 13 is a circuit djagram of another store matrix using FETs in accordance with the invention;
Figure 14 is a schematic side-sectional view of one of the FETs used in the storage matrix of Figure 13;

Figure 15 is a schematic plan view of the FET of Figure 14;
Figure 16 shows another storage matrix using FETs in accordance with the invention; and Figure 17 is a schematic side-sectional view of one of the FETs of the storage matrix of Figure 16.
The n-channel storage FET shown in Figure 1 has a floating storage gate Gl (floating, that is, in the electrical sense~ which is surrounded on all sides by an insulator Is.
The substrate HT of this storage FET which is produced by integration techniques, is p-doped and has two n-doped zones forming the drain D and the source S ~these letters being located in the Figure adjacent the connections to the re-spective zones). Between the drain and the source a channel K is formed in the substrate HT when the FET is driven into its conductive state. As a special feature, this storage FET is also provided with a control gate G2 which can be controlled externally via a connection A.
In the storage FET illustrated, channel injection is used. Thus, in its low-conduction state (or also in its high-conduction state, as hereinafter described) the chan-nel K, for example at the position V shown in Figure 1, is provided with a zone in which the local longitudinal field strength between the drain and the source is substan-tially stronger than in the remainder of the channel K.
Because of this localised high field strength at the position l~r704Z7 V, an acceleration region V is formed in the channel K at this point in which the free electrons flowing through the channel are heated to such an extent, e.g. to an energy of 3.6 volts, that some of them leave the channel K at this point V or in the immediate vicinity thereof, penetrate through the insulator IS and negatively charge the storage gate G1. This acceleration region V can, for example, be produced in known manner as already described above, by driving the storage FET through the connection A of its control gate G2 with a positive voltage, in order to form a channel.
There are other possible ways of producing accelera-tion regions V of this kind in the channel K and therefore producing channel injection. The acceleration region can, for example, be formed by a major spatial inhomogeneity in the channel width, i.e. by a radical, localised reduc-tion in the channel width at the location V (e.g. of wedge shape) and/or by a radical local thickening of the insu-lator Is at that point. Through such an inhomogeneity in the channel, there is produced (even ~hen the channel is in the high-conduction state) an increased longitudinal field strength localised at this positionJ so that heated electrons (particularly large numbers when the channel is in the high-conduction state) can penetrate from this loca-tion to the storage gate G1. The storage gate is the more q~ickly charged by heated electrons, the greater the ~UI~Z7 e~tent of inhomogeneity and the heavier the drain-source current. This has been discussed in our United States patent 4,087,795 (Figure 9-15).
The embodiment of the invention illustrated in Figure 1, relates, therefore, to an n-channel storage FET with a floating storage gate G1 surrounded on all sides by an insulator Is. The storage gate G1, when programming takes place, is negatively charged by channel injection, i.e.
by electrons heated in an acceleration region V of the channel K. During programming, it is adv~sable to positive-ly charge the control gate G2 so that, between the acceler-ation region V and the storage gate G1, there is a poten-tial which will accelerate these electrons. The storage gate C1 of this embodiment after programming (see references 1 or q in Figure 2 as well as reference 1 in Figure 3) and especially during read-out of the state of the storage FET, by virtue of its negative charge and by induction, acts upon the drain-source region K in such a way as to inhibit the drain-source current rather than assist it.
This inhibition of the current leads to an interruption in current flow if the storage FET has a depletion-type chan-nel ~see curves Glp, G10 in Figure 2 or G10, Gln in Figure 3~. The curve Glp in Figure 2 corresponds to a storage FET in accordance with the invention ~hich has a depletion-type channel in the unprogrammed state. On programming (see reference 4 in Figure 2 and reference 1 in Figure 3), 10'7() ~27 the storage gate Gl is negatively charged, so that the storage FET acquires the properties of an enrichment type FET in accordance with the curve G10 of Figure 2, or even the properties of a hitherto unknown FET with a so-called "blocking channel", corresponding to the curve Gln in Figure 3. When exhibiting this blocking property, by programming of the storage gate, the channel K is driven far into its completely blocked condition so that the storage FET is only driven into its conductive state by a control gate control voltage which is greater than the threshold value Up.
If the storage FET in accordance with the invention is already of the enrichment type when in the unprogrammed state, i.e. if it has an enrichment type channel (see Figure 2, curve G10) then the programming 1 will produce blocking properties in accordance with curve Gln of Figure
2, in this FET, also.
A storage FET in accordance with the invention which has blocking properties in the programmed state is there-fore distinguished by the fact that in the programmed state the channel would block even if, for example, owing to inadequate insulation, the storage gate Gl were to discharge to some extent over a period of time and even if control voltages U-G2 were to be applied to the externally controll-able control gate G2 which are below a relatively high voltage threshold value ~see Up). Blocking type FETs of 1070~Z7 this kind have not been known hitherto and equally unusual is the behaviour of the storage FET in accordance with the invention in this blocking condition. Because every stor-age FET in accordance with the invention, irrespective of the constitution of its channel, can be driven far into its blocking state when programming takes place, so that after programming it in each case exhibits blocking charac-teristics, all embodiments of the FET in accordance with the invention can be so operated that gradual discharge of the storage gate Gl due to inadequate insulationl and also due to residual charges trapped in the insulator Is, do not generally have any disturbing influence upon the amplitude of the signals produced at the time of read-out of the storage FET. The storage FET in accordance with the invention is therefore particularly insensitive to disturbance when it is driven at the time of programming, far into its blocking range, which is possible with the FETs in accordance with the invention.
A plurality of storage FETs Tl to T4 in accordance with the invention can be combined to form a matrix as shown in Figure 4, in which there is only one storage FET
in each storage cell. Then, during read-out, all the programmed and all the unprogrammed storage FETs can be driven into the non-conducting state by the application of appropriate voltages. An exception is the unprogrammed storage FET selected for read-out, to whose storage gate, via the relevant row control line X, a read-out potential not exceeding the threshold value ~p ~see Figures 2 and 3) is applied, driving its channel into the conductive con-dition. This storage FET, during read-out, should conduct in the unprogrammed state and block in the programmed state. If the storage FET is of the enrichment type in the unprogrammed state, in other words has an enrichment type channel, then for this purpose a small positive read-out potential on the row control line X will suffice. In the case of storage FETs with depletion type channels ~see Figure 3), earth potential will suffice as the read-out potential, so that a matrix with storage FETs of this kind is extremely easy to operate. When the read-out takes place, a corresponding signal is fed to an output amplifier LV in each case from E via S0, via the drain-source region of the selected storage FET and via the column switch, T5 or T6, which signal corresponds to the storage condition of the storage FET.
This matrix is thus of particularly simple construction and is particularly simple in operation. Again, programming of the storage FETs in the matrix is easily arranged; to the control gate of the particular, selected storage FET, an adequately high positive potential is applied in order to generate the accelerating voltage between the storage gate and the acceleration region V, and via the associated column control line Y, for example via one of the column 1(r704~7 switches T5 or T6, a channel voltage is ~pplied so that a current flows through the drain-source region of this selected storage FET, in the present matrix from the cir-cuit point SO, i.e. from Ru or Su, to the relevant column control line Y and onwards to the programming channel vol-tage source Us. This current flow causes the heating up of electrons in the channel of the selected storage FET, and these, through the mechanism of channel injection, negatively charge the associated storage gate. The embodi-ment having a blocking type channel in the unprogrammed state is also suitable use in building this kind of matrix, the matrix advantageously being operable in the same way although the read-out potential on the row control line X must be correspondingly higher so that small positive disturbing voltages on the line X do not cause any problem.
The special advantages of this blocking-channel storage FET will be discussed below.
The storage FET in accordance with the invention is conductive in the unprogrammed state (whether it be in a high conduction state or virtually non-conducting) so that if the storage FET in accordance with the invention has a depletion type channel in the unprogrammed state, then it is sufficient for the storage FET to have a storage gate G1, the control gate G2 no longer being required for the blocking and conducting states of the storage FET to be un-ambiguously assigned to respectiYe ones of the two programming states. Even if, after erasing ~2 in Figure 3, for U-G2=0 and 3 in Figure 2 for U-G2=0) rssidual charges are present, for example, on the storage gate or in the insulator, of a kind which has a disturbing effect upon the channel (see the disturbing shi~t R in Figure 2), allo-cation isstill unambiguously possible because, when pro-gramming takes place, the storage gate is again ~see curve Gln in Figure 3 for the value U-G2=0) capable of being driven far into the fully blocking range of the storage FET
and therefore exhibits blocking characteristics in the programmed state. Matrices with storage FETs of this kind are preferably equipped with storage cells which in addi-tion to the store in accordance with the cells shown in Sol. State Electronics 17 (1974) page 528, Figure 21, contain a further controllable FET.
From the article in Sol. St. Electronics 17 ~1974) 517 to 529, in particular Figure 3~b) and Figure 5 with the associated description, it is evident that the overlap between drain and storage gate on the one hand, and between source and storage gate on the other, has an affect upon the way in which the storage gate is charged by heated charges. In one embodiment of the inventionS it is also arranged that the capacitance between the drain and the storage gate is made a great deal larger by a correspondingly large overlap between these two parts of the storage FET, than the capacitance between the source and the storage 107(~4Z7 gate. In this way, the storage gate is more strongly influenced by the drain potential than by the source poten-tial. Because the source is normally negative with reference to the drain, the storage gate in this embodiment is cap-acitively supplied by the drain with a positive potential.
Thus, ~his overlap reinforces the mechanism of channel in-jection by virtue of the fact that a positive voltage attract-ing the heated electrons is produced on the storage gate Gl.
In another embodiment of the invention, in which a control gate is used which is in direct conducting commu-nication with the drain, the storage gate has a similar effect to that produced by an overlap between drain and stor-age gate. Such a control gate has the same kind of effect as the previously described overlap between the drain and the storage gateJ but to a much more marked degree. The area of overlap between the drain and the storage gate is, in other words, much larger in this casé than in the previously described embodiment, being in fact approximately the same size as the area of the storage gate which is covered by tha control gate.
In this embodiment, because of the particularly strong capacitive coupling between the drain and the storage gate, the supply of positive potential to the storage gate at read-out and in particular during programming is particu-larly high. In ~his embodiment, therefore, the acceleration 1~7(~427 voltage between the acceleration region V, ~Figure 1~
and the storage gate Gl is particularly high, so that the storage gate Gl is correspondingly charged with heated electrons to a very substantial extent.
In a further embodiment of the invention, the control gate G2 is not connected to the drain. At the time of programming, the control gate is supplied with a more posi-tive potential then the drain so that because of the strong capacitive coupling between the control gate and the storage gate, the latter is, in this case, provided with a parti-cularly high accelerating voltage for the heated electrons.
Preferably, the shortest possible channel length K is used, for example, 1 to 3 microns long. A channel length of less than 10 microns is recommended in all cases. The shorter the channel length, the lower is the overall vol-tage required at the time of programming between the drain and the source. If this overall voltage exceeds a critical value, i.e. if the length of the channel exceeds a correspond-ing critical value, then the p-n junction between the drain and the substrate will easily be driven when not required into its blocking condition by the induction effect of the electrons stored on the storage gate Gl, so that unwanted holes heated up in this p-n junction by the avalanche effect, can penetrate to the storage gate Gl and discharge it. This undesired discharging of the storage gate if the channel is too long, occurs in particular 1070~27 because with too long a channel the programmed storage gate Gl is often charged to a more negative potential than the drain, so that the channel K is interrupted at the p-n junction bctween the drain and the substrate. HoweverJ an ade-quately high negative char~e on the storage gate is difficult to achieve when the channel is long, in particular because of the discharging produced by holes arising from the avalanche effect, unless the control voltages on the control gate G2 are made unusually high during programming.
The use of a short channel in the FETs of the invention therefore has the particular advantage that it can easily be operated at a relatively low operating voltage between the drain and the source and with a relatively low control voltage on the control gate G2. It has been found, too, that the substrate HT, of the storage FET should, if possi-ble, not be too conductive, but should preferably having a specific resistance which is substantially in excess of 1 ohm. cm, e.g. 3 to 10 ohm. cm. The higher the specific resistance, the smaller are the disturbing capacitances, in particular between the drain and the substrate, on the one hand, and between the source and the substrate, on the other hand. It has been found that a high specific resistance on the part of the substrate HT has little or no inhibiting influence upGn channel injection.
Figure 6 illustrates an embodiment of the invention in which the FET exhibits blocking properties in the ~070~7 unprogrammed state. ~n the surface of the normally p-doped substrate HT, in the region of the channel K between the drain and the source, a p -doped layer is produced, for example, by ion implantation prior to the manufacture of the drain and the source, in which the channel K is formed when the FET is in the conductive condition. Because of the p -doping of this layer in the channel region of the FET, the channel K exhibits blocking properties. In other words, even in the unprogrammed-state of the storage gate Gl, the control gate G2 must be supplied with a rela-tively high, positive potential, namely a potential which exceeds a positive threshold value, in order to fully com-pensate for the effect of the holes collecting in the channel K as a consequence of the p -doping. It is only after this compensation has been effected that it is possible for free induced negative charges to collect in the p -doped channel region K. Above this threshold value, therefore, the n-channel K goes conductive between the drain and the source. Thus, this storage FET, even in the unprogrammed state, blocks, as it were, to an excessive extent, because uncompensated holes produced by the p -doping have collected in the channel region K, since even in the unprogrammed state, the storage FET has been driven far into its blocking region when the potential applied to the control gate is zero. During the programming of this storage FET the blocking channel K is unusually, driven still further into the blocking 2~

state. In Figure 5, the curve ~10 illustrates the blocking property of this storage FET in accordance with the inven-tion (shown in ~igure 6) prior to programming. The pro-gramming 1 causes the storage FET to acquire the even more marked blocking property represented by the curve Gln. In order to drive this storage FET into the conductive state after programming, it is necessary to apply to the control gate G2, in accordance with the curve Gln, a very high positive voltage indeed, which compensates both for the effects of the negative charges stored in the storage gate Gl, and for the effect of the holes collecting in the channel K because of the p -doping there.
To read out this form of storage FET, which has a blocking type channel in the unprogrammed state, the control gate G2 can be supplied with such a high positive potential, falling between the curves G10 and Gln, that the drain-source region reliably conducts should the storage FET be unprogrammed (corresponding to curve G10) but that the drain-source region K reliably blocks should the storage FET be program~ed, in accordance with curve Gln.
It is an advantage of this embodiment that both for programming and for read-out, a relatively high positive voltage is required, so that superimposed parasitic voltages and unwanted residual charges, in particular in the insulator Is, cannot produce any disturbances during read-out or programming.

2~

This embodiment is therefore particularly resistant to disturbance, even in a situation where, due to frequent discharge and reprogramming of the storage gate Gl, certain shifts have occurred, in particular in the curve G10, as indicated at R in Figure 5. This type of storage FET with a blocking type channel is particularly suitable, as already indicated, for the building of a matrix in accordance with Figure 4, since, because of the high security against disturbance, even the unprogrammed storage FETs are all reliably non-conducting both in the programmed and the unprogrammed states and in particular when U-G2=0, even after frequent erasing and reprogramming. The signals read out from the matrix are correspondingly unambiguous and reliable. Moreover, a matrix designed in this way exhibits only a correspondingly low power loss because, owing to the security against disturbance, all the storage FETs reliably block for U-G2=0, both in the programmed and in the unprogrammed state, irrespective of how frequently erasing and reprogramming have taken place.
Storage FETs with an insulated, floating gate which exhibit a blocking type channel in the unprogrammed state have not hitherto been described. The same applies to ordinary FETs with no storage gate Gl, but which have a blocking type channel.
The FETs in accordance with the invention as already mentioned, can also be erased again. The storage gate Gl, in other words, can discharge again through the avalanche effect. For this purpose, to the blocking p-n junction betwcen the substrate ar.d the drain a voltage must be applied which produces breakdown at this junction. At the same time, a negative voltage or earth potential is prefer-ably applied to the control gate G2. The charges generated by the avalanche effect then discharge to the storage gate Gl. Again, using corresponding, compensating control vol-tages on the control gate G2, the result can be achieved that after the erasing of the storage gate Gl and despite the possible presence of disturbing residual charges and other similar disturbances, (indicated at R in Figures 2 and 5) the channel acquires, with a high degree of reliability, the properties it is sought to achieve in the unprogrammed state, irrespective of whether the storage FET exhibits a blocking type channel in the unprogrammed state or an en-richment type channel, or a depletion type channel.
The electrical erasure of programmed FETs in accor-dance with the invention will now be described in more detail.
In general, the prior art refers to discharge of the charged (i.e. programmed) storage gate of known storage FETs by optical means. In addition, discharge by electrical means, that is to say either by the avalanche effect or by a special form of channel injection (i.e. by means of compensating charges which are emitted in the case of the avalanche effect by breakdown of the p-n junction between 1070~

the channel and the drain or source, or in the case of challnel injection, are emitted for example from zones within the near-blocking channel which are highly depleted in charges is described, for example, in IEEE J. Sol. St. Circ.
SC7, No. 5, October 1972, page 370 Figures l and 2, with the associated description. In both these known types of discharge, the charges emitted penetrate through the insu-lator to the storage gate.
When using the avalanche effect, however, the energy loss, namely the heat produced at the p-n junction in the breakdown state, is undesirably high so that the erasing efficiency is low. Electrical erasing can only be effected slowly. Much the same applies when using channel injection for erasing. In both these known methods of erasing, therefore, high losses occur in the drain-source region.
Because of the consequent large amount of heat produced in this region, the simultaneous erasing of a plurality, or indeed all, of the programmed storage FETs in a store, is made difficult if not impossible, since the heat pro-duced can give rise to operating faults and even to the destruction of this kind of storage FET.
In addition, there are other known electrical possibilities so far as the discharge of programmed storage FETs is concerned.
In an article in J. Appl. Phys. 40 (1969) pp. 278-283, the Fowler-Nordheim tunnel effect has been described.

According to this, electrical charges, especially electrons, can penetrate through specific insulators, e.g. Sio2; there appears to be a linear rela-tionship between the thickness of the SiO2-layer and the voltage required, at layer thicknesses between some few hundred Angstrom unlts and 1500 Angstrom units. The voltage producing this penetration can be a direct voltage, the storage gate being formed by either a metal layer or a semiconductor layer, in particular polycrystalline silicon.
In Proc. 4th Conf. Sol. St. Dev. Tokyo 1972, Suppl.
J. Japan Soc. Apl. Phys. 42 ~1973), page 163, left-hand column, penultimate and last paragraphs, the utilisation of this effect to erase storage gates in p-channel storage FETs is referred to. Presumably, of course, in this case it would be exclusively a discharge by the avalanche effect from a blocked p-n junction, or perhaps also by means of the gate surface effect referred to below, which would be achieved, i.e. a discharge by means of a special heating-up of charges in the storage gate itself, due to an erasing voltage pulse. This article, in other words, recommends that by way of drive voltages, pulse-type erasing voltages having appropriately high voltage levels should be used.
When using the Fowler-Nordheim tunnel effect, however, it is fundamentally possible to produce the discharge simply by the application of a direct voltage between the storage gate and the channel, or source or drain, i.e. between 1~70~Z7 the storage gate and the main path (the application of a direct voltage in order to erase the storage gate, can be cffccted particularly simply, which is an advantage). This advantageous application of a direct voltage as the erasing voltage for programmed storage FETs is consequently not disclosed in this article, the disclosure being concerned only with an application (untypical so far as this tunnel effect is concerned) of erasing voltage pulses, suggesting another discharge effect.
It has now been recognised by the Applicants that a feature of the discharge of the storage gate in programmed storage FETs, by means of the Fowler-Nordheim tunnel effect is that charges flow out of the storage gate through the insulator into the channel, or to the drain, or to the source, this outflowing current of charges of one polarity having superimposed upon it a current, flowing in the opposite direction, made up of charges of the opposite polarity which current flows from the source or the drain or the channel and penetrates through the insulator to the storage gate.
The special feature of the use of this tunnel effect there-fore resides in the fact that in contrast to the known methods of electrical discharge previously-described, charges flow not only towards the storage gate through the insulator in order to neutralise the charges thus far stored in the storage gate, but also that charges which were hitherto serving to charge the storage gate penetrate through the 1070 ~2 ~

insulator in the direction away from the storage gate.
Again, from articles in J. Electrochem. Soc, Sol. St.
Scicnce and Techn. 119 (1972) 597 to 603 and 11 Annual Re.
Phys. 1973, 163 to 169, the further kind of discharge pre-viously referred to and designated in these literature references as the gate surface effect, is described. In this case, storage gates of semiconductor material, in particular ones of polycrystalline silicon which may also be wholly or partially p-doped, are used. Discharge is produced in this case, not by means of direct voltages, but by using erasing voltage pulses. These pulses are applied between the control gate and the source or drain, or the channel, so that accelerated charges of corresponding polarity, in particular electrons, can flow from the storage gate through the insulator to the main path. By virtue of the outflow of electrons, therefore, a hitherto charged, programmed storage gate can be electrically discharged.
Usually, a plurality of such erasing voltage pulses, i.e.
an erasing voltage pulse train, is required to erase the originally programmed storage FET completely, because with each erasing voltage pulse only a small part of the stored charge normally flows away.
Investigations carried out by the present Applicants on storage FETs with storage gates and control gates have shown that, in particular during the steep leading edge of the applied erasing voltage pulse of appropriate polarity, 1~70~Z7 in the storage gate ~which has to be made adequately thick for the purpose, e.g. a thickness of 10,000 Angstrom units) scl)arcltion occurs bctween the freely mobile negative and positive charges present there. In so doing, the particu-larly numerous positive holes produced by p-doping flow to that storage gate surface which is remote from the channel i.e. faces the control gate, and the negative electrons flow to the opposite storage gate surface which faces the channel. This very rapid separation of the charges initially compensates for the high field strength within the storage gate semiconductor layer only to an incomplete extent, in particular at that surface of the storage gate which faces the channel where a hole depletion zone develops. If the erasing voltage pulses are of sufficiently high amplitude, this uncompensated field strength can be of such magnitude that free electrons present at this surface are accelerated away from it through the insulator to the main path i.e.
to the channel or to the drain or the source, so that they leave the storage gate and penetrate through the insulator.
Because the escape energy which electrons must have in order to flow away is significantly less than that which holes need, electrons can leave the storage gate more easily than holes. Consequently, this gate surface effect is particu-larly suited to the discharging of previously negatively charged storage gates. However, whilst the erasing voltage pulse lasts, i.e. shortly after the leading edge of this 10'7(~4Z7 pulse, t~e hitherto uncompensated field in the storage gate automatically collapses, evidently because in the storage gate adequate additional, new, free charges soon develop which more or less compensate for the field strength.
Because of this rapid collapse of the field, it is generally only in the vicinity of the leading edge of the erasing voltage pulse that there is a short outflow of some of the stored charges in a manner similar to that occurring with the Fowler-Nordheim tunnel effect in the direction from the storage gate towards the channel or the drain or source.
Gne or for that matter both these further effects effecting the erasing of charged storage gates in programmmed storage FETs by means of charges flowing out of the gate, namely the gate surface effect and, the Fowler-Nordheim tunnel effect, has or have obviously been exploited in the storage FET disclosed in German Patent Specification No.
2,356,275, although there of course the two effects are generally superimposed and this document neither describes the two effects nor draws any distinction between them.
Again, this document says nothing about the magnitude of the heat loss with this kind of electrical erasing.
The storage FETs of the invention can be repeatedly electrically programmed and also electrically erased again, and in so doing the loss power required for the electrical erasing of programmed storage FETs and applied to the FET electrodes can be made very small. Even if a plurality of storage FETs in accordance with the invention arranged in an integrated store, or even all the programmed storage FETs in such a store, the energy losses and therefore the unwanted heat produced are particularly small and conse-quently the permissible minimum erasure time is short. The outlay in terms of circuitry and manufacturing costs should be as small as possible. Investigations carried out by the applicants have shown that in this connection the Fowler-Nordheim tunnel effect and the gate surface effect are particularly suitable for the purpose, in contrast to the avalanche effect, which involves high power losses, and the channel injection mechanism which also involves not insub-stantial power losses.
Disregarding other results of the scientific invest-igation into the discharge mechanisms, this aspect of the present invention is based upon the recognition that a discharge taking place by the Fowler-Nordheim tunnel effect and/or the gate surface effect results in heat losses which are produced substantially only by the comparatively small currents penetrating through the insulator, if the substrate of the particular storage FET is floating; if the storage FET is part of a large storage chip with peripheral elect-ronic components for controlling the store also arranged on it, then only small currents should flow in the main path of the FET, e.g. from the source to the substrate, which currents generate only very little additional loss 1070~27 heat there. These weak currents generate a correspondingly small total loss heat. When carrying out electrical erasing using the avalanche effect or the channel injection mechanism, in addition to the loss heat produced in the insulator, comparatively extremely high amounts of loss heat are pro-duced in the main path also. Where these two last mentioned effects are concerned, in other words, in addition to the currents which discharge the storage gate, comparatively very heavy currents have to be produced in the main path in order to bring about the discharge of the storage gate;
in other words, in this situation erasing voltages which produce heavy channel currents have to be applied in par-ticular between the drain and the source, or between the drain or source on the one hand and the channel on the other hand> so that at least in parts of the main path, currents flow which are higher to an extraordinary degree than those encountered in the present invention.
In this embodiment> therefore> it is essentially only the erasi~g vol~age directly responsible for causing stored charges to flow away from the storage gate which is applied between the control gate ~and therefore the storage gate also), on the one hand, and the channel or drain or source, on the other hand> in order to effect erasing; the definition of drain relates in all cases to the polarity of the voltage across the main path during electrical programming by the avalanche effect of by channel injection> and not to the 1~704~7 polarity of the voltage across the main path during erasing.
The advantageously low heat production, which has been discovered for the first time by the Applicants is therefore employed. This arrangement, in addition to permitting electrical programming and erasing of the s~orage FETs which can be repeated many times also, in particular, makes it possible to reduce the time taken to effect electrical erasing of the storage FET, so that because of the small amount of loss heat involved, it is possible simultaneously electrically to erase large numbers or even all of the storage FETs in accordance with the invention contained in a store within milliseconds or seconds, with only a low energy consumption; in contrast, with the known technique o~ erasing using optical means, on the other hand, many minutes are required for complete erasure. In particular, there are two different solutions available, namely the application of the Fowler-Nordheim tunnel effect and the application of the gate surface effect, it being possible also to utilise both effects at the same time, superimposed as it were.
Both solutions are characterised in that the charged, i.e. programmed, storage gate is discharged using electrical means, viz an erasing voltage applied betw~en the control gate and the main pahh of the FET, by an effect which causes electrons stored in the storage gate, which electrons have been accelerated by the erasing voltage in the 1070~27 direction away from the storage gate into the insulator between the gate and the main path, to flow away from the storage gate through the insulator to the main path, i.e.
to the channel or to the drain or source; and in that in order to produce this effect an erasing voltage of appro-priate polarity is applied between the control gate and that ~one to the main path towards which the discharge is to be effected. In this connection, at least the potential on the drain or the source, towards which no electrons flow, can be maintained floating during erasure. This will now be explained in more detial with reference to Figures 8 and g, Figure 8 being a side sectional view of a storage FET in accordance with the in~ention and Figure 9 being a diagram in which insulator thickness is plotted against erasing voltage, when using the Fowler-Nordheim tunnel effect.
The storage FET shown in Figure 8 can be program.~ed by means of channel injection. To make channel injection possible, somewhere in the channel between the drain and the source, preferably in the neighbourhood of the source, an acceleration region acting in the longitudinal direction of the channel is formed by producing a large inhomogeneity in the channel structure, e.g. by narrowing the channel or by thickneing the insulator above this point in the channel. The current Ke which charges the storage gate Gl ~see Figure 8) can be produced by channel injection, at an , ~

107042'7 acceleration region indicated in Figure 8 at the point V
in the channel.
This current Ke is an electron current, which is nor-mally the case with channel injection, so that when pro-gramming takes placed the insulated, floating storage gate Gl is negatively charged. The insulator Is has a thickness x between the storage gate Gl and the channel and forms a barrier which has to be overcome during electrical erasing of the storage FET. In accordance with a feature of the invention, for this purpose, the charged, programmed, storage gate Gl is discharged using an erasing voltage applied between the control gate G2 and the main path of the FET by means of an effect which is responsible for accelerating electrons from the gate towards the main path.
This effect can be the Fowler-Nordheim tunnel effect or the gate surface effect, at least the drain or the source being a floating condition. The result is that the electrons stored in the storage gate Gl and accelerated by the erasing voltage in the direction away from the storage gate into the x of the insulator, flow away through the insulator x of the channel K or to the drain D or the source S. With a floating substrate, it is essentially this current between the storage gate and the main path, which is alone responsible for producing the loss heat, because, no appreciable additional loss heat is required for erasing produced by currents flowing along the 10704'~7 main path.
The storage FET shown in Figure 8 can constitute a single storage cell of a store. Because of the minimal energy losses encountered with this storage FET when dis-charged as described above, it is possible simultaneously and quickly to erase a plurality or indeed all the storage FETs in accordance with the invention contained in the store, without overheating the store or any individual FET.
Through this feature of the invention, it is thus possible, at thc expense of a particularly low outlay in terms of loss heat and time, to simultaneously erase a very large number of the storage FETs in the store with only a small outlay and energy consumption. Thus, making use of this feature of the invention, erasure is made particularly simple. It has been found that, because of contamination of the insulator which is found frequently to happen, both when using the Fowler-Nordheim tunnel effect and when using the gate surface effect for the erasing of the storage gate, it is frequently advisable to allow the electrons hitherto stored in the storage gate Gl to flow away to that zone of the main path (e.g. the source S) via which no programming of the storage gate was originally carried out.
In the example shown in Figure 8, programming takes place within the channel in the neighbourhood of the drain D
by means of the discharge current Ke. The discharge of the storage gate Gl, negatively programmed by electrons, takes lO~U42, place as indicated in Figure 8 by the discharge current Kd, towards the source S, that is to say into a zone of the insulator which is wcll removed from the zone in which the current Kc flows. The advantage of this measure is that the insulator Is is less heavily contaminated in the zone x between the storage gate Gl and the channel with each fresh programming and discharge of the storage gate, tllan it would be if programming and erasing or discharge of the storage gate, were in each case to be effected via the same part of the insulator Is. The measure in accordance with which the electrons are allowed, at the time of erasing, to flow away to that zone of the main path not involved in the programming of the storage gate, thus secures the advantage that the storage gate, and therefore the storage FET, can be reprogrammed electrically more often than would be the case if this measure were not used.
It is a good idea to allow the electrons of the storage gate to flow away to the source S during erasing, i.e.
to allow the drain to float. This has two particular further advantages. First of all, the interval between those two zones in the insulator S, through which, on the one hand, the programming and, on the other hand, the erasing takes place, is particularly large, so that the risk of conta-mination of the insulator Is is particularly small. Secondly because of the then generally particularly small interval between the acceleration region in the channel K and the 1()7~ 7 drain D, programming can be performed with only a very small outlay in energy.
The outflow of the electrons hitherto stored in the storage gate G1 is thus produced by applying an erasing voltage of such polarity that the electrons stored in the storage gate at the time of programming are accelerated towards the main path. Such an erasing voltage can, for example, be applied between the control gate G2 and the source S of the relevant storage FET, so that electrons hitherto stored in the storage gate G1 flow away to the source S. Because the source zone is n-doped, the electrons can flow away through it. The erasing voltage can also be applied between the control gate G2 and the drain D, so that the electrons hitherto stored in the storage gate G1 flow away to the drain D. By appropriate application of the erasing voltage, it is thus easy to arrange that the elec-trons hitherto stored in the storage gate should flow away to the particular selected zone of the main path which is n-doped. An advantage of thus allowing the stored electrons to flow away to the main path instead of to the control electrode G2, is that only very low voltages are needed between the two gates G1 and G2, i~e. a particularly high capacitance can be allowed between these two gates, in comparison to the capacitance between the storage gate G1 and channel K. It is proposed in United States patent 4,o87,79S (Figure 17-20) that the capacitance ''~'' 107~)4Z7 between the gates should be increased whereby particularly low voltages on the gate G2 will be sufficient for readout and programming (and also for erasing), since a change in the potential on the control gate G2 is virtually the same as a change in the storage gate potential.
The erasing voltage may, for example, be a direct voltage which is applied between the control gate G2 and the channel K or the drain D or source S. The erasing voltage can also, however, be constituted by a train of pulseswhich are applied between the control gate and the channel K or drain D or source S. Whether it is a direct voltage or an a.c. voltage which is applied depends upon whether it is predominantly the Fowler-Nordheim tunnel effect or the gate surface effect which is to be used to produce erasing. When using the Fowler-Nordheim tunnel effect, both kinds of voltages, can be used, but direct voltages are preferred, and during the entire selected time of application of the erase voltage, the discharge currents flow from the storage gate Gl to the main path until all the electrons which can be made to flow away by this direct voltage have left the storage gate Gl. It has, of course, al-ready been observed that by the application of pulse trains of similar amplitudes discharge using the Fowler-Nordheim tunnel effect can sometimes be speeded up (presumably because of the simultaneous occurrence of the gate surface effect).
Consequently, even when using this effect, an erasing voltage pulse train or a direct erase voltage with superimposed pulse train, can often be applied with advantage between the control gate G2 and the channel K or the drain D
or source S.
As previously described, discharge can also largely be produced using the gate surface effect, i.e. by the application of erasing voltage pulses having sufficiently steep leading edges and adequate amplitude, e.g. pulse train frequencies of 100 kHz to 1 MHz with a mark-space ratio of 1:1, between the control gate G2 and tha~ zone of the main path towards which the electrons 107()~27 hitherto stored in the storage gate Gl are to flow. The storage gate in this case preferably consists of polycrystalline silicon which has been p-doped.
By applying such erasing voltage pulses, as Figure 8 shows and as described above, the charges in the storage gate Gl are split. This splitting or separ-ation, however, is not sufficient to compensate completely for the field strength originally generated in the storage gate Gl by the erasing voltage pulse. In particular, at that gate surface which faces the channel and is enriched by the electrons stored for programming purposes, a depletion zone is left (de-pleted in terms of majority charge carriers), that is to say a residual, uncom-pensated field strength is left by means of which electrons to be removed from the storage gate and hitherto stored there, are accelerated towards the relevant zone of the main path in such a way that they leave t~e storage gate Gl, penetrate through the insulator Is in the zone x, and can flow away into the relevant zone of the main path. Because of the rapid collapse of the remaining uncompensated field strength at the storage gate surface, in order to completely discharge the storage gate Gl, generally speaking it is not merely one erasing voltage pulse but a substantial train of such pulses which has to be applied.
The use of the Fowler-Nordheim tunnel effect has the advantage, as compared with the use of the gate surface effect, that erasing of the charged storage gate can be performed in a single operation because it is possible to use a direct erasing voltage. When using the gate surface effect, on the other hand, if the leading edges are steep, a lower erasing voltage will often suffice. This is particularly useful in many integrated stores, because their peripheral electronic co~ponents are often only capable of supplying relatively low voltages in order to operate the store at relatively low outlay.
If it is desired to use direct voltages to erase the programmed stor-age FET, then it is often advantageous to produce this erasing voltage by means 1071~4Z7 of a constant yotential applied to the control gate G2 (in particular earth potential) and be another constant potential applied to the source. In this case, the storage gate Gl can be approximately discharged to an extent such that it later approximately exhibits earth potential. By a suitable choice of the erasing voltage amplitude and/or duration, it is possible, with this mode of operation, approximately to achieve either this kind of complete discharge or an excessive discharge, going beyond the previously described kind of discharge, of the storage gate Gl. Generally, after discharge, a predetermined potential will be required on the storage gate, for example a potential identical with the potential on the control gate, source S, drain D and channel K, if the potentials on the gate G2, the source S, the drain D and the channel K are all the same. If an excessive amount of charge were to flow away from the storage gate Gl, it would not only be the complete discharge of the storage gate Gl which would be achieved but, as it were, a reprogramming of the storage gate Gl with a potential of the reverse polarity, which, generally speaking at any rate, is not desirable. Because of the fact that with the ap-plication of a direct voltage of appropriate amplitude and duration as the eras-ing voltage, the control gate G2 acquires approximately earth potential, this kind of excessive discharge, i.e. programming with the reverse polarity, can largely be avoided, a small departure from the desired ideal discharge of the storage gate frequently having little or no adverse effect.
On the other hand, it is not difficult by applying a direct voltage as the erasing voltage, which has a potential differing radically from earth potential, to the control gate G2, to deliberately produce a different terminal condition of discharge in the storage gate Gl, if such different condition of discharge is what is required.
~ hatever the required condition of discharge may be, in any event the utilisation of the Fowler-Nordheim tunnel effect as proposed in the invention 107~142, is advantageous because at relatively low erasing voltage amplitudes, only arelatively small amount of loss heat is generated. When using the avalanche effect or the channel injection mechanism to erase the storage gate Gl, in addition to this loss heat a particularly large amount of loss heat would be generated at least in parts of the main path of the storage FET.
Much the same applies to the utilisation of the gate surface effect to erase the storage gate. Here, again the unprogrammed state of the storage gate Gl can be defined in different ways, according to reguirements. Depending upon what potential is applied to the control gate G2 and how the steepness of the leading edge as well as the number, duration and amplitude of the eras-ing voltage pulses are selected, a different discharge condition of the stor-age gate will be achieved. Thus, using the gate surface effect also, any de-sired condition of discharge of the storage gate Gl can be brought about. In particular, it is possible to produce the erasing voltage in the form of a constant potential ~in particular earth potential) applied to the control gate G2, and by voltage pulses applied, for example, to the source. The erasing voltage pulse train thus produced achieves the selected erasing of the storage gate by the flowing away of the hitherto stored charges, in this instance to the source S.
If a very lengthy train of such erasing voltage pulses is applied, and if at the same time, the control gate potential is appropriately chosen, e.g. made identical to the potential on the drain which is earth potential, then because of the very large number of erasing voltage pulses, ultimately it is possible to achieve a terminal condition of the potential on the storage gate Gl, which is fairly consistently reproducible and which, moreover, de-per,ding upon the choice of the control gate potential applied at the same time and the erasing voltage pulse amplitude, can be chosen more or less at will .

10~7042'7 In order to utilise the Fowler-Nordheim tunnel effect particularly effectively, it is often advisable, especially in the case of n-channel storage FETs which are programmed by means of the channel injection mechanism, i.e.
by negative charging of the storage gate, to choose a specific optimum insulator thickness x between the storage gate and the substrate.
This thickness x should usually be greater than a lower limiting value in order to avoid disturbances, for example, so that the charged storage gate is not partially discharged due to the electrical connection of the drain of this s~orage FET to the drain of another which is just being pro~rammed by the avalanche effect. If, for example, SiO2 is used as the insulatorJ
then it is consequently generally a good idea to choose the insulator thickness x to be greater than about 400 to 500~.
The diagram of Figure 9 shows the lower limiting value for the insu-lator thickness _. Figure 9 is a diagram in which the logarithm of the insul-ator thickness x is plotted as abscissa, while there is plotted as the ordinate the logarithm of the effective erasing voltage U which must be exceeded during erasing and is applied between the storage gate Gl and that zone of the main path, i.e. S or D, towards which the electrons are to flow away from the storage gate Gl. The curve Fl indicates by its slope of about 45 that with this insulator, SiO2, the Fowler-~ordheim tunnel effect yields an approximately linear relationship between the insulator thickness and the erasing voltage U.
This curve Fl is intersected at the lower limiting value by the curve F3.
The curve F3 was obtained, as an example, with UD=15V and UGl=-lOV (UD
being the drain voltage, and UG, the material of the storage gate Gl) with an unselected, already programmed cell Zl of a store, on programming the neigh-bouring cell Z2 which was connected to the same column line connected to the drain. So long as Fl is below F3, on programming of the cell Z2, the cell Zl will be partially erased. The optimum insulator thickness x is thus greater 10~(~4Z ~

than this lower limiting value.
It has been found that the insulator thickness x often has an upper limiting value as well~ and that the thickness x must be made smaller than this.
'I'he insulator thickness x thus must be lower than the upper limiting value at which, for example, a major avalanche breakdown commences between the source and the biased substrate, or at which, given particular se'ected values for the direct voltage supply, and the amount of electrons Kd flowing away from the storage gate as a consequence of the Fowler-Nor & eim tunnel effect, are approximately the same as the amount of holes flowing through the storage gate Gl as a consequence of the avalanche effect in the blocked p-n junction between the drain D and the channel K. When the insulator Is consists of SIO2, this upper limiting value is generally at about 1200 Angstrom units. At this upper limiting value, with accompanying major heating of the main path of the FET, a number of holes Ke flows as a consequence of the avalanche effect to the hit-herto charged storage gate Gl, which is equivalent to the number of electrons Kd which, as a consequence of the Fowler-Nordheim tunnel effect, at the same time flows away from the storage gate Gl to the main path of the storage FET, in particular to the source thereof. If the insulator thickness x is made greater than this upper limiting value, then in the example referred to, the current Ke formed by the holes and generated by the avalanche effect will exceed the electron current Kd flowing from the p-n junction between the drain and the channel to the storage gate Gl, due to the Fowler-Nordheim tunnel ef-fect. Instead of achieving a discharge Kd from the storage gate by means of the Fowler-Nor &eim tunnel effect in the required manner, in this case, dis-charge of the hitherto negatively charged storage gate Gl will take place by means of the compensating hole current Ke generated by the avalanche effect with accompanying production of large amounts of loss heat.
In addition, it is generally advisable to keep the insulator thickness iO70~Z7 x as small as possible in order that the amplitude of the erasing voltage required for erasing is similarly as small as possible, e.g. is about 40 volts (voltages of this low order can~ if required, more readily be supplied by the peripheral electronic components which control the store). The layer thick-ness should thus be only a little greater than the lower limiting value in order to enable such a low erasing voltage to be used.
The curve F2 of Figure 9, which is inclined at about 22 to the abscissa in accordance with the generally square nature of the function in guestion, illustrates the dependence of the minimum value of the voltage U
between the storage gate Gl and the drain D (plotted as ordinate) upon the layer thickness x (plotted as abscissa) in the context of the production of the hole current Kd created by the avalanche effect. The point of intersection between the curves Fl and F2 indicates the upper limiting value of the layer thickness x; above this, the hole current Ke produced by the avalanche effect exceeds the required discharge current Kd.
The optimum insulator thickness x generally lies as far as possible below this critical upper limit at which the curves Fl and F2 intersect one another. In the example illustrated in Figure 9, for the specific Figures given there, the optimum layer thickness x is about 600 Angstrom units, a departure from this value slightly downwards or upwards being permissible with-out significantly straying from the optimum value.
In order to use the gate surface effect to erase a storage FET, as already stated, it is advisable to make the storage gate Gl of a semiconductor material which is oppositely doped to the type of charges which are to be stored in it during programming. Because the storage gate is to carry negative charges, the semiconductor storage gate Gl should therefore be p-doped.
As is the case when using the Fowler-Nordheim tunnel effect, when us-ing the gate surface effect, there are also generally upper and lower limits lV704~7 for the layer thickness x of the insulator Is. The curves F2 and F3, in a particular example, had approximately the same appearance as in Figure 9.
Thc graph El, of course, had a different shape and position to that shown in l:igure 9. The shapc of the curve Fl is also dependent upon the steepness of the leading edge of the erasing voltage pulse and upon the duration of the individual pulses. Also, for low values, of x, higher field strengths are - required than is the case with higher values of x (see J. Electrochem, Soc.
Sol. St. Science and Techn. 119 ~1972) p. 598 Figure 3). The lower and upper limiting values thus obtainable, as well as the optimum value of the insulator thickness, frequently do not differ very radically from the values obtained for the Fowler-Nordheim tunnel effect, so that for an n-channel storage FET a thickness of approximately 600 Angstrom units has been found to be the optimum value for the thickness x.
Because the storage gate Gl is programmed using electrons, as Figure 8 indicates, there must be applied to the control gate G2 a potential which is negative with respect to the source S or to other parts of the main path of the transistor, in order to make use of the gate surface effect or the Fowler-Nordheim tunne] effect.

As already mentioned, the loss heat produced is particularly small if the stored electrons can flow away to the drain or the source whilst the substrate is floating. However, even if the substrate carries a biassing voltage, for example, because of the peripheral electronic components of the store, the heat losses generated in the main path of the FET are small com-pared with what happens when erasing is performed by the avalanche effect or by channel injection, as the top limiting value of the insulator thickness x serves to show.
Investigations carried out by the present applicants have shown that frequently there is at least a temporary superimposition of a hole dis-~070~Z7 charge current -Kd, flowing in the opposite direction, on the electron discharge current Kd. This superimposed hole current -Kd also has a discharging effect on the storage gate Gl. This superimposed hole current does not require a heavy current in the main path of the FET for its production. Thus there is no appre-ciable production of loss heat in the main path. Consequently, this superimposed hole current has not in general been expressly mentioned in the above descrip-tion but has been considered as part of the electron current Kd flowing away from the storage gate. (Another reason for disregarding this hole current is the desire to avoid unnecessarily complica~ing the description of the invention).
The above description should therefore be read bearing the possible presence of this hole current in mind.
In an article in the journal Proc. 3rd Conf. Sol. St. Dev. Tokyo 1971/Suppl. OYO BUTURI 41 (1972) 159, in particular Figure 8 thereof, and the associated description, a first report by a number of authors relating to an n-channel storage FET, is given a second report by the same authors in IEEE J.
So. St. Circ. SC7J No. 5, October 1972, pages 369-375, with similar contents appeared at about the same time. The FET shown in Figure 8 of the first report is provided with an electrically floating storage gate Gl surrounded on all sides by an insulator. In addition, it is provided with a controllable control gate G2. The storage gate Gl is so arranged between the control gate G2 and the main region of this storage FET that the storage gate covers only a first part of the channel, namely a part adjoining the source, although it does so over the full channel width. The control gate covers the remaining part of the sub-strate, which is electrically in series and which adjoins the drain, as well as the storage gate Gl itself. The state of the channel in the neighbourhood of the source is controlled both by the condition of the control gate and by that of the storage gate. The state of the channel in the neighbourhood of the drain, however, is controlled exclusively by the state of the control gate.

10'704Z ~

At no point do the authors explain why they use an ass~nmetrical stor-age gate. ~n the same page, and indeed on the preceding page of this report, however, some statements are made about the mode of operation of this storage F~T, some referring to Figure 6, and in that connection it should be noted that, obviously due to a printing error, in the text Figure 8 is referred to as Figure 9. In the following, discussion of this prior art, the Figure in quest-ion will be referred to as Figure 8 in all instances, in accordance with the numbering actually assigned to this Figure.
According to the description associated with Figure 8 of the prior article, heating of the electrons takes place in the pinch-off zone near the source end of the depletion zone (see the arrows indicating gate-channel field strength in Figure 6). The depletion zone is formed in those drain-end zones where the gate potential is negative with respect to the potential of these drain-end zones. Along these zones, so far as electrons in the channel are concerned, there is a gate-channel deceleration voltage which prevents these channel electrons from being emitted by the substrate surface and injected into the gate. It is only in the pinch-off zone that there is no such deceleration voltage, but instead an accelerating voltage, so that injection of the emitted electrons into the gate is made possible. Because of the gate potentials re-quired in this connection, experiment shows although relatively quick dischargeof a previously positively charged storage gate can be achieved by compensation of the stored holés using injected channel electrons, a high negative charge on the storage gate is no longer attainable in the presence of the erasing volt-ages used (see also Figure 5 of the second report by these authors, and the associated description). The slight negative "charging" of the gate, which the authors happened to notice after the first and third erasing operations was simply a side effect occurring in a narrow scatter range, which was not used for programming because of its small amplitude. Investigations by the present appli-11~7V42'~

cants on identical storage FETs, i.e. FETs having channels of the same lengthof 10 microns, (see the second report, page 370, right-hand column, first para-graph of chapter A) showed that abnormally high voltages had to be applied in order to be able to provide a reliable and adequate negative charging of the storage gate for programming purposes.
Because the authors of the two reports provide no reasons as to why they use an asymmetric storage gate, one can only speculate. The authors appear initially to have suspected that their previously positively programmed storage gate would notmerely be discharged by the electron injection taking place in the pinch-off zone, i.e. by compensation, but that the relatively fast channel electrons, particularly in the neighbourhood of the drain, i.e. in the neigh-bourhood of the drain p-n junction, generate heated holes and that such heated holes could also be injected into the storage gate, a mechanism which could slow down or even completely inhibit the discharge of the storage gate. It is probably for this reason that the authors used the asymmetric storage gate shown in Figure 8 of the first report, in the hole that no heated holes could then be injected into the storage gate. The second report, because of its particularly clear drafting, appears to have been written after the first report. From Figure 2 and the associated description of the second report, it is very clear that at this time, it was only considered necessary to use a symmetrical storage gate Gl in order to achieve the desired erasing shown in the associated Pigure 5.
In the present invention, in order to produce the induction effect which inhibits the drain-source current, appropriate negative charging of the storage gate is required. Investig~tions by the present applicants have shown that at short channel lengths, e.g. of 3.6 microns, it is possible to achieve a high negative charge on the storage gate even when using channel injec~ion.
The particular feature in this connection is that, with short channel lengths, 10'7()4~ ,`

the field strength in the channel can be made adequately high using relativelylow voltages, even without the formation of a depletion zone and without the formation of a pinch-off zone due to velocity saturation, that channel electrons are heated to such an extent that they are emitted by the channel, penetrate through the insulator and negatively charge the storage gate. Where this chan-nel injection mechanism is concerned, therefore, the potential on the storage gate can even be highly positive with reference to the drain, so that neither a pinch-off zone nor a depletion zone is produced but, in contrast to disclosures of the two reports just referred to, injection is nevertheless improved instead of being rendered impossible.
The authors of these two reports therefore simply sought to achieve (and indeed succeeded in achieving) the erasing of the originally positively charged storage gate ~see also Figure 5 of the second report). However, they did not achieve the intended, unambiguous, negative storage gate charge of for example -10 volts, which is used in the present invention and which is not merely a minor, negligible side effect but a major feature of the invention, and can reliably be used in order to produce the induction effect which in-hibits the drain-source current.
In thc publication So. St. Electr. 12(1969) pp. 981 to 987, an MNOS storage FET with two gates is shown in Figure 1. Between its control gate G2 and the main path of this storage FET which, in accordance with Figure
3 has an n-type channel, a second intermediate controllable gate is arranged which covers only a part of the channel adjoining the source. The remaining part of the channel adjoining the drain, as well as parts of the intermediate gate, are covered by the control gate. Thus, we are concerned here with a struc-ture similar to the previously mentioned storage FET described in the first report with the distinction that we are here dealing with an MNOS storage FET
without any channel injection and in which, moreover, the intermediate gate is 10'70~

not floating but is externally controllable. However, MNOS storage FETs, as com-pared with storage FETs having an insulated floating storage gate, have the disadvantage that, due to charge collapse, they lose their programmed state after a relatively short time, the more quickly the more frequently the state is read out. In storage FETs with a floating storage gate, on the other hand, the charge breakdown starts much later and, moreover, is much less dependent upon the number of read-out operations which have taken place in the meantime.
The storage FETs of the present invention can be programmed by channel injection, that is to say by means of electrons, whilst the storage gate can be discharged using electrical means, e.g. by means of the avalanche effect with a high drain-substrate or source-substrate voltage in the blocking state of the channel, or by means of other effects described hereinafter.
For example, a quartz window can be left in the housing surrounding the FET, in order to enable erasing to be effected using ultraviolet light, alternatively a cheap plastic housing can be used.
In a preferred form of storage FET in accordance with the invention even with excessive erasing i.e. positive charging of the storage gate with holes, after the erasing has taken place, the main path of the storage FET which car-ries the read-out drain-source voltage, i.e. the drain-source region, is non-conductive as lo~g as its control gate carries no potential which is positivein relation to all the channel zones directly controlled by it, i.e. as long as it is, for example, at the source potential. If the control gate car-ries an adequately high, positive potential, then the main path of the storage FET in accordance with the invention, which region carries the read-out drain-source voltage, will be conductive if the device is unprogrammed - i.e. is erased or over-erased. When carrying the read-out drain-source voltage, however, the main path will, despite the presence of a positive potential on the control gate, be non-conductive if the storage gate has been programmed by electrons. If, how-Z ~

evcr, the control gate carries a potential which with reference to at leastone of these channel zones, is negative or approximately the same, then the main path when carrying the read-out drain-source voltage, will, irrespective of whether the storage gate is erased, excessively erased or programmed, be non-conductive in all cases be non-conductive or at least only in a state of low conduction.
Such a FET is provided by a special embodiment with an asymmetric storage gate, this FET being operated in a different manner to that utilised in the prior art. The storage gate covers only a part of the channel, although it extends, over the full channel, width, this part containing that point in the channel which, through the mechanism of channel injection, emits heated electrons during programming, or at any rate being adjacent to it. The control gate, but not the storage gate, covers the remaining part of the channel, which is connected electrically in series, so that the state of the first part of the channel is controlled both directly in accordance with the state of the control gate and indirectly in accordance with the state of the storage gate, whilst the state of the rest of the channel is directly controlled only by the state of the control gate.
Thus, in this embodiment, the channel location which as a consequence of channel injection emits electrons and which may be located, for example, in the neighbourhood of the drain, is covered by the storage gate, or the part of the channel which is covered by the storage gate adjoins this channel location. Consequently, the emitted, heated electrons can readily charge the storage gate. The electrons emitted as a consequence of channel injection are primarily used for programming, i.e. to charge the storage gate, instead of for erasing, i.e. discharge of the storage gate. In addition, it is arranged that, because of the negative charge on the storage gate, the main path of the storage FET, i.e. its drain-source region, is driven into the blocked or excess-107042 ~

ively blocked state. The negative charging of the storage gate thus means that, in the case of an enhancement FET, for example, (and even with exces-sive erasing of the storage gate, i.e. with positive charging of the storage gate with holes) the application of the source potential, e.g. earth potential, to the control gate, generates no current in the main path of the FET ~car-rying the read-out drain-source voltage) because the remaining part of the channel is non-conductive, irrespective of the state of that part of the channel which is controlled by the storage gate. The same applies, with correspondingly modified potential, to a depletion-type FET and to a FET
with a blocking type channel.
This will be explained in more detail with reference to Figures 10 to 12, of the drawings.
The longitudinal section shown in Figure 10 is taken through an n-channel storage FET of the enhancement type, and shows the storage gate Gl which is electrically floating since it is surrounded on all sides by an insulator Is. When programming takes place, the storage gate Gl is negatively charged by the stream of heated electrons Ke which are generated in the channel itself at the location V. The storage gate Gl therefore, after negative charging in this way, and in particular at read-out, acts inductive-ly to inhibit the current flowing through the main path S-D, the effect being the more marked the shorter the interval. The storage FET additional-ly contains controllable control gate G2. Between the control gate G2 and the main path D-S, in the case of the example shown in Figure 10, the stor-age gate Gl is arranged in such a way that it covers only a first part Kl, of the channel, in this case adjoining the drain. This coverage extends, however, over the full width of the channel. This channel section ~1 con-tains the location V which~ by channel injection occurring at the time of programming3 emits the heated electrons Ke. The remaining part K2 of the 107U4Z*

channel is covered by the control gate G2 but not by the storage gate Gl,this remaining part K2 adjoins the source.
The state of the first char.nel section Kl is controlled both dir-ectly by the condition of the storage gate and indirectly by the condition of the control gate which is capacitatively coupled to the storage gate; the capacitative coupling of the two gates is the tighter the shorter the interval y between the two gates and the larger the area of mutual overlap between them.
The state of the remaining channel section K2 is controlled directly only by the state of the control gate, the control being the more effective the shorter the interval z between the control gate G2 and the remaining channel section K2.
The mutual overlap between the gates can also be arranged outside the plane of section of the FET illustrated in Figure 10, instead of within this plane of section in the manner actually shown in this Figure.
The channel in the storage FET illustrated therefore has the two sections Kl, and K2, which are electrically connected in series. If, there-fore, the storage FET is not supplied via its control gate terminal A with a read-out potential which is clearly positive in relation to the source potential, i.e. if, for example, the source potential is simultaneously ap-plied to the control gate terminal A, then the remaining channel section K2 will be in its non-conductive state. Irrespective of the state of the first channel section Kl, the remaining channel section K2 and therefore al-so the main path S-D, will in every case be non-conductive. Thus, as the read-out result, irrespective of the condition of the storage gate no urrent will flow in the main path irrespective in particular of whether the storage gate is charged with electrons, or whether the ctorage gate is discharged or whether the storage gate has been excessively erased, i.e. is charged with holes. Even excessive erasure, so that the first channel section Kl is driven into the conductive state, cannot, in the case of 1070~2 ~

the present embodiment, result in the read-out voltage between the control gate and the channel producing false read-out results.
If, on the other hand, the control gate terminal A is supplied with a read-out potential which is adequately positive with respect to the source potential, then the whole of the remaining channel section K2 will be driven into the conductive state irrespective of the state of program-ming of the storage gate Gl. Simultaneously, the first channel section Kl, irrespective of the state of programming of the storage gate Gl, will, because of the capacitive coupling between the two gates, be either conduc-tive or non-conductive. It will be non-conductive if the storage gate Gl has been programmed by means of electrons, but will be conductive if the storage gate Gl is at least approximately in the discharged or excessively discharged, i.e. positively charged, state.
Thus, if, after erasing, the storage gate Gl is not fully uncharged, but has been excessively discharged and therefore carries a positive charge, in the embodiment described, reliable read-out is nevertheless possible be-cause the main path S-D shown in Figure 10, is, on the one hand, only con-ductive, in the presence of a positive read-out potential on the terminal A, and, on the o:ther hand, is non-conductive in the presence of potentials which by comparison are negative and correspond to the non-read-out command, irrespective of whether the storage gate is completely or excessively dis-charged. Moreover, the reliable read-out described can be achieved using the indicated mode of operation even for a storage cell containing only one storage FET in accordance with the invention and belonging to a store which contains a plurality of storage FET cells in accordance with the invention, without any need to arrange an individual control FET in series with the storage FET in question, even if excessive erasing is allowed (see ~igure
4). ln the case of the embodiment described, it is possible to achieve a ~7()42, particularly small unit volume per storage cell and to reduce the number ofcomponents required per storage cell whilst only imposing very small demands upon the tolerances of the electrically controlled erasing operations. The wide tolerances are due in particular to the fact that, in accordance with the invention, excessive erasing can be permitted.
Channel injection can be brought about by the method of generating heated electrons in the channel in the neighbourhood of the drain ~see the corresponding channel location V of Figure 11)~ For this purpose, it is pos-sible, for example, to apply to the control gate, via the terminal A, a potential such, and to the main region D-S a voltage such, that at the re-levant location V in the first channel section Kl, the velocity saturation of the channel electrons is brought about, until the desired complete program-ming of the storage gate Gl is achieved. It is equally possible, however, (see Figure 12) additionally to form an acceleration zone V in the channel, e.g. in the neighbourhood of the drain, this acceleration zone being formed in the embodiment of Figure 12 by a restriction V in the channel. Instead of this kind of restriction V, or for that matter in addition to it, the acceleration zone can also be constituted by a different kind of disuniformity in the channel at this channel location, e.g. by the radical thickening of the insulator between the storage gate and the channel at the location V.
The storage FET illustrated need not only be programmed using electrical means but can also be erased, electrically for example, by utilising the avalanche effect, if the first channel section Kl covered by the storage gate Gl, adjoins the p-n junction between the channel, on the one hand, and the drain or source, on the other, this p-n junction being driven into the breakdown condition in its blocking state so that heated holes from the p-n junction penetrate through the insulator to the storage gate. ~hese holes injected into the storage gate Gl neutralise for the negative charge present 1070~Z7 thereon, so that electrical erasing is brought about. As already mentioned, itis possible without any dangerto the operationofthe storage FET in accordance with the invention,to allow over-compensationofthe negati~e charge on the storage gate. Because over-compensation is not damaging, the tolerances as re-gardsthe erasing voltage can becorrespondingly wide. Moreover, especially by using high erasing voltages, the dischargingof the storage gate Gl can be acce-lerated, i.e. can becarried out in a particularly short time. Moreover, the storage FET can also be erawed by other known techniques, e.g. by the use of ultraviolet light or X-rays.
Erasing can also be performed byutilising the Fowler-Nordheim tunnel effect or the gate surface effect. The flowing away ofthe electrons can take place to the first channel section Klif the latteris designedas a depletion chan-nel and istherefore n-doped,or,fGrthat matter, to the source Sor to the drain D, i.e. to n-doped zones. For this purpose, the erasing voltage must be applied between the terminal A onthe one hand and the terminalS orD on the other; in addition, the potential of the other zone D or S, or the potential of the sub-strate ~T, can be arranged tofloat if a depletion channel has not been provid-ed. The definition of drain and source here relates to the direction of cur-rent flow in the main path during programming or during read-out.
This utilisation of an effect which accelerates the movement of stored electrons from the storage gate Gl towards the main path of the FET, has the additional advantage that the erasing voltage which has to be applied between the terminal A and the main path can often be made significantly lower than if the avalanche effect were used for erasure purposes, as already ex-plained with reference to Figure 9.
In one form of storage FET in accordance with the in~ention, it is arranged that the discharge of the storage gate can also take place towards the source S if a remaining channel section K2 is left between the source ,, ~ ~04Z7 and the first channel section Kl. For this purpose, the storage gate Gl, (see Figure 11) is arranged to exhibit laterally of the channel Kl/K2 a conductive connection LK arranged over a thick oxide layer and extending to a tongue L which covers parts of the source S well to the side of the channel.
Between the tongue L and the source S, there is a thin oxide layer. Via the conductive connection LK between the tongue L and the storage gate Gl, the latter is discharged. In particular, it is possible to utilise for this purpose three different effects, either separately or simultaneously:-1. In the neighbourhood of the tongue L, the p-n junction between the source and the substrate HT can be driven into the avalanche breakdown condition so that holes from this p-n junction flow through the tongue L to the storage gate Gl if at the same time an adequately negative potential with reference to the source terminal, is applied to the control gate G2 which is capacitively coupled to the storage gate Gl;
2. The Fowler-Nordheim tunnel effect; and/or 3. The gate surface effect, which can also be applied between the tongue L and the source S in order to erase the storage ga~e Gl. For this purpose, between the control gate G2, and therefore the storage gate Gl, on the one hand, and the source S on the other, a voltage sufficient to acceler-ate the electrons of the storage gate Gl through the tongue L into the in-sulator between the tongue L and the source S, is applied. So far as the voltage required is concerned, the conditions illustrated in Figure 9, with reference to the insulating layer thickness x between the tongue L and the source S, apply in a corresponding way. At the same time, the potential on the drain, or for that matter the potential on the substrate HT, can be arrang-ed to float, so that no electrons can flow to either of these two zones from the storage gate Gl.
The connection LK between the tongue L and the storage gate Gl ~070~ 7 should be isolated from the substrate HT by a thick oxide layer, for example 10,000 Angstrom units in thickness, so that at the surface of the substrate l~T in the neighbourhood of the connection LK, no conductive channel between the source S and the channel section Kl can develop should the storage gate Gl become positively charged with holes as a consequence of excessive discharge.
The provision of the tongue L and the electrical connection KL between it and the storage gate Gl, thus has the particular advantage that discharge of the hitherto negatively charged storage gate to the source S is possible with only particularly small heat losses and additionally at low erasing voltage amplitudes U. Programming takes place at the channel location V, i.e. well removed from the location at which discharge of the storage gate occurs, so that contamination of the insulator by charges trapped in it is negligible.
Figure 12 also shows a connection KL as shown in Figure ll. The example shown in Figure 12 is distinguished, however, from that of Figure 11 in two essential respects:-1. By the construction of the channel location 4 responsible for the channel injection mechanism, i.e. by a radical disuniformity serving as an acceleration zone;
2. By the control gate G2 which here covers only that part of the storage gate Gl in the neighbourhood of the first channel section Kl.
It has been found that, at any rate when the layer thickness y between the storage gate Gl and the control gate G2 is small, frequently a relatively small mutual overlap on the part of the storage gate will be suf-ficient, as Figure 12 shows. In this case, the overlap is less than is basically geometrically possible. Even in embodiments of this kind exhibiting only partial overlap, it is possible to achieve a degree of capacitive coupl-ing between the storage gate Gl and the control gate G2 which is often suffic-ient in order to capacitively influence the potential on the storage gate Gl through the potential on the control gate G2 and therefore to influence the 10 71)~27 state of conduction of the channel section Kl. If the first channel section Kl adjoins the drain D, then channel injection can be produced by controlling a channel which does not have such a disuniformity by the application of adequately high voltages between the drain and the source, especially by the application of an appropriately high, positive, accelerating potential to the terminal A in order to accelerate the channel electrons towards the storage gate.
If the first channel section Kl is instead arranged adjacent the source S, then programming can be performed by means of a channel injection mechanism created by a channel disuniformity. Advantageously, the applicat-ion of any capacitive load to the lead connected to the drain is avoided in the situation where the first channel section K1 has been driven conductive due to excessive erasing, as long as the remaining channel section K2 is conductive; in other words, a conductive first channel section Kl adjoining the drain, results in a certain degree of capacitive coupling between the line connected to the drain D and the terminal A, via the capacitance consti-tuted on the one hand by the storage gate Gl/control gate G2 and on the other by the conductive first channel section Kl. In this embodiment, a particular-ly small insulator thickness x between the storage gate and the channel is permissible because there is no lower limit to observe indicated by the inter-section between the curve Fl and the curve F3 in Figure 9 (which applies in a situation where the first channel section Kl adjoins the drain) under the operating conditions outlined there. Because of the particularly small layer thickness x, this embodiment of the invention can consequently be operated at particularly low voltages.
If the first channel section Kl adjoins neither the source S nor the drain D, i.e. if both between the drain D and the first channel section Kl and between the source S and the same channel section Kl, there is in each case a section of the remaining channel section K2, the latter thenconsisting of two sections then when the first channel section Kl is conduct-ive, capactive coupling of both the source S and the drain D to the terminal A is avoided. The inherent capacitance between the tongue L used for the erasing function, and the associatedmain path terminal, in this case the source S, is thus small in comparison to these connections, and therefore largely negligible. Moreover, this further embodiment of the invention has the advantage that a particularly small insulator thickness x, with consequent particularly low operating voltages, is permissible since the lower limit-ing value shown in Figure 9 can once again be disregarded in this situation,i.e. when the first channel section Kl does not adjoin the drain.
If the remaining channel section K2, or at least a portion thereof, is arranged between the drain D and the first channel section Kl; then the main path, despite the fact that the channel section Kl is conductive, can only pass current in a low-ohmic state if the control gate G2 carries a more positive potential than that applied to the drain D.
The tongue L can, especially in a further embodiment in which the remaining channel section is in two parts, also cover part of the drain instead of part of the source, so that erasing can be performed~by applying the erasing voltage to the drain D instead of to the source S.
These embodiments of the invention has been particularly described with reference to enhancement FETs. However, they can also be storage FETs with depletion-type channels. The properties pertaining to these various channels can therefore be linked with the advantages of the invention.
It has already been stated that a hole discharge current is fre-quently superimposed upon the electron discharge current, which former, because of its opposite direction of flow, also discharges the storage gate.
To simplify the description, reference will only be made to the electron dis-Z ~

charge current and, where appropriate, the description should be read as hav-ing been appropriately modified to refer to the hole current also.
The electrical erasing and also the electrical programming of the FET can advantageously be performed within a very short time, e.g. within some few milliseconds, if suitable voltage values are used; for example, they can be performed in this time at as little as 35 volts in the form of voltage pulses between the storage gate and the source on the occasion of the first erasing and within one minute, for example, on the occasion of the twentieth erasing, the measured values thus change. The outlay required for this is particularly low.
The use of an n-type channel instead of a p-type channel for the storage FET of the invention is necessary since otherwise programming by means of channel injection and subsequent erasing by means of the aforementioned effects would not be possible.
Through the measures described hereinafter, it is possible to individually erase a single storage cell of a store, comprising a FET in accordance withthe invention, without at the same time having to erase other storage cells in the store, e.g. other storage cells in the same store row.
Thus, bit by bit erasing of the plurality of bits stored overall in the stor-age matrix can be carried out. Moreover, this measure often makes it possible to simultaneously erase other storage FETs in the store matrix, in particular ones in the same store row, the appropriate voltages being applied to these selected storage cells. The constructional outlay involved for the provision of this facility is particularly small. It has been found that the desired protection against interferences is not only not impaired by the measure pro-posed in accordance with the invention but that the ability to erase only a single bit of the totality of information stored in the store makes it possible to maintain the disturbance to the other bits stored in the store at a part-icularly low value, or even entirely to avoid any such disturbance~

Z~

Such a storage matrix comprising a plurality of storage cells each comprising a FET in accordance with the invention can be formed on a substrate using integration technology. The charged, i.e. programmed storage gate of an FET is discharged electrically by means of an erasing voltage applied between the control gate and the main path of the transistor using an effect which causes electrons stored in the storage gate and which are accelerated by the erasing voltage in the direction from the storage gate into the insulator between the storage gate and the main path, to flow away through the insulator into the main path, i.e. to the channel or to the drain or the source. For this purpose, an erasing voltage is applied with appropriate polarity between the control gate and that zone of the main region to which discharge is to be effected, the control gates of the storage cells arranged in the first matrix direction each being connected to a first control line.
The second terminals of the two-terminal main paths of the storage cells arranged in the second matrix direction, are each connected to a second control line; the second control lines are not continually electrically con-nected together; and when a storage cell is erased, the erasing voltage is applied between the first control line connected to the associated control gate, and the second control line connected to the associated second terminal.
In contrast to the store shown in Figure 4, in this form of store, the second control lines are not continually electrically connected together through a common circuit point So. Because of the normal electrical isolat-ion of these two control lines, it is possible, via this kind of separate se-cond control line and via a first control line, to apply the erasing voltage to the storage cell arranged at the intersection point between these two con-trol lines, in such a way that it is simply the information in this storage cell which is erased in bit fashion, and not simultaneously the information ~704Z7 in the other storage cells connected to the same first control line, whichwould mean word erasing. This sort of arrangement thus constitutes a special, inherently advantageous system for driving an n-channel storage FET.
This form of store and the type of storage cell used therein will now be further described with reference to Figures 13 to 15.
In the store illustrated in Figure 13, n-channel storage FETs Tl to T4 according to the invention are shown forming a two-dimensional storage matrix. The matrix may, of course, contain many more than just four such storage FETs. The individual storage FETs each comprises, in addition to a controllable control gate, an electrically floating storage gate surrounded on all sides by an insulator, for example, the storage gate Gl in Figure 14.
At the time of programming the storage gate is negatively charged by heated electrons, produced in the channel of the FET itself at a channel location V (Figure 14). After this negative charging, the negative charge on the storage gate Gl acts, in particular at the time of read-out, inductively on the section Kl of the main path of the FET in such a way as to inhibit the drain-source current. After programming, therefore, the main path Kl-K2 will have been driven into an excessively blocked condition.
The charged, programmed storage gate Gl can be erased electrically by the application of an erasing voltage between the control gate and the main path using an effect which causes electrons stored in the storage gate to flow away through the insulator Is to the main path. This electron dis-charge current may have superimposed upon it the hole discharge current already referred to at the same location in the insulator. For erasure, the relevant eTasing voltage is applied with appropriate amplitude and polarity between the control gate and that ~one of the main path to which discharge is to take place, i.e. between control gate on the one hand and the drain or source or the channel on the other. In the embodiment shown in Figure 13, 1~04Z7 discharge is to be effected to the source S, i.e. ~co a second control lineY"l or Y"2.
The individual storage FETs are manufactured using the integrated technique and are combined to form a storage matrix, each individual FET for~-ing an individual storage cell therein. The control gates of the storage cells, arranged in a row in the first matrix direction, are connected together by a first control line Xl, or X2. These control lines constitute the row lines of the store. The second terminals, S in the case illustrated, of the two-terminal main paths of the storage cells arranged in a column in the second matrix direction, are connected together by a second control line Y"l, Y"2, these second control lines Y" not being continually electrically connected together ~i.e. connected together in an ohmic highly-conductive manner).
This is a first feature by means of which the arrangement shown in Figure 13 is distinguished from the arrangement shown in Figure 4. So far as the arrange-ment of Figure 13 is concerned, therefore, due to the electrical isolation, the common circuit point So shown in Figure 4, is not present. Instead, the electrically isolated corresponding circuit points SYl and SY2 are provided, which are not, however, continuously electrically connected to one another.
Erasing is performed in the store of Pigure 13 by virtue of the fact that the erasing voltage Url/Utl (for example9 Url = ~35V, utl = OV) is applied to the selected storage cell, e.g. T3, via the corresponding first control line, in this case X2, and via the corresponding second control line, in this case Y"l. The negative charge stored on the insulated, floating storage gate of the cell T3 thus discharges via the source S of this storage cell T3 to the circuit point SYl. To the other first control lines it is possible, for example, to apply ~20V whilst this is happening, whilst to the other second control lines zero potential is applied, in order to prevent unwanted influencing, i.e. erasing and programming, of the unselected storage ~704Z ~

cells T], T2, and T4. To prevent currents flowing through the main paths, at the same time the potential on the drain terminals D and the lines Yl and Y2, can be arranged to float.
By means of special switches (not shown in Figure 13) it is possible, however, to effect temporary electrical connection between the CiTCUit points SYl and SY2 and therefore to electrically connect the second control lines, for example in order to simultaneously erase several storage cells in a speci-fic row of the store. If the circuit points SYl and SY2 are electrically connected, the erasing vo~tage is applied, not only to the storage FET of cell T3, but also simultaneously to other storage FETs arranged in the same row, in this case the additional storage cell T4, so that, in this case, both the storage FETs T3 and T4 are erased via their respective sources S. How-ever, because of the normal electrical isolation between the two control lines Y", it is possible to erase information in the store bit fashion instead of simultaneously erasing the overall information contained in several stor-age cells in word fashion, for example, with the consequent need to write the new word into all the erased cells. The invention, therefore reduces the number of cell erasing operations, which, because of the frequently restricted number of erasings and reprogrammings of a cell which are possible without contaminat-ing or destroying the insulator, generally leads to an extension of the trouble-free service life of the store.
In particular, the superimposed hole discharge current component can, if it is of sufficient magnitude, obviously create local charges on the insulator at the discharge location, i.e. can generate charged trapping centres in the insulator so that at that location in the insulator at which discharge of the storage gate Gl takes place, the contamination becomes pro-gressively worse and worse from discharge to discharge. As previously descri-bed, this contamination means that with each fresh discharge, the discharge 10704'~ ~

time becomes longer and longer until, ultimately, the discharge time is solongJ e.g. several minutes, that further erasing operations have to be regard-ed as disturbed and, as it were, incapable of execu~ion. Similar changes in the times required for programming, or in the programming voltages required for the same times, are frequently observed with contamination of the insula-tor at or near the location therein via w~ich the storage gate is charged.
In order to increase the number of erasing operations and reprogram-mings which can be performed without major contamination, i.e. without dis-turbance, the measure already referred to can be employed, namely programming of the uncharged storage gate being performed as far as possible from that location in the insulator of the storage FET through which erasing of the gate is performed; smaller changes in the erasing and programming times are then observed. Because, in the store shown in Figure 13, erasing of the storage gate is to take place towards the source S~ in order to avoid con-tamination (for example due to trapping charges as already described) of the insulator Is insulating the floating storage gate~ programming should take place as far as possible from the source S. It is therefore a good idea in this situation if the channel location ~V in Figure 14) at which the electrons used to charge the gate Gl are emitted, is as far as possible from the source S.
In Figures 14 and 15, an embodiment is shown in which the storage gate of the n-channel storage FET covers only a first section Kl of the chan-nel but extend over the full channel width. This section Kl contains the channel location V at which heated electrons Ke are emitted by channel inject-ion when programning takes place. It is equally sufficient, if this first channel section Kl simply adjoins the location V. In this special storage FET, it is additionally arranged that the control gate Gl, but not the storage gate G2~ covers the remaining section K2 of the channel, which is electrically 1070~ ~
in series with section Kl, so that the state of the first section K1 of thechannel is controlled both directly in accordance with the state of the con-trol gate and the state of the storage gate, whereas the state of the re-maining section K2 of the channel is controlled directly only in accordance with the state of the control gate.
This storage FET can be so designed, that, despite the interval between the source S and the first channel section Kl, erasing of the gate Gl can take place to the source S. In Figures 14 and 15, an example of a con-venient embodiment of this kind has been shown. Figure 14 is a section taken partially in the plane MM and partially in the plane NN of Figure 15, which will be apparent from a consideration of Figures 14 and 15 together. In this example, erasing of the storage gate Gl is effected via an arm LK (see Figure 15) electrically connected to the gate Gl and disposed laterally of the channel Kl/K2, and via an overlap L electrically connected to the arm LK coupled to the source S which is separated therefrom only by a thin (e.g.
600 Angstrom units thick) insulator Is (see Figure 14). The arm LK is in turn separated from the substrate HT by a particularly thick insulating layer, e.g. 10lO00 Angstrom units in thickness, so that the negative charge carried by the arm LK cannot generate beneath it in the p-doped substrate HT any conductive channel of a kind which could shunt the region K2.
As Figures 14 and 15 indicate, the control gate G2 can be separated from the substrate HT in the channel section K2 simply by a thin oxide layer of, for example, 60~ Angstrom units in thickness. In this case, the control gate G2 produces the charges flowing in the channel exclusively over its width ~1 (Figure 15). The potential on the arm LK, because of the relatively good conductivity of the material of which this arm is formed, will be substantially identical wi~h the potential on the storage gate Gl in the neighbourhood of the first ch~nnel section Kl. The potential on the arm LK is thus only in~irectIy influenccd by the control gate G2.
In order to increase the degree of this influence, the capacitance between the control gate G2 on the one hand and the arm LK and the storage gate Gl, on the other hand, can be increased, for example by arranging them in a variant of the embodiment shown in Figure 15, the extension B2 of the control gate G2 covering not only the storage gate Gl but also the arm LK.
The control gate G2 is thus insulated from the arm LK simply by a thin oxide layer which has not been shown in Figure 15 in order not to overburden the illustration. Along the width B2 therefore, the control gate G2 is separated from the substrate HT by a thick oxide layer so that at that location neither the control gate G2 nor the storage gate Gl can produce a conductive channel in the substrate HT. Through this increase in the capacitance between the control gate G2, on the one hand, and the arm LK and storage gate Gl, on the other, the voltage between the control gate G2 and the source S can be made lower at the time of erasing than would be possible without such an increase in capacitance. I'hrough the reduction in this voltage, the tolerances in the dimensioning of the generators supplying this voltage, and their switches, can be considerably increased so that the reliability of operation of the store is improved.
The first terminals, in the case illustrated the drains D, of the main paths of the storage cells arranged in the second matrix dimensions, can be connected together by additional third control lines, Yl and Y2. These third control lines Y can advantageously be used both for programming and for read-out in a manner which will be described hereinafter.
During programming of a storage cell, e.g. T3, a programming poten-tial Ut2 can be applied to the first control line X2 assigned to this storage cell. The programming potential Ut2 accelerates the free electrons generated in the channel b~ the channel injection mechanism towards the storage gate.

1070~2 ~

In order that the channel location V can act by channel injection to emit the free electrons which charge up the storage gate Gl, the main path of the relevant store FET, in this case T3, must be supplied with a programming vol-tage, in this case Ur2/Us2, via the second and third control lines Y"l and Yl the programming voltage Ur2/Us2 bèing applied betweèn the second control line Y"l and the third control line Yl, across the switch T5 shown in Figure 13.
It has been found that the storage FETs in accordance with the invention can also be read out via the third control lines Y, without any considerable constructional outlay being required. When reading out a selected storage cell, e.g. T3 in Figure 13, a read-out potential Ut3 is applied to the first control line assigned to this cell, i.e. the control line X2, which drives the main region of the cell T3 into the conductive state, if the cell is not programmed, and which drives the main region, i.e. the first channel section Kl of the storage cell arrangement shown in Figure 14, into the blocking state if the storage cell T3 is programmed. Whether the main path of the relevant storage cell is conducting or blocking is determined by simultaneously applying a read-out voltage, e.g. Ur3/Us3, via the associated second control line Y"l and the associated third control line Yl. When read-ing out a storage cell, therefore, a read-out potential Ut3 is applied to the first control line XZ assigned to this cell T3, and an additional read-out voltage Ur3/Us3 is applied between the second and third control lines Y"l/Yl;
the current then flowing through the main region Kl/K2 and therefore through the second and third control lines Y'l/Yl, which current is mor.itored in the output amplifier LV, depends upon whether or not the storage cell T3 is pro-grammed.
The storage FET shown in Figure 14 which exhibits two differently controlled channel sections Kl and K2 which are separated from one another and arranged electrically in series, also has the advantage described earlier,than when erased it can also be excessively discharged, so that the storage gate Gl rather than being discharged becomes positively charged. The arrange-ment of storage FETs of this kind in a store matrix thus has the advantage that erasing, since excessive erasing is permissible, can be performed easily and particularly quickly, with wide tolerances as regards the erasing voltage, the erasing potential and the time during which this voltage and potential can be applied to the individual storage cells. This form of store is therefore a particularly reliable one.
As already described above, the contamination of the insulator is an undesirable phenomenon, especially because the time required for erasing then lengthens rapidly from erasing operation to erasing operation, so that ultimately erasing is completely disrupted. It has been observed that this contamination during erasing can be virtually completely avoided so that the erasing time only increases slightly, the number of undisturbed erasing operations increases considerably and therefore the service life of the storage FET is correspondingly lengthened. It is advisable in this connect-ion to perform discharge using erasing voltages Url/Utl which slowly and con-tinuously increase, e.g. rise in saw-toothed fashion over a period of 3 seconds from zero volts to their final value, e.g. 35 volts, the voltage being applied between the main path and the control gate G2. It is also possible to use a corresponding amplitude-modulated train of positive pulses for erasing, the envelope curve of the pulse train slowly and continuously increasing in amplitude.
By the use of such a slowly rising erasing voltage, instead of an erasing voltage which is high right from the start, it is possible to cause the discharge of the storage gate Gl to commence only ~uite slowly, in fact at the minimum possible erasing voltage ~see Fl in Figure 9). This discharge -7$-lO~V~;~7 is effected solely by the Fowler-Nordheim tunnel effect, the voltage applied between the storagegate Gl and the main path always being too small for there to be any possibility that, due to the avalanche effect, a hole discharge current could flow simultaneously in superimposed fashion (see the minimum voltage in accordance with curve F2 of Figure 9, which is not reached here but which is required to generate a hole discharge current). The hole discharge current is therefore absent so that thetrapping centres inthe insulator do not become pop-ulated with holes. During the slow rise in the erasing voltage between the control gate and the main path of the transistor, the electron discharge cur-rent therefore flows gradually, i.e. progressively, withoutthe voltage betweenthe storage gate Gl and the main path substantially exceeding the value corres-ponding to the curve Fl. The rise in the erasing voltage Ur/Ut should there-fore be so slow that no hole discharge current flows and the erasing time re-mains constant. Because contamination is avoidedatthe time of erasing, despite the execution offrequent erasing operationswith reprogramming thereafter, no substantial rise in the particular erasing time is any longer observed. The highest permissible value of the rate of rise in the erasing voltage can be deter-mined for the particular storage FET structure usedby tests carriedouton aspecimen.
Because of this avoidance of contamination, erasing can also be al-lowed to take place via the same insulator location at which programming hasbeen performed. Thus, with this special erasing method, it is also possible to permit the storage gate to be both programmed and erased, bit fashion, in the vicinity of the drain without causing an undesirably steep rise in the er-asing time. Accordingly, in this case, it is not necessary either to provide an arm LK and a tongue L in the neighbourhood of the source (see Figures 14 and 15) of a storage FET whose storage gate covers only the first channel section but not the remaining channel section. It is advantageous, however, in this ; situation, to arrange the arm LK and the tongue L in the proximity of the ~070~ ~

drain, if the first channel section Kl is separated from the drain by a short part of the remaining channel section K2.
m e erasing method described can also be applied in the manner des-cribed hereinafter, apart from the way in which it is used in the store of Figure 13. In this connection, the mechanism of discharge will once again be described in particular detail.
The step of allowing the erasing voltage to rise slowly to its terminal value resolves the problem of radically reducing the increase ~n erasing times which otherwise occurs from erasing operation to erasing operation, and can of course be applied to FETS according to the invention not arranged as in the store of Figure 13. Because the erasing times which are required when this step has been introduced, increase much more slowly (if they increase at all), it is possible in this way to considerably increase the number of erasing operations and reprogrammings which can be performed without distur-bance. Thus, the service life of the storage FET iS also increased because the erase times do not so quic~ly reach impermissibly high values.
The erasing voltage used can, for example be of saw-tooth form or be a pulse type erasing voltage with a very shallowly rising leading edge and a constant peak portion corresponding to the terminal value, or may for that matter be constituted by an amplitude-modulated pulse train of slowly increas-in~ amplitude. The improvements obtained in erasing, in this way, i.e. the greater freedom from disturbance, together with further developments of the invention, will now be explained in re detail with reference to Figure 16 and 17, Figure 16 showing storage FETS in accordance with the invention com-bined to form a storage matrix, and Figure 17 illustrating a special embodi-ment of an individual storage FET.
In Figure 16 n-channel storage FETs Tl to T4 are shown. The two-dimensional storage matrix can, of course, contain many more than justfour such iO70~2, storage FETs. The individual storage FETs each contain, in addition to a control gate, an electrically floating storage gate surrounded on all sides by an insulator, such as, for example, the storage gate Gl in Figure 17. The storage gate, at the time of programming by heated electrons (i.e. the stream Ke of Figure 17) generated in the channel of the FET itself by a channel in-jection mechanism at the location V in the channel, is thus negatively charged.
Once negatively charged in this way, the storage gate especially at read-out, acts inductively upon the main path of the FET, in fact in this case on the first section Kl thereof, in such a way as to inhibit the drain-source cur-rent. After programming, therefore, the main path Kl/K2 will have been driveninto an excessively blocked condition.
The charged, programmed storage gate Gl can be discharged electrically using an erasing voltage applied between the control gate and the main path, using the Fowler-Nordheim tunnel effect, the latter effect causing electrons stored in the storage gate to flow away through the insulator Is to the main path of the transistor. When erasing takes place, this electron discharge cur-rent may have a hole discharge current superimposed upon it at the same locat-ion in the insulator. The holes in this case flow in the opposite direction to the electrons, so that the hole discharge current also has a discharging effect upon the storage gate Gl.
The hole discharge current is produced substantially because of the fact that the avalanche effect is superimposed on the Fowler-Nordheim tunnel effect. This avalanche effect has been described in connection with curve F2 of Figure 9. It has been found that the radical increase in erasing time f-rom one erasing operation to another is particularly associated with the occurrence of the hole discharge current. Because of the holes, in other words, the trapping centres present ~normally unavoidably) in the insulator Is become populated with holes, and this contaminates the insulator. These holes trapped in the insulator produce an increase in the minimum erasingvoltages required to perform erasure, and in the time taken by the erasing operation.
It has been found that the radical rise in erasing times, which other-wise leads to complete contamination and complete disruption of the erasing operations, can be avoided completely or at least to a very large extent, if, when carrying out erasing, the erasing voltage (Ur/Ut in Figure 16, this vol-tage being applied between the control gate G2 and the main path of the stor-age FET T3) is arranged to rise only slowly to its terminal value. The eras-ing voltage may therefore rise, for example, in saw-toothed fashion and contin-uously over a period of 3 seconds, from zero volts to its terminal value, e.g.
+35 volts, the voltage being applied between the main path and the control gate G2. In this connection, the potential Ut can be constituted by constant earth potential, and the potential Ur by a relatively positive, rising potent-ial. Alternatively, a corresponding amplitude-modulated train of positive pulses can be used for erasing, the amplitude of these pulses also rising slowly in saw-tooth fashion and continuously, i.e. using an amplitude- modu-lated pulse train in which the envelope of the amplitude peaks rises in saw-tooth fashion, slowly and continuously, to the terminal value at which the storage gate is erased. The terminal value of the saw-tooth voltage can also last somewhat longer at a constant level iln order to continue discharge over the extra time.
By the use of such a slowly rising erasing voltage instead of an eras-ing voltage which is high right from the start the discharge of the storage gate Gl is effected slowly and progressively as soon as the voltage Fl between this gate and the main path, i.e. the drain or source, has been reached.
Because of the discharge of the storage gate which now commences, this voltage tends to fall. However, because the erasing voltage between the control gate 10704Z'~i and the main path continues to rise it nevertheless continues to be the sameas or only slightly higher than the minimum possible voltage Fl required for the production of the Fowler-Nordheim tunnel effect (see Figure 9) especially if the insulator thickness _ has the optimum value. Discharge takes place solely in accordance with the Fowler-Nor &eim tunnel effect because the volt-age between the storage gate Gl and the main region, which is approximately constant because of the small magnitude of the electron discharge current, is always less than F2, despite the slow rise in the voltage between the control gate and the main path, so that a hole discharge current due to the avalanche effect cannot flow at the same time ~compare the requisite, high minimum vol~-age F2 of Figure 9, which is not attained in the present case but which has to be attained in order to generate a hole discharge current) as long as the thickness x of the insulator Is does not reach an abnormally high value (1100 Angstrom units in Figure 9). Because of the discharge method used, therefore, the superimposed hole discharge current created by the avalanche effect is avoided. Instead, due to the slow rise in the erasing voltage, only the Fowler~Nordheimtunnel effect actually occurs, which advantageously progress-ively produces discharge of the storage gate Gl at only relatively low volt-ages.
Because in the operating method described, the hole discharge current is prevented, the trapping centres in the insulator Is are no longer populated by holes coming from that source. During the slow rise in the erasing voltage between the control gate and the main path, the electron discharge current increases progressively without the voltage between the storage gate Gl and the main path reaching the level shown by the curve F2 of Figure 9. The rise in the erasing voltage Ur/Ut should take place at such a slow rate that no hole discharge current flows and the erasing time remains as far as possible constant. An indication of the presence of a hole discharge current can be 107042~

obtained by measuring the voltage between the floating substrate HT and that zone S or D to which the electron discharge is to take place; if a hole current is flowing, then this voltage will increase. The maximum permissible rate of rise in the erasing voltage can be determined for the particular chosen storage FET structure by testing a specimen this rise must be at a rate such that, despite multiple erasing and reprogramming, there is no sub-stantial increase in the particular erasing time.
Because of this avoidance of contamination, erasing can now be per-mitted to take place via the same part of the insulator as that at which pro-gramming is performed. Thus, referring to Figure 17, programming can firstbe carried out using the heated electrons Ke produced at a channel location V close to the drain, and subsequently erasing carried out to the drain by means of the electron discharge current Kd, through practically the same part of the insulator. In this case, again, the usual, undesirably sharp increase in the erasing time or the reprogramming time is not observed, nor the normally inadequate charging of the storage gate following reprogramming, which is encountered when contamination has taken place.
In order to improve erasing of the storage FETs in accordance with the invention a further arrangement can be resorted to which permits excessive discharging of the storage gate Gl without at the same time driving the hole channel of the storage FET into the conductive state. In this further arrange-ment, the storage gate of the storage FET only covers a first section Kl (over the whole width thereof) of the channel Kl/K2. This first channel section Kl contains the location V at which~ by means of the channel injection mechan-ism, heated electrons are emitted at the time of programming; or at least, the first channel section Kl should adjoin this location V. In addition, a control gate G2, but not the storage gate Gl, covers the remaining section K2 of the channel, which is electrically in series with the section Kl, so that 1070~Z7 the state of the first section Kl of the channel is controlled both ~ythe state of the control gate and by the state of the storage gate, whereas the state of the remaining section K2 of the channel, is controlled exclu-sively by the state of the control gate.
Figure 16 illustrates a storage matrix which corresponds approxi-mately to that shown in Figure 4. The store matrix shown in Figure 17, however, is equipped with the form of storage FET, which is shown in Figure l7. Such storage matrices can advantageously be operated in various ways, so far as erasing is concerned.
In a first way, the information stored in an individual storage gate FET can be erased bit by bit. To do this, in order for example to erase the storage FET T3, the erasing voltage must be applied between the associated control electrode line X2, and the corresponding drain line Yl.
Thus, for example, the rising erasing voltage can be generated by applying the rising potential Usl=OV+35V to the selected storage cell, whilst driving the switch T5 into the conductive state. The negative charge stored on the insulated, floating storage gate of the storage cell T3 then discharges across the drain D of this storage cell, to the switch T5. At the same time, to each of the other control lines X connected to the control gates, a voltage of, for example, +20V is applied, whilst to each of the other control lines Y connected to the drains, a zero voltage is applied and the common circuit point SO is arranged to float in order to prevent unwanted influencing (i.e. erasing and programming) of the unselected storage cells Tl, T2 and T4. Since the common circuit point SO is floating, the develop-ment of main path currents which generate unnecessary loss heat, is at the same time prevented.
In a second method, the total information stored in a row of the store, or for that matter the total information stored in several such 10 ~0~2 ,`

rows, can be simultaneously electrically erased. For this purpose, therelevant potentials must be applied to all the correspondingly allocated matrix control lines X and Y. In this way, the entire information stored in all the rows can if desired be simultaneously electrically erased, the relevant potentials being applied to all the matrix control lines.
When programming a storage cell, e.g. T3, a programming potential Ut2 of, for example, +20 volts, is applied to the control line X2 allocated to this storage cell and connected to its control gate G2. The programming potential Ut2 accelerates the free electrons heated in the channel by the channel injection mechanism towards the storage gate Gl. In order that the relevant location V in the channel shall emit the free electrons Ke as a consequence of channel injection, which electrons serve to charge the storage gate Gl, the main path of the relevant storage FET T3 must be supplied with a programming voltage Ur2/Us2 of appropriate magnitudes for example, Ur2 = OV, Us2 - +20V. By applying zero potential to the other matrix control lines Xl and Y2, the other storage FETs Tl, T2 and T4 remain unprogrammed, unread and unerased; these other storage FETs consequently consume no current and therefore no power.
The store shown in Figure 16 can be read out without involving any substantial constructional outlay. When reading out a selected storage cell, e.g. T3, a read-out potential Ut3, e.g. of +5 volts, is applied to the control line X2 allocated to this storage cell and connected to the control gate, which drives the main path of the storage cell T3 into the conductive state if the cell T3 is not programmed, but which does not drive the main path (in this case the first channel section Kl of the storage cell structure shown in Figure 17) into the conductive state, so that T3 remains blocked, if the storage cell T3 is programmed. Whether or not the main path of the relevant storage cell is conductive or blocked is determined 10'7~)42 ~

by the simultaneous application of a read-out voltage, in this case Ur3/Us3, via the switch T5 belonging to the relevant column, e.g. Ur3 = +5V and IJs3 = OV. Thus, when reading out a storage cell, a read-out potential is applied to the control line X2 assigned to the control gate of this stor-age cell, and also a read-out potential Ur3/Us3 to the main path of this storage cell. The current flowing through the main path Kl/K2 forms a signal which drives an output amplifier LV. This output amplifier thus monitors whether or not a current is flowing, i.e. whether or not the storage cell T3 is programmed.
To the unselected control line Xl, at the time of read-out, as in the case when carrying out programming, a voltage of for example zero volts, is applied ~see Figure 16). In this way, it is ensured that no current can flow in any of the unselected storage FETs.

-~5-

Claims (44)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An n-channel zone storage FET comprising:
a p-doped semiconductor substrate having formed therein source and drain regions of n-doped materials, a region of said substrate between said source and drain regions forming said channel zone therebetween, a layer of insulating material adjacent said substrate, a floating storage gate entirely surrounded by said insulating material and arranged so as to have at least a portion of said insulating material disposed between said channel zone and said floating storage gate located so as to be able to receive electrons from said channel zone through said insulating material, means for producing channel injection to charge said gate comprising means for applying a potential to said source and said drain regions to produce a longitudinal field strength and a source-drain current of electrons between said source and drain regions and to accelerate said electrons by said longitud-inal field strength to a sufficiently great degree that at least a portion of them penetrate said portion of said insulat-ing material and charge said floating storage gate, and the negative charge so produced on said floating storage gate can act, by electrostatic induction, to reduce or inhibit the source-drain current of electrons between said source and drain.
2. A storage FET as claimed in claim 1, wherein said storage gate overlaps the drain region.
3. A storage FET as claimed in claim 1 provided with an additional, controllable control gate with a connecting terminal.
4. A storage FET as claimed in claim 3, wherein said control gate is connected to the drain region.
5. A storage FET as claimed in claim 1 or claim 3, wherein the length of said channel zone is less than 10 microns.
6. A storage FET as claimed in claim 1 or claim 3, wherein the length of said channel zone is 1 to 3 microns.
7. A storage FET as claimed in claim 1 or claim 3, wherein said substrate has a specific resistance considerably in excess of 1 ohm. cm.
8. A storage FET as claimed in claim 1 or claim 3, wherein said substrate has a specific resistance of 3 to 10 ohm. cm.
9. A storage FET as claimed in claim 1 or claim 3, wherein said channel zone has an acceleration zone constituted by a substantial localized structural disuniformity.
10. A storage FET as claimed in claim 1 or claim 3, wherein said channel zone is of the enhancement type in the unprogrammed state.
11. A storage FET as claimed in claim 1 or claim 3, wherein a p+-doped layer is present on the surface of said p-doped substrate between said drain region and said source region.
12. A storage FET as claimed in claim 3, wherein said storage gate consists of p-doped polycrystalline silicon.
13. A storage FET as claimed in claim 1 or claim 3, wherein the thickness of said insulating material between said storage gate and said substrate exceeds that value at which the charged storage gate, because of the electrical connection of said drain of said storage FET to the drain of another storage FET
in the same substrate which is being programmed, would be at least partially discharged again because of the avalanche effect.
14. A storage FET as claimed in claim 1 or claim 3, wherein said insulating material has a thickness between said storage gate and said substrate of more than 450 .ANG..
15. A storage FET as claimed in claim 1 or claim 3, wherein said insulating material has a thickness between said storage gate and said substrate of more than 450 .ANG. and less than 1200 .ANG..
16. A storage FET as claimed in claim 3, wherein said storage gate covers only a first part of said channel zone extending over the full width thereof, which part contains or adjoins a location at which said portion of accelerated electrons are emitted by said channel injection during charging;
and wherein said control gate but not said storage gate covers the remaining part of said channel zone, which is electrically in series with said first part, whereby, in use, the state of said first part of said channel zone is controlled both indirectly by the state of said control gate and directly by the state of said storage gate, whilst the state of said remain-ing part of said channel zone is directly controlled exclusively by said state of said control gate.
17. A storage FET as claimed in claim 16, wherein said storage gate is provided with a conductive connection extending laterally of said channel zone and insulated from said substrate by a relatively thick oxide layer, said connection having a tongue arranged outside said channel zone which covers part of said source region or said drain region above a relatively thin oxide layer.
18. A storage FET as claimed in claim 16 or claim 17, where-in said first part of said channel zone adjoins said drain region or said source region.
19. A storage FET as claimed in claim 16 or claim 17, wherein between said first part of said channel zone and said drain region and said source region there is in each case a portion of said remaining part of said channel zone.
20. A store comprising a plurality of storage FETs as claimed in claim 1 integrated in a common substrate to form a storage matrix, each said storage FET forming a storage cell of said matrix.
21. A store as claimed in claim 20, wherein said storage gate covers only a first part of said channel zone extending over the full width thereof, which part contains or adjoins a location at which said portion of accelerated electrons are emitted by said channel injection during charging; and wherein said control gate but not said storage gate covers the remaining part of said channel zone, which is electrically in series with said first part, whereby, in use, the state of said first part of said channel zone is controlled both indirectly by the state of said control gate and directly by the state of said storage gate, whilst the state of said remaining part of said channel zone is directly controlled exclusively by said state of said control gate, and wherein said control gates of lines of said storage cells arranged in a first matrix direction are in each case connected by a first control line, corresponding terminals of the two-terminal main paths of lines of said storage cells arranged in the second matrix direction are in each case connected by a second control line.
22. A store as claimed in claim 21, wherein the other terminals of said main paths of said lines of said storage cells arranged in said second matrix direction are in each case connected by a third control line.
23. A store as claimed in claim 22, including means for applying a programming potential to the first control line associated with a storage cell to be programmed, and for apply-ing a programming voltage between the second and third control lines associated with this storage cell.
24. A store as claimed in claim 22 or claim 23, including means for applying a read-out potential to said first control line associated with a cell to be read-out, and applying a read-out voltage between said second and said third control lines associated with said storage cell.
25. A storage FET as claimed in claim 17, wherein laterally of said remaining part of said channel zone, there is an extension of said control gate which covers said conductive connection and is insulated from said substrate by said relative-ly thick oxide layer, said extension and said conductive connection being insulated from one another by a relatively thin oxide layer.
26. A storage FET as claimed in claim 17, wherein said relatively thick oxide layer is an SiO2 layer of 10,000 .ANG.
thickness and said relatively thin oxide layer is an SiO2 layer of 600 .ANG. thickness.
27. A method of operating storage FET as claimed in claim 3, wherein, for negatively charging said storage gate by means of electrons which are strongly accelerated at a point in said channel zone by said longitudinal field strength, a potential which is positive relative to the source potential is applied to said drain region during programming.
28. A method as claimed in claim 27, wherein a potential which is positive relative to the channel potential, is applied to said control gate during programming.
29. A method as claimed in claim 27, wherein, in order to read-out the charge state of said storage gate, a potential is applied to said control gate which is so highly positive that the drain-source region conducts in the unprogrammed state but blocks in said programmed state of said storage FET.
30. A method as claimed in claim 27, wherein, during programming said positive potential at said drain region is so high and enduring so long that after programming in said programmed state, said channel zone is driven far into the blocking range.
31. A method as claimed in claim 30, wherein, for diminishing charging time, the charging control gate potential is positive relative to the drain potential during programming.
32. A method as claimed in claim 27, wherein, for dis-charging said charged storage gate during erasure by holes produced by the avalanche effect, a potential which is positive relative to the substrate potential and to the control gate potential is applied to said drain region during erasure.
33. A method as claimed in claim 27, wherein, for dis-charging said charged storage gate during erasure by an effect which causes said electrons stored in said storage gate to flow through said insulator to a zone of the main path of said storage FET (i.e. said source region, said drain region or said channel zone), a potential which is sufficiently highly negative relative to the potential of said zone of said main path is applied to said control gate during erasure.
34. A method as claimed in claim 33, wherein, for avoiding a contamination of said insulating material during erasure, said zone of said main path is said source region.
35. A method as claimed in claim 33, wherein said erasing voltage applied is a direct voltage applied between said control gate and said zone of said main path, namely the said channel zone, said drain region or said source region.
36. A method as claimed in claim 33, wherein said erasing voltage is a pulse train applied between said control gate and said zone of said main path, namely said channel zone, said drain region or said source region.
37. A method as claimed in claim 33, wherein, for erasure, the potential on that one of said drain region and said source region to which no electrons flow during erasure, is a floating potential.
38. A method as claimed in claim 33, wherein during erasure, for increasing the permissible number of programming-erasure-reprogramming cycles said erasing voltage which is applied between said control gate and said zone of said main path, rises slowly to a terminal value.
39. A method as claimed in claim 38, wherein said erasing voltage rises over a period of 3 seconds from 0 to 35 Volts.
40. A method as claimed in claim 38 or claim 39, wherein said zone of said main path is said drain region.
41. A store comprising a plurality of storage FETs as claimed in claim 3 integrated in a common substrate to form a storage matrix, each said storage FET forming a storage cell of said matrix.
42. A store as claimed in claim 16, integrated in a common substrate to form a storage matrix, each of said storage FET
forming a storage cell of said matrix, wherein said control gates of said storage cells arranged in a first matrix direction are in each case connected by a first control line, correspond-ing terminals of the two-terminal main paths of lines of said storage cells arranged in the second matrix direction are in each case connected by a second control line.
43. A store as claimed in claim 42, wherein the other terminals of said main paths of said lines of said storage cells arranged in said second matrix direction are in each case connected by a third control line.
44. A store as claimed in claim 43, including means for applying a programming potential to the first control line associated with a storage cell to be programmed, and for apply-ing a programming voltage between the second and third control lines associated with this storage cell.
CA235,230A 1974-09-20 1975-09-11 N-channel storage field effect transistors Expired CA1070427A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE2445137A DE2445137C3 (en) 1974-09-20 1974-09-20 Method for operating an n-channel memory FET, n-channel memory FET for carrying out the method and applying the method to the n-channel memory FETs of a memory matrix
DE19752505816 DE2505816C3 (en) 1974-09-20 1975-02-12 Method for operating an n-channel memory FET, n-channel memory FET for carrying out the method and applying the method to the n-channel memory FETs of a memory matrix
DE2513207A DE2513207C2 (en) 1974-09-20 1975-03-25 n-channel memory FET
DE19752525097 DE2525097C3 (en) 1975-06-05 1975-06-05 Method of operating an n-channel memory FET
DE19752525062 DE2525062C2 (en) 1975-06-05 1975-06-05 N-channel memory FET array

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JPS5391585A (en) * 1977-04-04 1978-08-11 Agency Of Ind Science & Technol Nonvolatile field effect transistor
US4173766A (en) * 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory cell
SE7907193L (en) * 1978-09-28 1980-03-29 Rca Corp Permanent memory
JPS5560469U (en) * 1978-10-20 1980-04-24
JPS5571072A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Semiconductor nonvolatile memory
JPS57160163A (en) * 1981-03-27 1982-10-02 Agency Of Ind Science & Technol Nonvolatile semiconductor memory
JPS5864068A (en) * 1981-10-14 1983-04-16 Agency Of Ind Science & Technol Non-volatile semiconductor memory
JPH04307974A (en) * 1991-04-05 1992-10-30 Sharp Corp Electrically erasable nonvolatile semiconductor storage device
CN111739572A (en) * 2019-03-25 2020-10-02 亿而得微电子股份有限公司 Low-voltage quick erasing method for electronic writing erasable read-only memory

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IT1042632B (en) 1980-01-30
AT365000B (en) 1981-11-25
ATA646575A (en) 1981-04-15
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NL7511017A (en) 1976-03-23
AU498494B2 (en) 1979-03-15

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