SE7907193L - Best memory Constantly - Google Patents

Best memory Constantly

Info

Publication number
SE7907193L
SE7907193L SE7907193A SE7907193A SE7907193L SE 7907193 L SE7907193 L SE 7907193L SE 7907193 A SE7907193 A SE 7907193A SE 7907193 A SE7907193 A SE 7907193A SE 7907193 L SE7907193 L SE 7907193L
Authority
SE
Sweden
Prior art keywords
source
drain
floating gate
region
regions
Prior art date
Application number
SE7907193A
Other languages
Swedish (sv)
Inventor
S T Hsu
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US94672278A priority Critical
Application filed by Rca Corp filed Critical Rca Corp
Publication of SE7907193L publication Critical patent/SE7907193L/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor

Abstract

An array of floating gate semiconductor devices wherein the floating gate member 16 associated with a particular device extends across the drain-channel region junction with a leading edge that terminates over the channel region. The associated control gate 20 extends across the channel region. It is insulated from the floating gate, and has a leading edge that terminates over the drain region and a trailing edge that terminates over the source region. The displacement of the trailing edge of the floating gate from the source region permits the control gate of each device, in a given row, to be connected to a common line 40 and the source and drain regions of a given device to be the same regions as the drain and source regions, respectively, of the next adjacent device on either side in a given row. The common source-drain regions of respective columns are connected in common to form an addressable array. <IMAGE>
SE7907193A 1978-09-28 1979-08-29 Best memory Constantly SE7907193L (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US94672278A true 1978-09-28 1978-09-28

Publications (1)

Publication Number Publication Date
SE7907193L true SE7907193L (en) 1980-03-29

Family

ID=25484885

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7907193A SE7907193L (en) 1978-09-28 1979-08-29 Best memory Constantly

Country Status (6)

Country Link
JP (1) JPS5732514B2 (en)
DE (1) DE2937952C2 (en)
FR (1) FR2437676B1 (en)
GB (1) GB2032687B (en)
IT (1) IT1122538B (en)
SE (1) SE7907193L (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409723A (en) * 1980-04-07 1983-10-18 Eliyahou Harari Method of forming non-volatile EPROM and EEPROM with increased efficiency
DE3141390A1 (en) * 1981-10-19 1983-04-28 Itt Ind Gmbh Deutsche carried floating-gate memory cell in which the write and delete by injection of hot charge carriers
FR2524714B1 (en) * 1982-04-01 1986-05-02 Suwa Seikosha Kk A thin film transistor
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
US4795719A (en) * 1984-05-15 1989-01-03 Waferscale Integration, Inc. Self-aligned split gate eprom process
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4783766A (en) * 1986-05-30 1988-11-08 Seeq Technology, Inc. Block electrically erasable EEPROM
FR2621737B1 (en) * 1987-10-09 1991-04-05 Thomson Semiconducteurs Memory in integrated circuit
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
KR100241524B1 (en) * 1996-12-28 2000-02-01 김영환 Flash memory cell
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728695A (en) * 1971-10-06 1973-04-17 Intel Corp Random-access floating gate mos memory array
AT365000B (en) * 1974-09-20 1981-11-25 Siemens Ag N-channel-memory-fet
DE2525097C3 (en) * 1975-06-05 1982-08-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
DE2643948C2 (en) * 1976-09-29 1981-10-15 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
FR2375692A1 (en) * 1976-12-27 1978-07-21 Texas Instruments Inc Electrically programmable semiconductor storage matrix - has devices applying high and low voltages to selected row and column lines of matrix

Also Published As

Publication number Publication date
GB2032687A (en) 1980-05-08
IT7925552D0 (en) 1979-09-07
GB2032687B (en) 1983-03-23
FR2437676B1 (en) 1982-12-17
IT1122538B (en) 1986-04-23
DE2937952A1 (en) 1980-04-03
JPS5546598A (en) 1980-04-01
DE2937952C2 (en) 1983-04-14
JPS5732514B2 (en) 1982-07-12
FR2437676A1 (en) 1980-04-25

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