GB2032687A - Electrically programmable floating gate read only memory - Google Patents
Electrically programmable floating gate read only memory Download PDFInfo
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- GB2032687A GB2032687A GB7932557A GB7932557A GB2032687A GB 2032687 A GB2032687 A GB 2032687A GB 7932557 A GB7932557 A GB 7932557A GB 7932557 A GB7932557 A GB 7932557A GB 2032687 A GB2032687 A GB 2032687A
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- floating gate
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- 230000015654 memory Effects 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000003860 storage Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 7
- 239000010980 sapphire Substances 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 4
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052596 spinel Inorganic materials 0.000 claims description 3
- 239000011029 spinel Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000003607 modifier Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
An array of floating gate semiconductor devices wherein the floating gate member 16 associated with a particular device extends across the drain-channel region junction with a leading edge that terminates over the channel region. The associated control gate 20 extends across the channel region. It is insulated from the floating gate, and has a leading edge that terminates over the drain region and a trailing edge that terminates over the source region. The displacement of the trailing edge of the floating gate from the source region permits the control gate of each device, in a given row, to be connected to a common line 40 and the source and drain regions of a given device to be the same regions as the drain and source regions, respectively, of the next adjacent device on either side in a given row. The common source-drain regions of respective columns are connected in common to form an addressable array. <IMAGE>
Description
SPECIFICATION
Electrically programmable floating gate read only memory array
This invention relates, in general, to nonvolatile memory structures and more particularly to a novel array of electrically alterable floating gate devices.
The computer and related arts have long required read only memory (ROM) elements that were non-volatile and the prior art has provided many devices which, to some extent, attempted to fill this need. However, as the computer art has progressed in complexity there now exists a need to provide electrically alterable read only memories that may be programmed (or "written") and, if the occasion arises, to reprogram (erase and write) in the field. To this end, devices are presently available that exhibit non-volatile characteristics but, as will be discussed, have inherent shortcomings that are overcome by the subject invention.
At one end of the spectrum of semiconductor memory devices is the family of Floating
Gate-Avalanche-Metal-Oxide-Semiconductor (FAMOS) devices while the other end is represented by the family of Metal-Nitride-Oxide
Semiconductor (MNOS) devices. The advantages of both types of devices resides in the fact that they are independent of any outside current to maintain the stored information in the event power is lost and, since they are independent, there is no need for any further refreshing of the devices. Hence, there is a significant saving in power.
The floating gate family of devices usually has source and drain regions of one conductivity formed in a substrate of the opposite conductivity, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is formed by first applying a thin insulating oxide layer. A conductive layer is placed over the insulating layer (the floating gate) and a second insulating layer is formed to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (the control gate) is then formed atop the second insulating layer.
These floating gate devices which are exemplified in U.S. Letters Patent No. 3,500,142 and No. 3,755,721, have inherent drawbacks in that high fields are required to produce the necessary avalanche breakdown so that a charge will appear on the floating gate. Further, to erase the charge appearing on the floating gate, the entire device must be flooded with energy in the untraviolet or x-ray portion of the spectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the remainder of the device, and thereby requiring the device to be completely reprogrammed. However, one serious defect that manifests itself is the tendency toward zener breakdown, at the drain-substrate junction, at low voltages.Further, after a relatively short number of charge and discharge (write and erase) cycles has been accomplished, the user is faced with a radical change in threshold voltage, a situation which, in many instances, may require the replacement of the device.
In accordance with the invention, a nonvolatile memory structure of the floating gate type device is described that may be readily formed into an x-y matrix in which an individual device, at the intersection of a given row and column, may be easily accessed for programming, reprogramming or reading. The individual devices are further characterized in that they may be written or erased with the same ease that one may write or erase an
MNOS device. As distinguished from my previously filed application, Serial No. 864,766 filed on or about December 27, 1977 entitled "Floating Gate Solid State Storage Device" and assigned to the same assignee as the subject application, the subject application avoids the uniformity of the gates with respect to each other and with respect to the channel areas.Instead, the floating gate of the subject device is placed off to the side of the channel region, adjacent the drain region, in order to extend over a portion of the drain region. The control gate is insulated from the floating gate but is aligned with that portion of the floating gate that extends over the drain region, while the other edge of the control gate extends beyond the far edge of the floating gate and extends over the junction of the source-channel regions. Thus, the control gate is disposed at two levels.
The electric field distributions in each device are such that each device can be "written" by a voltage applied between its control gate and its drain, but not by a voltage of similar polarity and magnitude applied between its control gate and its source. Thus, the drain of one device may be the same region which serves as the source of an adjacent device in an array, leading to compactness and high device density.
Figure 1 is a cross-sectional view of one embodiment of an element that may be utilized in an x-y array.
Figure 2 is a cross-sectional view of another embodiment of a floating gate device which may be used as an element that may be utilized in an x-y array; and
Figure 3 is a cross-sectional view of an x-y array of the elements of Fig. 1.
It should be noted that while the following explanation, with regard to Fig. 3, will be discussed in terms of a silicon-on-sapphire (SOS) device, it will be obvious to those skilled in the art that while sapphire is preferred, other similar insulators such as spinel
and beryllium oxide may be used. Further, while the structure will be shown and described as a P-channel device, it is only by way of example since the conductivity types of the various elements may be changed without departing from the inventive concept.
Referring now to Fig. 1, there is shown a semi-conductor device 10 having an insulative substrate 12 which may, for example, be selected from the group consisting of sapphire, spinel or beryllium oxide. As is well known in the SOS art, the layer of monocrystalline silicon is first deposited or formed on sapphire substrate 12 and formed into discrete islands and is thereafter doped or implanted with one type of conductivity modifier to form source region 14.1 and drain region
14.3 with an intervening channel region 14.2 that is doped with an opposite type conductivity modifier. In the example shown, source
14.1 and rain 14.3 have P + type conductivity while channel region 14.2 is shown as having n- type conductivity.Having formed the island, a layer of gate oxide is formed thereon and a layer of polycrystalline silicon (poly-silicon) is formed thereon to constitute the floating gate portion. Floating gate 16 is positioned so that its leading edge extends over the drain-channel region junction and its trailing edge terminates over the channel region. The control gate is formed over floating gate 16 after first forming an oxide coating 22 over floating gate 16 and conforming to the contour thereof. As a result, the portion of control gate 20 that will overlie floating gate 16 is disposed further away from the channel region than the remaining portion of control gate 20.Thereafter, a second layer of doped polysilicon is formed over insulating layer 22 constituting the control gate 20 which has its leading edge aligned with the leading edge of floating gate 16 and its trailing edge covering the source-channel junction and terminating in an area over the source region. Thereafter, the entire device is coated with a field oxide 30.
In order to make contact to the various elements thus formed, contact openings are formed which expose portions of source 14.1, control gate 20 and drain 14.3. Thereafter, electrical contacts are made to each of the respective elements and are shown as metallic contacts 24, 26, 28 respectively.
Referring now to Fig. 2 there is shown my novel structure as it may be formed utilizing bulk silicon. In this embodiment a body of bulk silicon 32, of a given concentration of conductivity modifiers therein, has certain areas 34 and 38 formed therein which areas constitute the source and drain regions respectively with the resultant channel region 36 being formed therebetween. Thereafter, gate oxide layer 18 is provided on the upper surface of the silicon body 32 after which floating gate 16 is formed which gate is made to extend partially over the drain-channel region junction. Floating gate 16 is then provided with an insulated field oxide layer 22 which conforms to the raised profile due to the presence of floating gate 16 and thereafter, control gate 20 is formed so that one edge thereof is aligned to the edge of the floating gate covering the drain-channel region junction.The other edge of control gate 20 extends over the source-channel junction and over the source region. Field oxide 30 is also provided in order to cover control gate 20 after which metallic leads 24, 26, and 28 are provided in direct ohmic contact with source 34, control gate 20, and drain 38 respectively.
Referring now to Fig. 3 there is shown in cross section, an array of devices in a memory matrix arrangement where similar elements are similarly numbered to those shown in
Figs. 1 and 2 and wherein similar rows of devices are behind and in front of the plane of section forming doped lines 52 and 54. While this embodiment will be described in terms of an SOS device it will be obvious that a similar device may be constituted utilizing bulk silicon. In this embodiment, a layer of monocrystalline silicon 14 is deposited on the surface of sapphire substrate 12 and is ultimately doped with P + and n - type regions in a well known manner.In the illustration herein presented floating gates 22 are disposed over and insulated from the n - type channel regions and a control gate 20 is disposed thereover and insulated therefrom in a similar manner to that shown and desribed with respect to Figs. 1 and 2. In the array, all control gates 20 in each row are interconnected by a common line through connections
R,-R5 to a terminal 40 and each of the P + regions 52 of a given column are interconnected and terminated via lines C,-C4 to terminals 42-50, respectively. Thus, if it is desired to write a charge on the device associated with lines R2-C2 one first block-erases all cells to their high conductive state by applying a negative voltage (or pulse) to terminal 40 and a positive voltage or pulse to the C,-Cs lines via terminals 42-50. This has the effect of placing a positive pulse on all P + diffusion lines.
To now write the R2C2 device into a low conductive state, a negative pulse is applied to terminal 44 and a positive pulse to terminal 40. All other terminals are grounded. In this manner the floating gate associated with R2C2 will be charged with holes while the adjacent cells (R,-C, and R3-C3) will not be affected.
All the devices in the given row, except the
R3C3 device, will not be affected because both the source and drain regions of each device are at ground potential, and the electric field strength between the control electrode and the drain is not sufficient to charge the floating gate. The R3C3 device will not be affected because the full writing voltage is between its control gate and its source region, rather than between the control gate and the drain region.
The offset of the floating gate toward the drain insures that the electric field strength at the floating gate of the R3C3 device, under these conditions, will be less than that required to charge this floating gate with holes.
While there may be other methods for manufacturing my invention the following explanation represents one such method of fabrication that I have found to be successful. Further, while the following explanation will be described in terms of an SOS device, it should be obvious to those skilled in the art that with only a slight, obvious modification the same processing would apply to bulk silicon.
A sapphire substrate is provided having a broad flat surface on which a layer of intrinsic silicon 14 is deposited in a well known manner. The thickness of layer 14 is of the order of about 0.5-0.6 lim. Thereafter, layer 14 is formed into islands which may then be appropriately doped or implanted with phosphorus, for example, to introduce n type conductivity modifiers and then masked to define the P + lines 52. The structure may now be doped or implanted with, for example, boron in a well known manner to form P + lines 52. The resultant structure (as shown in Fig. 3 in cross-section) will then have alternate P + and n - lines 52 and 54 respectively.
Having formed the P + and n - lines in layer 14, a layer of gate oxide, comparable to gate oxide 18 (Figs. 1 and 2) is then grown on silicon layer 14 to a thickness of about 100-200A using dry 02 at about 900 C for a period of about 30 minutes. Thereafter, the polycrystalline silicon (polysilicon) floating gate is formed over the gate oxide layer. This is done by means of a low pressure chemical vapor deposition process and is continued until floating gate 1 6 (Figs. 1 and 2) then masked so that one edge overlaps the junction of one P + line 52 and n - line 54. Thus, the mask defines both limits of floating gate 16 wherein one edge thereof will overlap one drain-channel junction and the other edge will terminate somewhere over the channel region.
The polysilicon layer is then etched using a hot ethylene diamina pyrocatechol and water solution at a temperature approaching the boiling point of the etchant. This then defines both the leading and trailing edges of floating gate 16 as shown in Figs. 1, 2 and 3.
Thereafter, a second layer of oxide is grown over the now defined floating gate 16 to a thickness of about 8CO-900A and may, for example, be accomplished using wet oxygen (steam) at 900 C for about 40 minutes. The net result of this step will be the production of an oxide thickness of about 800-9OO immediately above floating gate 16 tapering to a thickness of about 1000 over that portion of the channel region that is not covered by floating gate 16.
The process is continued by depositing a layer of polysilicon over the now step-shaped oxide in order to form a control gate. Control gate 20 (Figs. 1 and 2 is first formed by depositing a polysilicon layer to a thickness of about 6000A utilizing any well known low pressure chemical vapor deposition. This second polysilicon layer is then masked and appropriately etched with the same type of solution previously mentioned with regard to the etching of floating gate 16. The masking in this instance will align one edge of control gate 20 with the corresponding edge of floating gate 16.Thereafter, to complete the array, another layer of silicon oxide is deposited over the entire structure to a thickness of about 6000A. This oxide layer may also be done by a chemical vapor deposition and thereafter should the user deem it necessary, the last oxide coating may be densified in an oxygen ambient. The structure is now masked so as to form contact openings and the openings suitably etched down to all control gates 20 and to all P + regions 52 and subsequently metallized in a manner so as to connect all of the control gates 20 which occur in a given row while each P + line 52 is connected via Ca, C2, C3, C4, and C5 to terminals 42, 44, 46, 48 and 50 respectively.
Accordingly, by utilizing the configuration described in Fig. 3 as an array of floating gate storage devices arranged in a matrix of rows and columns it will be obvious to those skilled in the art that when so connected, the source and drain regions of a particular device associated with a particular floating gate-control gate combination in a given row will function as a drain and source region, respectively, for the next adjacent device on either side in the given row. Further, by utilizing the described configuration there is no need for the required isolation between devices thereby saving a considerable amount of "real estate" and allowing a greater packing density.
Claims (6)
1. In a non-volatile memory array of the type including a plurality of floating gate storage devices arranged in a matrix of rows and columns, each storage device having a floating gate member (16), a control gate member (20), a body (14) of semiconductor material in which spaced drain and source regions (52) of a first conductivity type are embedded at the surface thereof, the drain and source regions (52) spaced a given distance one from the other defining a channel region (54) of an opposite conductivity type in the space between the drain and source regions (52); a drain-channel junction formed at the boundary of the drain (52) and channel (54) regions; a source-channel junction formed at the boundary of the source (52) and channel (54) regions; and a first layer (18) of insulating material deposited on the body (14) of semiconductor material over the drain (52), channel (54) and source (52) regions; the floating gate member (16) being disposed on the layer (18) of insulating material, over the drain-channel junction, and having a leading edge extending into the area over the drain region (52) and a trailing edge extending into the area over the channel region (54); the control gate member (20) being disposed over and insulated from the floating gate member (16) and having a leading edge extending into the area over the drain region (52) and a trailing edge extending over the source-channel junction into the area over the source region (52); and contact means connected to the drain region (52), the control gate member (20) and the source region (52), characterized in that the contact means connected to the control gate member (20) of each storage device, in a given row, are connected in common; the source and drain regions (52) of each storage device in a given row are the same regions as the drain and source regions (52), respectively, of the next adjacent storage devices on either side in the given row; and the source and drain regions (52) of each storage device in a given column are respectively common.
2. The non-volatile memory array of Claim 1, wherein: the drain (52), channel (54) and source (52) regions of the storage devices are colocated on an island (14) of silicon formed on an insulative substrate (12).
3. The non-volatile memory array of Claim 2, wherein: the insulative substrate (12) is selected from the group consisting of sapphire, spinel, and beryllium oxide.
4. The non-volatile memory array of Claim 1, wherein: the drain (52), channel (54) and source (52) regions of the storage devices are colocated immediately beneath the surface of a body (32) of monocrystalline silicon.
5. The non-volatile memory array of Claim 4, wherein: the body (32) of silicon is one type of conductivity and the drain and source regions (52) are of the opposite type conductivity.
6. A non-volatile memory array substantially as described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US94672278A | 1978-09-28 | 1978-09-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2032687A true GB2032687A (en) | 1980-05-08 |
| GB2032687B GB2032687B (en) | 1983-03-23 |
Family
ID=25484885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7932557A Expired GB2032687B (en) | 1978-09-28 | 1979-09-20 | Electrically programmable floating gate read only memory array |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5546598A (en) |
| DE (1) | DE2937952C2 (en) |
| FR (1) | FR2437676A1 (en) |
| GB (1) | GB2032687B (en) |
| IT (1) | IT1122538B (en) |
| SE (1) | SE7907193L (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4328565A (en) | 1980-04-07 | 1982-05-04 | Eliyahou Harari | Non-volatile eprom with increased efficiency |
| US4597000A (en) * | 1981-10-19 | 1986-06-24 | Itt Industries, Inc. | Floating-gate memory cell |
| GB2243718A (en) * | 1990-04-30 | 1991-11-06 | Intel Corp | A process for fabricating a contact less floating gate memory array |
| GB2320807B (en) * | 1996-12-28 | 2001-09-19 | Hyundai Electronics Ind | Flash memory cell |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4409723A (en) * | 1980-04-07 | 1983-10-18 | Eliyahou Harari | Method of forming non-volatile EPROM and EEPROM with increased efficiency |
| FR2524714B1 (en) * | 1982-04-01 | 1986-05-02 | Suwa Seikosha Kk | THIN FILM TRANSISTOR |
| US4795719A (en) * | 1984-05-15 | 1989-01-03 | Waferscale Integration, Inc. | Self-aligned split gate eprom process |
| US4639893A (en) * | 1984-05-15 | 1987-01-27 | Wafer Scale Integration, Inc. | Self-aligned split gate EPROM |
| US4868629A (en) * | 1984-05-15 | 1989-09-19 | Waferscale Integration, Inc. | Self-aligned split gate EPROM |
| US4783766A (en) * | 1986-05-30 | 1988-11-08 | Seeq Technology, Inc. | Block electrically erasable EEPROM |
| FR2621737B1 (en) * | 1987-10-09 | 1991-04-05 | Thomson Semiconducteurs | INTEGRATED CIRCUIT MEMORY |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3728695A (en) * | 1971-10-06 | 1973-04-17 | Intel Corp | Random-access floating gate mos memory array |
| AT365000B (en) * | 1974-09-20 | 1981-11-25 | Siemens Ag | N-CHANNEL STORAGE FET |
| DE2525097C3 (en) * | 1975-06-05 | 1982-08-05 | Siemens AG, 1000 Berlin und 8000 München | Method of operating an n-channel memory FET |
| DE2643948C2 (en) * | 1976-09-29 | 1981-10-15 | Siemens AG, 1000 Berlin und 8000 München | Matrix memory FETs and methods of making them |
| FR2375692A1 (en) * | 1976-12-27 | 1978-07-21 | Texas Instruments Inc | Electrically programmable semiconductor storage matrix - has devices applying high and low voltages to selected row and column lines of matrix |
-
1979
- 1979-08-29 SE SE7907193A patent/SE7907193L/en not_active Application Discontinuation
- 1979-09-07 IT IT25552/79A patent/IT1122538B/en active
- 1979-09-20 DE DE2937952A patent/DE2937952C2/en not_active Expired
- 1979-09-20 GB GB7932557A patent/GB2032687B/en not_active Expired
- 1979-09-27 JP JP12524779A patent/JPS5546598A/en active Granted
- 1979-09-27 FR FR7924057A patent/FR2437676A1/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4328565A (en) | 1980-04-07 | 1982-05-04 | Eliyahou Harari | Non-volatile eprom with increased efficiency |
| US4597000A (en) * | 1981-10-19 | 1986-06-24 | Itt Industries, Inc. | Floating-gate memory cell |
| GB2243718A (en) * | 1990-04-30 | 1991-11-06 | Intel Corp | A process for fabricating a contact less floating gate memory array |
| US5087584A (en) * | 1990-04-30 | 1992-02-11 | Intel Corporation | Process for fabricating a contactless floating gate memory array utilizing wordline trench vias |
| GB2243718B (en) * | 1990-04-30 | 1993-11-24 | Intel Corp | A process for fabricating a contactless floating gate memory array |
| GB2320807B (en) * | 1996-12-28 | 2001-09-19 | Hyundai Electronics Ind | Flash memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1122538B (en) | 1986-04-23 |
| FR2437676B1 (en) | 1982-12-17 |
| DE2937952A1 (en) | 1980-04-03 |
| FR2437676A1 (en) | 1980-04-25 |
| GB2032687B (en) | 1983-03-23 |
| JPS5732514B2 (en) | 1982-07-12 |
| JPS5546598A (en) | 1980-04-01 |
| DE2937952C2 (en) | 1983-04-14 |
| IT7925552A0 (en) | 1979-09-07 |
| SE7907193L (en) | 1980-03-29 |
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