CN111739572A - Low-voltage quick erasing method for electronic writing erasable read-only memory - Google Patents

Low-voltage quick erasing method for electronic writing erasable read-only memory Download PDF

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CN111739572A
CN111739572A CN201910229435.6A CN201910229435A CN111739572A CN 111739572 A CN111739572 A CN 111739572A CN 201910229435 A CN201910229435 A CN 201910229435A CN 111739572 A CN111739572 A CN 111739572A
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semiconductor substrate
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林信章
钟承谕
黄文谦
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Yield Microelectronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

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  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A low-voltage fast erasing method for EEPROM features that a transistor structure with the first conducting grid is arranged on semiconductor substrate, and the ions of same type are implanted in the semiconductor substrate or the doped region of source and drain at the interface between the first conducting grid and source and drain to increase the concentration of ions in said region and decrease the voltage difference for erasing. The invention can be applied to a single-grid transistor structure and is more suitable for an electronic writing erasable read-only memory with a floating grid structure.

Description

Low-voltage quick erasing method for electronic writing erasable read-only memory
Technical Field
The invention relates to an electronic writing erasable rewritable read-only memory technology, in particular to a low-voltage quick erasing method of an electronic writing erasable rewritable read-only memory.
Background
In the modern times of development of computer information products, nonvolatile memories such as an Electrically Erasable Programmable Read Only Memory (EEPROM) and a Flash Memory (Flash) are semiconductor storage devices that can be rewritten many times by an electronic method, and Only a specific voltage is required to erase data in the Memory so as to write new data, and the data does not disappear after the power is turned off, so the Memory is widely used in various electronic products.
Since non-volatile memories are programmable, they utilize stored charge to change the gate voltage of the transistor of the memory, or no charge is stored to leave the gate voltage of the transistor of the original memory. The erase operation removes the charge stored in the non-volatile memory, causing the non-volatile memory to return to the gate voltage of the transistor of the original memory. For the current non-volatile memory, a high voltage difference is required for erasing, which results in an increase in area and complexity of the process.
In view of the above, the applicant has proposed a low current and low voltage difference EEPROM for overcoming the above drawbacks of the prior art, and through further research, a low voltage and fast erasing method for the EEPROM architecture is proposed.
Disclosure of Invention
The main object of the present invention is to provide a low voltage fast erase method for an EEPROM, which uses the EEPROM and increases the electric field between the transistor or the substrate and the gate by increasing the ion implantation concentration for the EEPROM, so as to reduce the erase voltage difference; meanwhile, by using the erasing condition of the present invention, the source or the drain is set to be floating, so as to achieve the effect of fast erasing of a large number of memory cells (memory cells).
The present invention provides a low-voltage fast erasing method for an eeprom, which is applied to an eeprom, and the eeprom mainly includes a semiconductor substrate on which at least one transistor structure is disposed, the transistor structure includes a first dielectric layer on a surface of the semiconductor substrate, a first conductive gate on the first dielectric layer, and at least two first ion-doped regions respectively in the semiconductor substrate and on two sides of the first conductive gate to serve as a source and a drain; wherein, the same type ions are further implanted into the semiconductor substrate at the junction of the first conductive grid and the source and the drain or the first ion doped region by ion implantation to increase the ion concentration thereof and reduce the erasing voltage difference.
In addition to the single gate transistor structure, the present invention is also applicable to a floating gate structure, and therefore, in addition to the transistor structure described above, the present invention further includes a capacitor structure located on the surface of the semiconductor substrate and isolated from the transistor, the capacitor structure includes a second ion-doped region located in the semiconductor substrate, a second dielectric layer located on the surface of the second ion-doped region, and a second conductive gate overlying the second dielectric layer, the second conductive gate being electrically connected to the first conductive gate to serve as a floating gate.
In addition, the implanted same-type ions can increase the ion concentration in the semiconductor substrate or the first ion-doped region by 1 to 10 times, regardless of the single-gate transistor structure or the floating gate structure.
When the transistor structure is an N-type transistor, the first ion-doped region or the second ion-doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well. When the transistor structure is a P-type transistor, the first ion-doped region or the second ion-doped region is a P-type doped region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well.
Regardless of the single gate structure or the floating gate structure, there are different operation methods due to different regions for increasing ion concentration and different types of transistors.
When the transistor is an N-type transistor and the same type ions are implanted into the first ion doped region to increase the ion concentration, the erasing method of the present invention includes implanting the same type ions into the first conductive gate or the floating gateA gate voltage V is applied to the gate, the source, the drain and the semiconductor substrategSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions: satisfy VsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or satisfy VsubTo earth, VsHigh pressure, VdIs floating and Vg0 or less than 2V.
When the transistor is a P-type transistor and the same type ions are implanted in the first ion doping region to increase the ion concentration, the erasing method of the present invention includes applying a gate voltage V to the first conductive gate or the floating gate, the source, the drain and the semiconductor substrate respectivelygSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions: satisfy VsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
When the concentration of the above-mentioned transistors, whether they are P-type transistors or N-type transistors, is increased by implanting ions of the same type into the semiconductor substrate to increase the ion concentration, the erasing method of the present invention comprises applying a gate voltage V to the first conductive gate or the floating gate, the source, the drain and the semiconductor substrate respectivelygSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions: when the transistor is an N-type transistor, V is satisfiedsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or satisfy VsubTo earth, VsHigh pressure, VdIs floating and Vg0 or less than 2V. When the transistor is a P-type transistor, V is satisfiedsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
The purpose and technical contents of the present invention and the effects achieved thereby will be more easily understood by the following detailed description of the embodiments in conjunction with the accompanying drawings.
Drawings
FIG. 1(a) is a schematic structural diagram of the EEPROM of the present invention, which is formed by performing ion implantation in the first ion-doped region (source/drain).
FIG. 1(b) is a schematic structural diagram of the EEPROM of the present invention after ion implantation in a semiconductor substrate.
FIG. 2 is a schematic diagram of a single memory cell structure with an N-type transistor and a single gate structure according to the present invention.
FIG. 3 is a schematic diagram of a single memory cell structure with an N-type transistor and a single floating gate structure according to the present invention.
FIG. 4 is a schematic diagram of a single memory cell structure with a P-type transistor and a single gate structure according to the present invention.
FIG. 5 is a schematic diagram of a single memory cell structure with a single floating gate structure having a P-type transistor according to the present invention.
List of reference numerals: 10-a semiconductor substrate; 12-transistor structure; 14-a first dielectric layer; 16 — a first conductive gate; 18-a source electrode; 20-a drain electrode; 22-ions; 30-P-type semiconductor substrate; 32-N type transistors; 320-a first dielectric layer; 322 — a first conductive gate; 3221 — floating gate; 3222 — a control dielectric layer; 3223 — control gate; 324-source; 326-drain electrode; 34-N type well capacitance; 340-N well; 342-a second dielectric layer; 344 — a second conductive gate; 36-an isolation element; 38-single floating gate; 40-N type semiconductor substrate; 42-P-type transistor; 420 — a first dielectric layer; 422 — first conductive gate; 4221-floating grid; 4222-control dielectric layer; 4223-control grid; 424-source; 426-drain electrode; 44-P-type well capacitance; 440-P well; 442-a second dielectric layer; 444-second conductive gate; 46-an isolation element; 48-Single floating gate.
Detailed Description
The invention mainly provides a low-voltage quick erasing method of an electronic writing erasable read-only memory, which is applied to the electronic writing erasable read-only memory, wherein the electronic writing erasable read-only memory increases the electric field between a transistor or a substrate and a grid by increasing the ion implantation concentration so as to reduce the voltage difference of erasing.
As shown in fig. 1(a) and fig. 1(b), the eeprom proposed in the present invention mainly includes: a semiconductor substrate 10 is formed with at least one transistor structure formed on the semiconductor substrate 10. the transistor structure 12 includes a first dielectric layer 14 disposed on the surface of the semiconductor substrate 10, a first conductive gate 16 disposed on the first dielectric layer 14, and at least two first ion-doped regions (18, 20) disposed in the semiconductor substrate 10 and on both sides of the first conductive gate 16, respectively, as a source 18 and a drain 20. In the invention, the voltage difference of source/drain to grid or the voltage difference of substrate/trap to grid is used to make electrons pass through dielectric layer (oxide layer) so as to achieve low current erasing. Therefore, there are two ways to increase the ion implantation concentration, one way is to implant the same type of ions 22 into the first ion doped regions 18, 20 at the junction of the first conductive gate 16 and the source 18 and drain 20 by ion implantation, i.e. the first ion doped regions 18, 20 are P-type, then implant P-type ions 22, and implant N-type ions 22 for N-type to increase the ion concentration, so as to increase the ion concentration in the first ion doped regions 18, 20 by 1 to 10 times of the original concentration, so as to apply a voltage difference between the transistor structure and the first conductive gate for erasing, and thereby reduce the voltage difference for erasing, as shown in fig. 1 (a). Alternatively, as shown in fig. 1(b), the same type ions 22 are implanted into the semiconductor substrate 10 at the junction of the first conductive gate 16 and the source 18 and drain 20 by ion implantation, i.e., the semiconductor substrate is P-type, the P-type ions 22 are implanted, and the N-type ions 22 are implanted into the semiconductor substrate 10 to increase the ion concentration thereof, and similarly, the ion concentration in the semiconductor substrate 10 is increased by 1 to 10 times of the original concentration, so that the difference between the applied voltage and the applied voltage is larger than that of the semiconductor substrate and the first conductive gate for erasing.
Furthermore, spacers (not shown) are further disposed on both sidewalls of the first dielectric layer and the second conductive gate of the transistor structure, and the same type of ions implanted in the first ion doped region at the junction of the first conductive gate 16 and the source 18 and the drain 20 are implanted before the spacers are formed to increase the concentration of the doped region, and the first ion doped region 18, 20 further has a Lightly Doped Drain (LDD), and in this case, the preferred doping position is the Lightly Doped Drain (LDD) region.
In addition to the single-gate structure, the present invention also applies to the single-floating-gate structure by using the two structures to increase the ion concentration, and the difference is that, if the structure is a single-floating-gate structure, the present invention further includes a capacitor structure, such that the second conductive gate of the capacitor structure is electrically connected to the first conductive gate to serve as the single-floating-gate. The detailed application and operation of the various structures will be described in sequence as follows.
First, referring to fig. 2, the single memory cell structure of the eeprom includes a P-type semiconductor substrate 30, which may also be a semiconductor substrate with a P-type well, wherein the P-type semiconductor substrate 30 is taken as an example, an N-type transistor 32, such as an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), is disposed on the P-type semiconductor substrate 30, the N-type transistor includes a first dielectric layer 320 disposed on the surface of the P-type semiconductor substrate 30, a first conductive gate 322 disposed on the first dielectric layer 320, and two N-type ion doped regions disposed in the P-type semiconductor substrate 30 to serve as a source 324 and a drain 326, respectively, and a channel is formed between the source 324 and the drain 326; the first conductive gate 322 sequentially includes a floating gate 3221, a control dielectric layer 3222 and a control gate 3223 stacked on the first dielectric layer 320 from bottom to top, which is a single gate structure.
Referring to FIG. 3, the single cell structure of the EEPROM comprises a P-type semiconductor substrate 30 having an N-type transistor 32 and an N-well (N-well) capacitor 34 separated by an isolation element 36. The N-type transistor 32, such as an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), includes a first dielectric layer 320 on the surface of the P-type semiconductor substrate 30, a first conductive gate 322 overlying the first dielectric layer 320, and two N-type ion doped regions within the P-type semiconductor substrate 30 to serve as a source 324 and a drain 326, respectively, forming a channel between the source 324 and the drain 326. The N-well capacitor 34 includes a second ion doped region in the P-type semiconductor substrate 30 as the N-well 340, a second dielectric layer 342 on the surface of the N-well 340, and a second conductive gate 344 on the second dielectric layer 342 to form a top-dielectric-bottom plate capacitor structure. The first conductive gate 322 of the N-type transistor 32 and the second conductive gate 344 of the N-type well capacitor 34 are electrically connected and isolated by the isolation device 36 to form a single floating gate (floating gate)38 structure.
Referring to fig. 2 and fig. 3, regardless of the memory cell structure shown in fig. 2 or fig. 3, when the eeprom has the N-type transistor 32 and the N-type ions of the same type are further implanted into the ion doped regions of the source 324 and the drain 326 near the boundary of the first conductive gate 322 to increase the ion concentration thereof, for example, by 1 to 10 times, the erasing method of the present invention includes: applying a gate voltage V to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326 and the P-type semiconductor substrate 30gSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd simultaneously satisfies the following conditions: the N-type transistor 32 satisfies V when erasedsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or satisfy VsubTo earth, VsHigh pressure, VdIs floating and Vg0 or less than 2V。
In summary, referring to fig. 2 and fig. 3, when the eeprom has the N-type transistor 32, the same type of P-type ions are further implanted into the P-type semiconductor substrate 30 near the junction of the first conductive gate 322 and the source 324 and drain 326 to increase the ion concentration, for example, by 1 to 10 times. The erasing method of the present invention includes: applying a gate voltage V to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326 and the P-type semiconductor substrate 30gSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd simultaneously satisfies the following conditions: the N-type transistor 32 satisfies V when erasedsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or satisfy VsubTo earth, VsHigh pressure, VdIs floating and Vg0 or less than 2V.
Referring to fig. 4, the single cell structure of the eeprom includes an N-type semiconductor substrate 40, which may also be a semiconductor substrate with an N-type well, wherein the N-type semiconductor substrate 40 is taken as an example, a P-type transistor 42, such as a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), is disposed on the N-type semiconductor substrate 40, the P-type transistor includes a first dielectric layer 420 disposed on the surface of the N-type semiconductor substrate 40, a first conductive gate 422 stacked on the first dielectric layer 420, and two P-type ion doped regions disposed in the N-type semiconductor substrate 40 to serve as a source 424 and a drain 426 thereof, respectively, and a channel is formed between the source 424 and the drain 426; the first conductive gate 422 further includes a floating gate 4221, a control dielectric layer 4222 and a control gate 4223 sequentially stacked on the first dielectric layer 420 from bottom to top, which is a single gate structure.
As shown in FIG. 5, the single cell structure of the EEPROM comprises an N-type semiconductor substrate 40 on which a P-type transistor 42 and a P-well (N-well) capacitor 44 are formed, separated by an isolation element 46. The P-type transistor 42, such as a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), includes a first dielectric layer 420 on the surface of the N-type semiconductor substrate 40, a first conductive gate 422 stacked on the first dielectric layer 420, and two N-type ion doped regions in the N-type semiconductor substrate 40 to serve as a source 424 and a drain 426, respectively, with a channel formed between the source 424 and the drain 426. The P-well capacitor 44 includes a second ion doped region in the N-type semiconductor substrate 40 as a P-well 440, a second dielectric layer 442 on the surface of the P-well 440, and a second conductive gate 444 disposed on the second dielectric layer 442 to form a top-dielectric-bottom plate capacitor structure. Wherein the first conductive gate 422 of the P-type transistor 42 and the second conductive gate 444 of the P-well capacitor 44 are electrically connected and separated by the isolation device 46 to form a single floating gate 48 structure.
Referring to fig. 4 and 5, in both the memory cell structures shown in fig. 4 and 5, when the eeprom has the P-type transistor 42, the same type of P-type ions are further implanted into the ion doped regions of the source 424 and the drain 426 near the boundary of the first conductive gate 422, so as to increase the ion concentration thereof, for example, by 1 to 10 times. The erasing method of the present invention includes: applying a gate voltage V to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426 and the N-type semiconductor substrate 40gSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd simultaneously satisfies the following conditions: the P-type transistor 42 satisfies V when erasedsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
In view of the above, as shown in fig. 4 and 5, when the eeprom has the P-type transistor 42, the N-type semiconductor substrate 40 near the boundary of the first conductive gate 422 and the source 424 and drain 426 is further implanted with the same type of N-type ions to increase the number of N-type ionsThe ion concentration is increased, for example, by 1 to 10 times. The erasing method of the present invention comprises: applying a gate voltage V to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426 and the N-type semiconductor substrate 40gSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd simultaneously satisfies the following conditions: the P-type transistor 42 satisfies V when erasedsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
According to the EEPROM disclosed by the present invention, since the erasing will have a relationship with the concentration of the driving voltage, and even affect the applied voltages of the source, drain and gate, the source, drain and gate can have the erasing effect as long as there is enough voltage difference, so that the grounding can be replaced by the negative voltage, and the required high voltage can be reduced; in view of the memory architecture capable of realizing low voltage operation, the present invention particularly proposes a condition that the source or the drain can be set to be floating during erasing, so that the erasing operation of the memory cell is simpler and faster.
The above-mentioned embodiments are merely illustrative of the technical spirit and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the content of the present invention and to implement the same, so that the scope of the present invention should not be limited by the above-mentioned embodiments, and all equivalent changes and modifications made in the spirit of the present invention should be covered by the scope of the present invention.

Claims (17)

1. A low-voltage fast erasing method for EEPROM includes a semiconductor substrate having at least one N-type transistor structure, the N-type transistor structure having a first conductive gate and at least two first ion doped regions located in the semiconductor substrate and at two sides of the first conductive gate to be used as source and drain respectively, and the first ion doped region at the junction of the first conductive gate and the source and drain being implanted with ions of the same type to increase the ion concentration, the erasing method includes:
respectively applying a gate voltage V to the first conductive gate, the source, the drain and the semiconductor substrategSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions:
satisfy VsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or
Satisfy VsubTo earth, VsHigh pressure, VdIs floating and Vg0 or less than 2V.
2. The method of claim 1, further comprising providing a capacitor structure on the surface of the semiconductor substrate and isolated from the at least one N-type transistor structure, the capacitor structure including a second ion-doped region in the semiconductor substrate and a second conductive gate electrically connected to the first conductive gate as a single floating gate, wherein the single floating gate applies the gate voltage Vg。
3. The method of claim 1, wherein implanting ions of the same type increases the concentration of ions in the semiconductor substrate or in the first ion-doped region by 1 to 10 times.
4. The method of claim 1, wherein the N-type transistor structure is an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
5. The method of claim 1, wherein the first doped region further comprises a Lightly Doped Drain (LDD).
6. A low-voltage fast erasing method for EEPROM includes a semiconductor substrate having at least a P-type transistor structure, the P-type transistor structure having a first conductive gate and at least two first ion doped regions located in the semiconductor substrate and at two sides of the first conductive gate to be used as source and drain respectively, and the first ion doped region at the junction of the first conductive gate and the source and drain being implanted with ions of the same type to increase the ion concentration, the erasing method includes:
respectively applying a gate voltage V to the first conductive gate, the source, the drain and the semiconductor substrategSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions:
satisfy VsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or
Satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
7. The method of claim 6, further comprising forming a capacitor structure on the surface of the semiconductor substrate and isolated from the at least one P-type transistor structure, the capacitor structure including a second ion-doped region in the semiconductor substrate and a second conductive gate electrically connected to the first conductive gate as a single floating gate, wherein the single floating gate applies the gate voltage Vg。
8. The method of claim 6, wherein implanting ions of the same type increases the concentration of ions in the semiconductor substrate or in the first ion-doped region by 1 to 10 times.
9. The method of claim 6, wherein the P-type transistor structure is a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
10. The method of claim 6, wherein the first doped region further comprises a Lightly Doped Drain (LDD).
11. A low-voltage fast erasing method for EEPROM includes a semiconductor substrate with at least one transistor structure, the transistor structure has a first conductive grid and at least two first ion doped regions in the semiconductor substrate and on two sides of the first conductive grid to be used as source and drain respectively, and the semiconductor substrate at the junction of the first conductive grid and the source and drain is implanted with ions of the same type to increase the ion concentration, the erasing method includes:
respectively applying a gate voltage V to the first conductive gate, the source, the drain and the semiconductor substrategSource voltage VsDrain voltage VdAnd a substrate voltage VsubAnd satisfies the following conditions:
when the transistor structure is an N-type transistor
Satisfy VsubTo earth, VdHigh pressure, VsIs floating and Vg0 or less than 2V; or
Satisfy VsubTo earth, VsHigh pressure, VdIs floating connected, andVg0 or less than 2V; and
when the transistor structure is a P-type transistor
Satisfy VsubHigh pressure, Vs＝0，VdIs floating and VgHigh pressure or less than 2V; or
Satisfy VsubHigh pressure, Vd＝0，VsIs floating and VgHigh pressure or less than 2V.
12. The method of claim 11, further comprising providing a capacitor structure on the surface of the semiconductor substrate and isolated from the at least one transistor structure, the capacitor structure including a second ion-doped region in the semiconductor substrate and a second conductive gate electrically connected to the first conductive gate as a single floating gate, wherein the single floating gate applies the gate voltage Vg。
13. The method of claim 12, wherein when the transistor structure is an N-type transistor, the first and second ion-doped regions are N-type doped regions, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well; and when the transistor structure is the P-type transistor, the first ion doped region and the second ion doped region are P-type doped regions, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well.
14. The method of claim 11, wherein when the transistor structure is an N-type transistor, the first ion-doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well; and when the transistor structure is the P-type transistor, the first ion doped region is a P-type doped region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well.
15. The method of claim 11, wherein implanting ions of the same type increases the concentration of ions in the semiconductor substrate or in the first ion-doped region by 1 to 10 times.
16. The method of claim 11, wherein the transistor structure is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
17. The method of claim 11, wherein the first doped region further comprises a Lightly Doped Drain (LDD).
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