FR3085530B1 - Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible. - Google Patents

Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible. Download PDF

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Publication number
FR3085530B1
FR3085530B1 FR1857840A FR1857840A FR3085530B1 FR 3085530 B1 FR3085530 B1 FR 3085530B1 FR 1857840 A FR1857840 A FR 1857840A FR 1857840 A FR1857840 A FR 1857840A FR 3085530 B1 FR3085530 B1 FR 3085530B1
Authority
FR
France
Prior art keywords
integrated circuit
memory cell
fuse device
circuit containing
dis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1857840A
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English (en)
Other versions
FR3085530A1 (fr
Inventor
Pascal Fornara
Fabrice Marinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1857840A priority Critical patent/FR3085530B1/fr
Priority to US16/546,002 priority patent/US10923484B2/en
Priority to CN201910813356.XA priority patent/CN110875322A/zh
Priority to CN201921428861.4U priority patent/CN210897284U/zh
Publication of FR3085530A1 publication Critical patent/FR3085530A1/fr
Application granted granted Critical
Publication of FR3085530B1 publication Critical patent/FR3085530B1/fr
Priority to US17/141,498 priority patent/US11322503B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate
    • H10B20/367—Gate dielectric programmed, e.g. different thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/50—ROM only having transistors on different levels, e.g. 3D ROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Circuit intégré comportant au moins une cellule mémoire (CM) intégrant un dispositif anti-fusible (DIS) comportant un transistor d'état (TR) possédant une grille de commande (EG) et une deuxième grille (FG) configurée pour être flottante de façon à conférer un état non claqué au dispositif anti-fusible (DIS) ou électriquement couplée à la grille de commande de façon à conférer un état claqué au dispositif antifusible (DIS).
FR1857840A 2018-08-31 2018-08-31 Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible. Active FR3085530B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1857840A FR3085530B1 (fr) 2018-08-31 2018-08-31 Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.
US16/546,002 US10923484B2 (en) 2018-08-31 2019-08-20 Integrated circuit including at least one memory cell with an antifuse device
CN201910813356.XA CN110875322A (zh) 2018-08-31 2019-08-30 包括具有反熔丝器件的至少一个存储器单元的集成电路
CN201921428861.4U CN210897284U (zh) 2018-08-31 2019-08-30 集成电路和半导体晶片
US17/141,498 US11322503B2 (en) 2018-08-31 2021-01-05 Integrated circuit including at least one memory cell with an antifuse device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1857840 2018-08-31
FR1857840A FR3085530B1 (fr) 2018-08-31 2018-08-31 Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.

Publications (2)

Publication Number Publication Date
FR3085530A1 FR3085530A1 (fr) 2020-03-06
FR3085530B1 true FR3085530B1 (fr) 2020-10-02

Family

ID=65685467

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1857840A Active FR3085530B1 (fr) 2018-08-31 2018-08-31 Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.

Country Status (3)

Country Link
US (2) US10923484B2 (fr)
CN (2) CN210897284U (fr)
FR (1) FR3085530B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3085530B1 (fr) * 2018-08-31 2020-10-02 St Microelectronics Rousset Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.
TWI770804B (zh) * 2021-02-04 2022-07-11 華邦電子股份有限公司 記憶體裝置及其製造方法
US20230251113A1 (en) * 2022-02-09 2023-08-10 Cyngn, Inc. Modular sensor system for automated guided vehicles

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2755781B2 (ja) * 1990-04-23 1998-05-25 株式会社東芝 半導体記憶装置およびその製造方法
JPH0834292B2 (ja) * 1990-06-22 1996-03-29 シャープ株式会社 半導体記憶装置の書き込み方法
FR2697673B1 (fr) * 1992-10-29 1994-12-16 Gemplus Card Int Circuit à fusible, pour circuit intégré.
KR100500579B1 (ko) * 2003-06-28 2005-07-12 한국과학기술원 씨모스 게이트 산화물 안티퓨즈를 이용한 3-트랜지스터한번 프로그램 가능한 롬
JP4437655B2 (ja) * 2003-10-02 2010-03-24 三菱電機株式会社 半導体装置及び半導体装置の駆動回路
US6903436B1 (en) * 2004-04-27 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-time programmable electrical fuse utilizing MOS oxide breakdown
US7271643B2 (en) * 2005-05-26 2007-09-18 International Business Machines Corporation Circuit for blowing an electrically blowable fuse in SOI technologies
JP4884077B2 (ja) * 2006-05-25 2012-02-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4818024B2 (ja) * 2006-08-23 2011-11-16 株式会社東芝 半導体記憶装置
KR100866960B1 (ko) * 2007-02-16 2008-11-05 삼성전자주식회사 반도체 집적 회로
KR100909799B1 (ko) * 2007-11-01 2009-07-29 주식회사 하이닉스반도체 퓨즈를 포함하는 비휘발성 메모리 소자 및 그 제조방법,퓨즈 리페어 방법
CN102150268B (zh) * 2008-09-30 2013-07-31 株式会社半导体能源研究所 半导体存储器件
US8050077B2 (en) * 2009-02-25 2011-11-01 Advanced Micro Devices, Inc. Semiconductor device with transistor-based fuses and related programming method
CN102110688B (zh) * 2009-12-29 2013-04-17 中芯国际集成电路制造(上海)有限公司 序列号发生器及其形成方法、集成电路及其形成方法
TWI446361B (zh) * 2010-01-21 2014-07-21 Etron Technology Inc 具有失能電路之記憶體及使記憶體失能之方法
TWI462116B (zh) * 2010-01-25 2014-11-21 Macronix Int Co Ltd 具有改良串列選擇線和位元線接觸佈局的三維記憶陣列
JP5466594B2 (ja) * 2010-07-29 2014-04-09 ルネサスエレクトロニクス株式会社 半導体記憶装置及びアンチヒューズのプログラム方法
JP5636794B2 (ja) * 2010-07-30 2014-12-10 ソニー株式会社 半導体装置及びその駆動方法
US10229746B2 (en) * 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US9431497B2 (en) * 2013-05-21 2016-08-30 Globalfoundries Singapore Pte. Ltd. Transistor devices having an anti-fuse configuration and methods of forming the same
CN104979362B (zh) * 2014-04-10 2019-11-19 三星电子株式会社 具有翅片式有源图案和栅极节点的半导体装置
KR102369926B1 (ko) * 2015-04-10 2022-03-04 에스케이하이닉스 주식회사 안티 퓨즈 소자, 안티 퓨즈 어레이 및 그 동작 방법
KR102106664B1 (ko) * 2016-06-22 2020-05-06 매그나칩 반도체 유한회사 Otp 셀 및 이를 이용한 otp 메모리 어레이
FR3054920B1 (fr) * 2016-08-05 2018-10-26 Stmicroelectronics (Rousset) Sas Dispositif compact de memoire non volatile
KR102684720B1 (ko) * 2016-12-09 2024-07-12 삼성전자주식회사 안티-퓨즈 소자 및 그 안티-퓨즈 소자를 포함한 메모리 소자
US9953990B1 (en) * 2017-08-01 2018-04-24 Synopsys, Inc. One-time programmable memory using rupturing of gate insulation
FR3085530B1 (fr) * 2018-08-31 2020-10-02 St Microelectronics Rousset Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.
US11201162B2 (en) * 2018-12-21 2021-12-14 Flashsilicon Incorporation Methods of erasing semiconductor non-volatile memories

Also Published As

Publication number Publication date
US20200075611A1 (en) 2020-03-05
CN210897284U (zh) 2020-06-30
CN110875322A (zh) 2020-03-10
FR3085530A1 (fr) 2020-03-06
US10923484B2 (en) 2021-02-16
US11322503B2 (en) 2022-05-03
US20210126000A1 (en) 2021-04-29

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