FR2637418A1 - Transistor bipolaire a grande vitesse et son procede de fabrication - Google Patents

Transistor bipolaire a grande vitesse et son procede de fabrication

Info

Publication number
FR2637418A1
FR2637418A1 FR8907861A FR8907861A FR2637418A1 FR 2637418 A1 FR2637418 A1 FR 2637418A1 FR 8907861 A FR8907861 A FR 8907861A FR 8907861 A FR8907861 A FR 8907861A FR 2637418 A1 FR2637418 A1 FR 2637418A1
Authority
FR
France
Prior art keywords
bipolar transistor
manufacturing
high speed
speed bipolar
locos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8907861A
Other languages
English (en)
Other versions
FR2637418B1 (fr
Inventor
Soon-Kwon Lim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2637418A1 publication Critical patent/FR2637418A1/fr
Application granted granted Critical
Publication of FR2637418B1 publication Critical patent/FR2637418B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

L'invention décrit un transistor bipolaire et son procédé de fabrication dans lequel un écartement minimal entre la base 9 et l'émetteur 13 d'un transistor bipolaire est déterminé en faisant appel au phénomène du " bec d'oiseau " se produisant lors du procédé dit LOCOS (LOCale Oxydation du Silicium).
FR8907861A 1988-09-23 1989-06-14 Transistor bipolaire a grande vitesse et son procede de fabrication Expired - Lifetime FR2637418B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880012323A KR910005403B1 (ko) 1988-09-23 1988-09-23 고성능 바이폴라 트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
FR2637418A1 true FR2637418A1 (fr) 1990-04-06
FR2637418B1 FR2637418B1 (fr) 1996-12-20

Family

ID=19277971

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8907861A Expired - Lifetime FR2637418B1 (fr) 1988-09-23 1989-06-14 Transistor bipolaire a grande vitesse et son procede de fabrication

Country Status (6)

Country Link
US (1) US5162244A (fr)
JP (1) JPH0693459B2 (fr)
KR (1) KR910005403B1 (fr)
DE (1) DE3919575C2 (fr)
FR (1) FR2637418B1 (fr)
GB (1) GB2223126B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2679379A1 (fr) * 1991-07-16 1993-01-22 Thomson Composants Militaires Procede de fabrication de circuits integres avec electrodes tres etroites.

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3191479B2 (ja) * 1993-04-01 2001-07-23 日本電気株式会社 バイポーラトランジスタの製造方法
DE102005021932A1 (de) * 2005-05-12 2006-11-16 Atmel Germany Gmbh Verfahren zur Herstellung integrierter Schaltkreise
US8017480B2 (en) * 2006-06-13 2011-09-13 Macronix International Co., Ltd. Apparatus and associated method for making a floating gate cell in a virtual ground array

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004292A2 (fr) * 1978-03-27 1979-10-03 International Business Machines Corporation Procédé de fabrication d'un transistor bipolaire de type MESA présentant des régions d'émetteur et de base auto-alignées
EP0094482A2 (fr) * 1982-05-18 1983-11-23 International Business Machines Corporation Procédé de fabrication d'un transistor à émetteur peu profond et à base intrinsèque étroite
EP0122004A2 (fr) * 1983-03-08 1984-10-17 Trw Inc. Construction d'un transistor bipolaire
US4686763A (en) * 1985-10-02 1987-08-18 Advanced Micro Devices, Inc. Method of making a planar polysilicon bipolar device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536950A (en) * 1983-02-10 1985-08-27 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor device
DE3683183D1 (de) * 1985-04-10 1992-02-13 Fujitsu Ltd Verfahren zum herstellen eines selbtsausrichtenden bipolartransistors.
DE3571366D1 (en) * 1985-09-21 1989-08-10 Itt Ind Gmbh Deutsche Method of applying a contact to a contact area for a semiconductor substrate
US4746623A (en) * 1986-01-29 1988-05-24 Signetics Corporation Method of making bipolar semiconductor device with wall spacer
EP0239652B1 (fr) * 1986-03-22 1991-07-24 Deutsche ITT Industries GmbH Procédé pour fabriquer un circuit intégré monolithique comportant au moins un transistor planaire bipolaire
US4883772A (en) * 1986-09-11 1989-11-28 National Semiconductor Corporation Process for making a self-aligned silicide shunt
DE3683054D1 (de) * 1986-12-12 1992-01-30 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor.
US4829015A (en) * 1987-05-21 1989-05-09 Siemens Aktiengesellschaft Method for manufacturing a fully self-adjusted bipolar transistor
JPS6445165A (en) * 1987-08-13 1989-02-17 Toshiba Corp Semiconductor device and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004292A2 (fr) * 1978-03-27 1979-10-03 International Business Machines Corporation Procédé de fabrication d'un transistor bipolaire de type MESA présentant des régions d'émetteur et de base auto-alignées
EP0094482A2 (fr) * 1982-05-18 1983-11-23 International Business Machines Corporation Procédé de fabrication d'un transistor à émetteur peu profond et à base intrinsèque étroite
EP0122004A2 (fr) * 1983-03-08 1984-10-17 Trw Inc. Construction d'un transistor bipolaire
US4686763A (en) * 1985-10-02 1987-08-18 Advanced Micro Devices, Inc. Method of making a planar polysilicon bipolar device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, Rochester,N.Y.,US, 16-19 mai 1988; Y.OKITA et al.:"A Novel BaseEmitter Self-Alignment Process for High Speed Bipolar LSIS",p.2241-2244 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2679379A1 (fr) * 1991-07-16 1993-01-22 Thomson Composants Militaires Procede de fabrication de circuits integres avec electrodes tres etroites.
WO1993002470A1 (fr) * 1991-07-16 1993-02-04 Thomson Composants Militaires Et Spatiaux Procede de fabrication d'un circuit integre a transfert de charges avec systeme d'anti-eblouissement
US5399525A (en) * 1991-07-16 1995-03-21 Thomson-Csf Semiconducteurs Specifiques Process for manufacturing integrated circuits with very narrow electrodes

Also Published As

Publication number Publication date
DE3919575A1 (de) 1990-03-29
KR900005616A (ko) 1990-04-14
KR910005403B1 (ko) 1991-07-29
GB2223126B (en) 1992-09-23
JPH02109340A (ja) 1990-04-23
GB8914909D0 (en) 1989-08-23
US5162244A (en) 1992-11-10
JPH0693459B2 (ja) 1994-11-16
GB2223126A (en) 1990-03-28
FR2637418B1 (fr) 1996-12-20
DE3919575C2 (de) 1994-02-17

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