FR2495382A1 - FIELD EFFECT CONTROL DEVICE - Google Patents

Abstract

The invention relates to power rectifiers. A semiconductor rectifier is designed to be off in the absence of bias and can be switched to conductive by applying bias to a gate 68, 69 of a monolithically integrated MOS structure. to the rectifier, so as to induce a conductive channel between the anode 62 and the cathode 64 of the rectifier. The device provides forward and reverse blocking and has a low forward voltage drop in the conductive state. Application to motor control circuits. (CF DRAWING IN BOPI)

Description

The present invention relates to semiconductor devices having a

power field, and she

  more particularly relates to semi-rectifiers

  field-controlled conductors which have a structure

  control panel with integrated field effect in a mono-

  lithic to the straightener structure.

  For power switching applications, in electrical systems such as motor control circuits and power supplies operating on

  low to medium frequencies (0-2000 Hz), it is desirable

  performance at a high speed and low losses, with high levels of current and voltage. Three-terminal devices

  the prior art that can be used to control the power

  The supplied power to a load includes the MOS field effect transistor and the MOS gate thyristor. Among

  the MOS power transistors of the prior art shown in FIG.

  those described in U.S. Patent 4,072,975.

  and U.S. Patent 4,145,703. Figures 1 and 2 represent

  schematically

  MOS power sistors and Figure 3 shows their characteristics.

  operating characteristics. These devices were manufactured using either diffusion techniques

  of. plan type to form a DMOS structure 20, as

  shown in FIG. 1, either by etching V-shaped grooves to form a VMOS structure 21, such as

  shown in Figure 2. In each case, for

  Positive ions applied to the drain, the junctions 22, 23

  between the basic regions P, 24, 25, and the regions of

  placement type N, 26, 27, respectively shown in Figures 1 and 2, block the flow of current between the drains 28, 29 and the sources 30, 31, in the absence

  of grid polarizations. The application of a polarisa-

  positive gate, with respect to the source, causes the formation of an N-type inversion layer, 32, 33, in the respective base regions of

  type P, under the respective gate electrodes 34, 35.

  This inversion layer allows the conduction of an electrical current from the drain to the source, which produces the direct conduction characteristic represented by

  in Figure 3. The increase in grid polarization

  the, for example VG1 to VG5 increases the conductivity of the inversion layer and thus allows the circulation of a

  higher IDS drain current. For negative voltages

  When applied to the drain, the device conducts the current as a forward-biased P-N junction diode and can not block current flow. As a result, these devices are only operated with

positive applied to the drain.

  In the MOS transistors, only one current of majority carriers (electrons) flows between the drain and the source. The circulation of this current is therefore

  limited by the concentration of majority

  trons here) in the channel and displacement regions, which determines their resistivity. In the case of devices designed to operate at more than 100 V, the resistance of the displacement region becomes large because the concentration of majority carriers in this region must be low and the width of this region (W) must be

  to be large enough to withstand the blocking voltages of the

  positive. Due to the high resistance of the displacement region, the high voltage MOS transistors must be operated with low current densities to achieve low forward voltage drops. A typical operating current density is about 50 A / cm, with a forward voltage drop of 1.5 V for a device capable of blocking up to 600 V. Despite this disadvantage of high resistance to conductive state, power MOS transistors have

  the advantage of requiring power levels of attack

  The gate gate is smaller than that of the bipolar transistors because the gate voltage signal is applied on either side of an insulating layer. In these devices, it is also possible to block the drain current by decreasing

  the gate voltage up to the source potential. This block

  age by the grid can be performed with a current gain

  higher than for bipolar tr msistors.

  The MOS gate thyristor is another type of

  device of the prior art. Characteristic features

  Such ticks are described in GB 1,356,670, U.S. Patent 3,753,055 and U.S. Patent 3,831,187. A MOS gate thyristor is a PNPN thyristor structure, shown schematically in FIGS. 4 and 5, in FIG.

  which can trigger a priming with a positive reaction

  tive by applying a voltage on a MOS grid. In the device 40 of FIG. 4, the MOS gate is formed on a surface 41 which starts from the cathode N + 42, passes through the base P 43 and enters a small part of the base N 44. In the device 50 of FIG. 5, the MOS grid is formed on a surface 51 which extends along a V-shaped groove 52 and which starts from the cathode N + 53, passes through the

  base layer P 54 and enters the base N 55. These

  positively block the flow of current with

  positive or negative ions applied to their anodes

  45, 46, in the absence of gate bias.

  However, for positive anode voltages, the provisions

  may be brought into the conduction mode by the application of an appropriate positive voltage on the

  respective grids 46, 57. When a gate voltage is

  sitive is applied, the electric field on both sides

  gate oxide layers 47, 58 produce an impoverished

  in the base P, under the gate electrode. As a result, the depletion layer in the base P extends closer to the cathode region N + below the gate. This reduces the thickness of the non-depleted base region P of the upper NPN transistor, under

  the grie electrode, and therefore increases its current gain.

  It is well known that a PNPN thyristor structure

  mute from a current blocking state to a conduction state

  when the sum of the current gains of the

  NPN and PNP sistors, ie 0 <NPN and <PNP respectively.

  pass the unit. In the MOS gate thyristor, as the gate bias increases, the gain of the upper NPN transistor increases until 0 NPN + U. PNP exceeds unity. At this point, a strong injection of carriers

  take place from the cathode N + to the base P so that the dis-

  positive switches to the conductive state. This requires that the N + P junction be forward biased with a voltage greater than 0.5V. Once this takes place, the device switches to the conductive state and the removal of the gate bias voltage does not reduce the

  in the blocked state, because of the reaction action

  positive self-maintenance which is inherent to the PNPN thyristor structure. Thus, these devices have the advantage of requiring a low gate power to prime the thyristor via the MOS gate, but they have no possibility of blocking by the gate. The device must therefore be reduced to

  blocking state by inverting the polarity of the anode

  of. Figure 6 shows the characteristic of thyris-

  tor to MOS grid and it shows that the devices of this

  type have a negative resistance characteristic.

  The object of the invention is to provide a rectifier

  controlled by field effect and able to convey a cou-

  rant, which offers blocking possibilities

  direct and opposite, and a slight fall in

  direct connection, this rectifier can be switched to the conductive state and blocked with a low gate voltage and

  a very weak current, and therefore with a weak power.

  Another object of the invention is to provide a device which has a very high grid gate gain, high di / dt capabilities, and high dv / dt capabilities. The invention also aims to provide a device capable of functioning without being damaged in

  high levels of temperature and radiation.

  The invention therefore consists of a combination of

  monolithic structure of a straightener and a struc-

  A field effect control circuit for controlling the conductive state of the rectifier by inducing a conductive channel in a region of the rectifier for the purpose of controlling the conductive-locked state of PN junctions in the rectifier. The rectifier comprises a multilayer structure in a block of semiconductor material having a contact on one surface of the block and another contact on another surface of the block. The field effect control structure induces a conductive channel in a rectifier element to establish an electrically conductive path that connects one of the contacts to a second

element of the rectifier.

  The rest of the description refers to the drawings

  appended which respectively represent: FIGS. 1 and 2: partial diagrammatic sections of MOS gate power field effect transistors;

  Figure 3: a graphical representation of the characteristics

  characteristics of the transistors shown schematically in FIGS. 1 and 2; Figures 4 and 5: Partial schematic sections of MOS grid thyristors

  Figure 6: a graphical representation of a

  typical feature of the thyristors shown in Figures 4 and 5;

  Figure 7: a schematic representation of

  sectional view of a grid-controlled rectifier

  form to the invention; Figures 8 to 13: schematic representations

  partial, sectional, other embodiments of the re-

  FIG. 14: a graphical representation of the FIG.

  characteristic of the gate-controlled rectifier of the in-

vention

  Figure 15: a comparative graphical representation

  tive switching signals for

  devices of the prior art and for the rectifier com-

mandé by grid of the invention.

  Figure 7 shows a shape of the fundamental structure of the device of the invention. The device 60 comprises a block 61 of semiconductor material such as silicon, which comprises a first layer 62 of a conductivity type, P in FIG. 7, and a region of

  base 63 of opposite conductivity, N in FIG.

  first layer 62 may be made by diffusion in a block to produce the anode-base structure of the device, or it is possible to grow a layer by epitaxy on

  a block of the desired conductivity type, to produce the

  two-layer combination. Several islands 64, which here are of the conductivity type P, are formed by diffusion or by any other suitable technique in the layer 63,

  by being spaced from each other and contiguous to the over-

  free face 65 of the block 61. An island N + 66 is formed in the base layer 63, next to the island 64. The characteristic doping levels for the N-type layer 63 are in the range of 1013 to 1016 cm 3 for the wearers of

  type N; for the anode layer 62, type P, the concentrations

  Doping trait characteristics are in the range of 10 8 to 10 cm 3 for P-type carriers; for the

  P-type islets 64, the typical doping concentrations

  are 1016 to 1018 cm 3; and for the N + type islets 66, the characteristic doping concentrations

18 29 -3

  are 10 to 10 cm. A layer 67 of dielectric material

  is formed on part of the free surface 65

  comprising an area of the outer surface of islands 64 ad-

  and the region of the base layer 63 which separates the adjacent islands 64 and which contains the island 66. A contact 68, 69 of conductive material, such as aluminum or conductive polycrystalline silicon, is formed on the layer dielectric 67, and covers a portion of an island

  64 and a portion of the base layer 63, in position ad-

  the island 64, to act as a gate electrode. A layer 70 of conductive material such as aluminum or conductive polycrystalline silicon is deposited on the center of each of the batches 64 to form

  ohmic contact with the latter. A layer 72 of

  The conductive substrate, such as aluminum or polycrystalline silicon, is deposited on the surface 71 of the block 61, to form an ohmic contact with the layer 62. Although there are shown bands for the top surface pattern conductive contacts 68, 69 and 70 in Figure 7, one skilled in the art will note that one could use many geometric repetitive contact patterns, such as small contact pads disposed on the surface at a short distance from each other. other. The device is highly interdigital, i.e. the width of the individual bands is small and the total number of bands is high. The pattern is repeated in the direction

  to cover the entire semiconductor device

  tor. Each of the conductive contacts extends to a lateral edge of the device, at which the contacts 68, 69 are connected to a source of electrical potential, the contacts 70 are connected to a source of electrical potential of a different polarity of that of the source

  connected to the contacts 68, 69, and the contact 72 is connected

  to a source of electrical potential of one polarity

  different from that of the source connected to the contacts 70.

  The device shown in FIG.

  the operating characteristics shown in Fig. 14 and it operates in the following manner. The

  contact 70 being at the potential of the mass, and no polarity

  tion being applied to the gate electrode 68, the

  The application of negative voltages to contact 72 does not

  no current because junction 73 is polar.

  in the opposite direction. This provides the possibility of blocking in reverse. When no bias is applied to

  the gate electrode 68, the application of positive voltages

  Touching 72 does not move any more

  rant, because the junction 74 is reverse biased.

  This provides the possibility of blocking live, as well as a desired feature of blocking the device at rest. However, if a positive bias is applied

  on the gate electrode 68, an inversion layer extends

  As a result of the ohmic contact 70 to the base N 63, it can be formed under the gate in the base P of the region 78 of the batch 64, immediately below the insulating layer 67, and a charge generator accumulation layer. N type can

  form in region 79 of base N 63. The layer of

  N-type version which is now in the region 78 of the island P 64 and the accumulation layer in the region 79 of the base N now connect the ohmic contact 70 to the N + flow 66, in the middle of the device . A positive bias applied to the contact 72 now circulates a current of the P + layer 62, acting as anode, to the N + island 66, then to the contact 70,

  cathode function, passing through the

  N-type modulation 79 and the N-type inversion layer 78. The path from layer 62 to N + island 66 operates in a manner analogous to that of a P-I-N diode.

  1.0 shown at 80 in Figure 7, and the control region

  field effect is framed in 81. Conductivity

  of the current path passing through the base N 63 between the

  P + 62 and the island N + 66 will be modulated (increased) by

  current flow due to the injection of a concentra-

  high number of minority carriers (holes here) in

  N 63, from layer 62. Because the

  sion is supported by the base N 63 in the modes of blocking

  cage in direct and in reverse, the width W of the path located between the layer P + 62 and the island P 64 determined the maximum blocking voltages. This width must be increased to allow operation with high voltages. The circulation of a current with conductivity modulation is therefore very important to obtain a small direct voltage drop with high direct current dities.

  in high voltage devices. A characteristic density

  Direct operating current is approximately 500 A / cm2 for a direct voltage drop of 1.5 V,

  a device capable of blocking up to 600 V. If we invert

  all types of conductivity, similar performance characteristics can be obtained by applying

  electrical potentials of polarities opposite to the con-

conductive tacts.

  Figure 8 schematically shows another embodiment of the grid-controlled rectifier of the invention. The device 90 of Figure 8 differs from

  that of Figure 7 by removing the islet Born 66.

  The removal of block 66 requires the application of a potential to gate contact 91 to create an accumulation layer 99 under dielectric layer 67 to produce an N-type carrier region below the gate. To achieve this with the lowest spreading resistance in the flow path of the current under the gate, it is necessary that the gate contact 91 extends over the entire width of the gate region which

  connects the! 64 adjacent lots. A contact of smaller width

  Instead, it would create the necessary accumulation layer 99 of carriers N under the gate to perform the function of the N + batches 66, in the case of application of a potential to the gate. This decrease in the area of

  grid results in a decrease in gate capacity.

  When a positive bias is applied to the grid

  of the field effect control structure that is desired.

  framed by frame 93, a three-layer structure is

  formed in the region surrounded by the dotted rectangle

  92, which functions as a P-I-N structure.

  The current path in the rectifier involves

  the layer 62, the base region N 94, the accumulation layer

  N 99, an inversion layer 79 and the ohm-contact

that 70.

  Figure 9 schematically represents another

  embodiment of the invention. The device 100 com-

  takes a P region 62, a base region 94, P islands 102 and several N + lots 101, in each of the P islands 102. In this embodiment, the islands 101 make contact between the inversion layer located in the islands.

  islands 102 and the conductive contact 70. Two conductive contacts

  107, separated by a space 108, are arranged on the dielectric layer 67 so as to cover part of the batches 101, a region of the batches 102 and a part of the

  94. The application of a positive grid polarization

  to a control electrode 107, within the dashed frame 103, produces an accumulation layer in the base region N, located immediately underneath the gate, and

  an inversion layer in the island P 102, located immediately

  under the dielectric layer 67 and extending from the island N + 101 to the base N 94, closing the current path which will

  from the base N to the island N + 101, via the island P 102.

  This structure comprises a parasitic P-N-P-N thyristor located in the anode 62, the base 94, the P 102 island and the

  Islets N + 101 in the region designated by frame 106.

  To obtain the desired performances for this device, as regards the switching to the blocking state, at the time of the removal of the gate bias, it

  is very important that the priming mechanism by reaction

  positively in this parasitic thyristor be removed.

  This can be achieved by preventing the N + islands 101 from injecting electrons into the P islands.

  respectively, thus avoiding the triggering of the

  a positive feedback priming of the P-N-P-N thyristor.

  The suppression of carrier injection from

  islands N + 101 can be obtained by giving a small di-

  Lateral dimension (L) at N + islands 101. The lateral dimension

  (L) of the islands N + 101 must be sufficiently small so that, when the device conducts the current of the channel 78 to the cathode contact 70, the direct polarization of the junction 105 between the islands N + 101 and the island

  P 102 does not exceed 0.5 V. Another technique that can be

  should be used to suppress priming by positive reaction.

  In the P-N-P-N thyristor, it is possible to introduce recombination centers in the P 102 region and the N 94 base, in order to reduce the gains 0 <NPN and o <PNP. Diffusion recombination centers can be formed in the substrate.

  deep-level impurities, such as gold, or by irra-

  diation of the substrate with high energy particles

like electrons.

  Distinctive features between a thyris-

  MOS gate control tor, such as that shown in Figure 4, and the device of the invention, shown

  in Figure 9, consist first of all in that the

  positive embodiment of the invention contains N + regions 101 of

  lateral pressure (L) much lower, to avoid

  a positive feedback priming characteristic of the MOS gate thyristor. Securing, in the rectifier enriched by the gate, the anode current it

  circulates exclusively through the conductive channel

  which is formed in island P 102, towards the contact of

  cathode 70, when the device conducts the current, tan-

  say that the current of the MOS gate thyristor flows vertically

  calmly in the entire island P 102, under the island N + 101. Troi

  seventh, in the rectifier enriched by the grill

  the, we can stop the anode current by removing the

  gate voltage applied to induce the conductive channel

  in the island P 102, while the anode current of the MOS gate thyristor continues to circulate after the gate voltage suppression, because of the self-sustaining nature of the action of the P-NP-N thyristor positive feedback. Note that the embodiment of FIG. 8 avoids this problem by eliminating the N + islands in

islands P 102.

  In another embodiment shown in FIG. 10, an N + island 111, filling the entire width between the adjacent P islands 114 and the N base 113, and coming into contact with a portion of the Pest islands formed in the N base. a positive bias is applied to the gate 115, an inversion layer is created in the region of the P islands immediately below the gate, and the current conduction path of the N + island 111 to the cathode contact 116 is established, which releases the device and allows the flow of a current in the PIN diode designated by the frame 112, and to the

  cathode contact 116, by the inversion layer.

  In the embodiment shown in FIG. 11, N + islands 125 have been added to the P islands 124 of the device 120, and these islands 125 establish

  current flow paths from the inversion layer

  present in the P-type islands 124, towards the contact

  116, when a positive bias is applied

  This embodiment also contains the parasitic PNPN thyristor described in connection with the embodiment shown in FIG. 9. As shown, the electrode 117, in the gate structure 118, for the purpose of unblocking the PIN diode 119. As shown previously with reference to FIG. 9, the positive feedback priming mechanism of this parasitic thyristor can be suppressed, maintaining a small lateral dimensiom (L) for the N + island 125, and establishing recombination centers in the islets. P 124 and base N 113. Note that the embodiment of FIG. 10 avoids this problem by eliminating

  N + batches inside islands P 102.

  In the device 130 which is shown schematically

  12, islands P + 133, strongly

  doped, were added to the P 132 islands in the N 131 base.

  The current path includes the P-I-N diode 134 which is

  created when a positive polarization with respect to

  conductive tact 137 is applied to the gate 136 in the grid-controlled structure 135, to produce a

  accumulation layer-immediately below the

  Dielectric board 67. An inversion duch is produced in island P 132 between island P + 133 and base N 131, to allow flow of anode current to

the cathode.

  Figure 13 represents yet another structure

  device that uses the invention. The semiconductor material block for a device 140 includes a low-doped N 141 base region and a more heavily doped N-region 142. In the core region 142,

  islands P + 143 are formed adjacent to a surface

  this free main 144 of the block. Islets P 145 are formed

  in the N 141 region and N + 150 islets are formed

  in P 145 islands, adjacent to the other

  main face 146 of the block. For a given current density, in forward conduction, this structure gives a lower direct voltage drop in the diode 152 than the embodiments described above, for the

  same blocking capacity in the forward direction. However. the capacity

  blocking city in the opposite direction is reduced because of the

  shorting the islands 143 by the conductive contact

  147. The operating characteristics of this

  are similar to those of other modes of

  when a forward bias is applied. When a reverse bias is applied to the conductive contact 147, in the absence of bias on the gate electrode 148, in the grid-controlled structure 151, a characteristic, shown at 160 in FIG. different in that breakdown occurs for reverse polarization

* much weaker.

  Figure 14 shows the operating characteristics of the gate-controlled rectifier. In this device, the junction 73 blocks the flow of current when negative voltages are applied to the anode contact 72, which gives the device a capacitance.

  reverse blocking up to the level at which the breakdown occurs, as seen in 161. When

  positive voltages are applied to the contact of ano-

  of 72, the junction 74 becomes polarized in reverse and

  block the flow of current, which gives the possibility

  blocking ability, in the absence of grid bias, up to the level at which the breakdown occurs, as seen in 162. However, if a positive bias is applied to the gate, this creates a traffic path of the current from the anode junction 73 to

  the cathode contact 70, which gives the characteristics

  represented for each of the gate voltages VG1-VG4. For high gate voltages (VG4), the conductivity of the inversion layer is high and the device has characteristics similar to those of a PN junction diode. In this case, the P + anode region injects minority carriers into the N base and modulates (increases) the conductivity of the N base. As a result, the device can be operated with high current densities ( typically 500 A / cm 2), with a small direct voltage drop (about 1.5 V). For lower grid voltages (VG1, VG2 'VG3), the circulation of the

  current may be limited by the conductivity of the

  reversal, which gives the current saturation

  shown in Figure 14. These features of the dis-

  Positive are distinguished from those of other

  the prior art. Compared to the MOS transistor, the

  grid enrichment system can be used with

  higher current densities, due to the

  tion of the conductivity of the base N by the circulation of the anode current. Unlike the MOS transistor, these

  devices also present a possibility of blocking

  cage in reverse. Compared to the MOS gate thyristor, the gate enrichment rectifier is distinguished by the absence of a negative resistance region.

  in the direct features. This region has

  the thyristor results from the positive feedback priming phenomenon which is absent in the

  grate enrichment rectifier.

  Unlike the control thyristor

  MOS grid, no self-initiated positive feedback

  maintained does not occur in the grid enrichment rectifier device. Therefore, if the gate voltage is reduced to the cathode potential while the device is conducting current, the inverting layer beneath the gate electrode ceases to exist and the anode current is blocked. This blockage occurs in

  two phases. First, most of the char-

  The injected and stored ge in the base N is extracted by the current passing through the junction 74 towards the P region 145, until this junction is polarized in the opposite direction. After this point, the rest of the stored charge of minority carriers decreases by recombination.

  We can compare the switching characteristic

  of the MOS transistor, the gate-controlled thyristor

  MOS and the grid enrichment rectifier,

  Figure 15. In this figure, the grid tension

  is applied at time t1 and deleted at time t2, for the three cases, as shown in trace 164. At time t2, the MOS transistor is blocked quickly, as

  shows the trace 165, and the duration of the transitional condition

  blocking capacity is determined by the load of the

  grid city. However, the MOS gate control thyristor continues to conduct the current, even after the gate voltage has been reduced to zero at time t2,

  as shown in trace 166, because in these arrangements

  the circulation of the current is maintained by the internal positive reaction mechanism. On the contrary,

  Grid enrichment rectifier hangs at the

  both t2 and trace 167, because the inverting layer beneath the gate electrode ceases to exist when the gate voltage is reduced to zero, and this interrupts the current flow path between anode and cathode terminals. In this case, the minority carriers that the anode injects into the base N to modulate its conductivity during forward current conduction, are conduction-extracted through the junction 74, until the latter becomes polarized in direction. reverse, as indicated in

  168. Potential minority shareholders who remain

  then appear gradually by recombination. As a result, the grid-enriched rectifier blocks at time t1, like the MOS transistor, but it blocks more slowly due to the conduction of a bipolar current. It should be noted that this switching speed

  slower of the grid enrichment rectifier

  comes for many applications, such as motor control circuits, while its low forward voltage drop, in comparison with the MOS transistor, is a

  important advantage because it reduces the power of

  and thus improves the efficiency of switching power.

  ciency. Other advantages consist in a better

  ability to tolerate peaks of current in the possibility

  operating at higher temperature, and in the

  a high level of radiation, which is what

  possible by suppressing priming by positive reaction

described above.

Claims (19)

  1. Rectifier device with enrichment by   grid, characterized in that it comprises: a block of   semiconductor material (61); a rectifier disposed in said block and having a first electrically conductive element (72) in contact with a first free surface (71) of the block, and a second electrically conductive element (70) in contact with a second surface free (65) of the body; and field effect control means (67, 68, 69) which are disposed adjacent the rectifier such that a control electrode (68, 69) of the control means is located adjacent to a region Rectifier (66) of a first conductivity type, to control the conductive-locked state   of the rectifier by inducing an oppo-   in this region of the rectifier.   2. Rectifier device according to claim   1, characterized in that the rectifier comprises: a first   first layer (62) of the semiconductor material block, adjacent to the first free surface of the block and having a first conductivity type; a second layer (63) of the   block of semiconducting material, placed continuously   in the first layer and having a conductivity type opposite to that of the first layer; a first island (64)   formed in the second layer by being spaced from the pre--   first layer, this first island having the first type of conductivity; the first electrically conductive element (72) in contact with a free surface (71) of the first layer (62); the second electrically conductive element (70) in contact with a free surface (65) of the first   island (64); and a third conductive element of electricity   cited (68, 69) constituting the control electrode of the control means Rectifier device according to claim 2, characterized in that the field effect control means comprise a gate electrode (68, 69) which is arranged near the first island (64) of the rectifier, to induce a channel of the rectifier. opposite conductivity type in the first island; and said gate electrode is separated from the first island by a dielectric material side (67). Rectifier device according to Claim 3, characterized in that the field effect control means comprise means for generating a channel of the opposite conductivity type in the first island (64), this channel extending from the second electrically conductive element (70) to the second layer (63) of the semiconductor material block (61) under the effect of applying a bias signal to the gate electrode. 5. Rectifying device according to any one   claims 3 or 4, characterized in that   further takes a second island (66, 111) of semi-material   conductor of the opposite conductivity type which is arranged   inside the second layer in the immediate position   adjacent to the dielectric layer (67).   Rectifier device according to claim 1, characterized in that the second island (111) meets the first island (64).   7. Rectifying device according to any one   Claims 3 to 6, characterized in that the means   control devices also include   yens for inducing an accumulation layer of the opposite conductivity type in the second layer (63), and in a position immediately adjacent to the dielectric layer (67). 8. Rectifying device according to any one   claims 5, 6 or 7, characterized in that   further comprises a third island (101, 105) of semiconductor material of the opposite conductivity type disposed within the first island (64) and in contiguous position   the second electrically conductive element (70).   9. Rectifying device according to any one   Claims 4 to 8, characterized in that it comprises   in addition, a highly separated island (133) of the first conductivity type, which is arranged inside the first   island (132) in a position contiguous with the second conductive element electricity supplier (137).   Rectifying device according to claim 1, characterized in that the block of semiconductive material (61) has a first layer (62) contiguous with a first free face (71) of the block, and a second layer   (63) contiguous with a second free face (65) of the block, oppo-   at the first free face and contiguous to the first layer; a first island (64) within the second   layer, spaced from the first layer and   gu to the second free face (65) of the block, the field effect control means (67, 68, 69) forming a conductive channel within the first island (64), in position   adjacent to the free-face wave (65) of the block, under the ef-   fet of the application of a control signal to the grid controlled means; a first electrically conductive element (72) for making electrical contact with the first layer (6 2); a second conductive element   electricity (70) for making electrical contact with   only with the first island (64); and a third electrically conductive element (68, 69) for applying the control signal to the field effect control means. Rectifying device according to claim 1, characterized in that the first layer (62) consists of a semiconducting material of a first conductivity type; the second layer (63) consists of a semiconducting material of a conductivity type opposite to that of the first layer; the first island (64) consists of a semiconductor material region of the first conductivity type located within the second layer; and the chanp control means is constituted by field effect means for forming a channel of the type of   opposite conductivity inside the first island, in positive   adjacent to the field effect control means, and   this channel connects the second conductive element of the electricity   cited (70) at the second layer (63).   A rectifier device according to claim 11, characterized in that the field effect control means comprises a layer of dielectric material (67) which partially overlaps the first island (64) and which covers a gate region of the second layer (63) adjacent to the first island, and the third electrically conductive element (68, 69) covers at least a portion of the dielectric material bend and partially overlaps the first batch and at least partially the grid region.   13. Rectifier device according to claim 11, characterized in that it further comprises a second island of semiconductor material (66, 111) strongly doped with carriers of the opposite conductivity type, which is   adjacent the first island (64) to the   inside the grid area and in an adjacent position   to the field effect control means.   Rectifier device according to claim   13, characterized in that the second island of semi-material   a conductor (66) adjacent the first island (64) is spaced therefrom; and the field effect control means comprise or means for forming a current-carrying accumulation layer of the type   opposite conductivity, to establish an electrical connection   only between the channel and the second island.   15. Rectifier device according to claim 13, characterized in that the second island (111) meets the first island and the field effect control means comprise means (115) for inducing a channel of the conductivity type opposite to the interior of the first island, to establish an electrical connection between the second electrically conductive element (105) and the second island. Rectifier device according to claim 12, characterized in that it further comprises: a set   first islands (64) arranged in spaced apart   of the second layer (63), in a position contiguous to the second free face (65) of the block, each of these first islands extending in a band over an entire dimension of the block, while each element of a set of seconds   electrically conductive elements (70) extend in   in a position contiguous to a respective first flow, covering a portion of this island, and each of the second electrically conductive elements is connected to a common source of electrical potential; and a plurality of field effect control means (67, 68, 69), each of which covers a portion of a respective first island, each of said field effect control means comprising one of a set of electrically conductive control electrodes (68, 69) connected to a common source of electrical potential, each of these   control electrodes being formed on a strip   one of a plurality of strips of dielectric material formed on the free-surface sec wave (65) of the block and each of which extends in a strip which covers at least a portion of a respective gate region from a set of regions each of these control electrodes covers a portion of a respective one of the first waves (64), adjacent to one of the grid regions.   Rectifier device according to claim 16, characterized in that the first conductive element   (72) consists of an aluminum layer formed on the first   first free surface (71) of the block; each of the second   conductive elements (70) consists of an aluminum strip formed on an outer surface of a respective one of the plurality of first streams (64); and the third element   conductor of electricity consists of a strip of aluminum   formed on an outer surface of a respective   strips of dielectric material (67).   Rectifier device according to claim 16, characterized in that the first conductive element of   the electricity (72) consists of a layer of polysilicon   conductive crystal formed on the first free face (71)   block; each of the second conductive elements of the electri-   tricity (70) consists of a polycrystalline silicon strip   conductor formed on an outer surface of a resident island   spot among all the first islets; and each of the third electrically conductive elements comprises a conductive polycrystalline silicon strip formed on an outer surface of a respective one of the strips of dielectric material (67).   19. Rectifier device according to claim 1, characterized in that the block of semiconductor material (140) comprises a first region (141) of a first type   of conductivity and a second region (142) doped with   relative to the first region with carriers of the first conductivity type; a first island (143) of a   type of conductivity opposite to the first one, arranged   contiguous with a first free face (144) of the block, within the second region (142); a second island (145) of the opposite conductivity type disposed within the first region (141) spaced from the second region and contiguous with a second free face (146)   block, opposite to the first free face; a first   electrically conductive member (147) which comes into contact with the first free face of the block; a second electrically conductive element (149) that contacts the second island; and the field effect control means   (148) for inducing a channel of the first type of con-   ductivity in the second island (145), in an adjacent position   to the field effect control means, this channel extends   the second conductive element to the first region, under the effect of the application of a control signal by   field effect to the field effect control means.