JPH0715998B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a high power, high speed and high frequency switching element is realized monolithically.

[Prior Art] Some conventional high power, high frequency and high frequency switching elements having low on-resistance have been used, for example, as shown in FIG.

FIG. 3 is a cross-sectional view showing the structure of a conventional conductivity-modulated metal oxide semiconductor field effect transistor (hereinafter referred to as CAT element) having a monolithic structure. First, the structure of this CAT element will be described. In the figure, the structure of the CAT element is such that the n ^{+ type} drain substrate of a conventional metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) formed by double diffusion is replaced with a p ⁺ type drain / collector layer. . More specifically, the drain drift layer 6 made of, for example, an n-type epitaxial layer is formed on one surface of the p ⁺ -type drain / collector layer 7. A plurality of p-type base regions 5 are formed at intervals on the surface of the drain drift layer 6, and two n ^{+ -type} source / emitter regions 4 are spaced from each other on the surface of the p-type base region 5. It is formed separately. On the surface of the drain drift layer 6 between the p-type base regions 5, the surface of the peripheral portion of the p-type base region 5, and a part of the surface of the n ^{+ -type} source / emitter region 4,
For example, an oxide film 3 made of silicon dioxide is formed. A gate electrode 2 made of metal is formed inside the oxide film 3, and the gate electrode extends to above the n ^{+ type} source / emitter region 4. Source / emitter electrodes 1 are formed on the central surface of p-type base region 5, another part of the surface of n ^{+ -type} source / emitter region 4, and the surface of oxide film 3. Here, the n ^{+ -type} source / emitter region 4, the p-type base region 5, and the drain drift layer 6 form an npn transistor parasitic on the MOSFET, and the p-type base region 5
And drain drift layer 6 and p ^{+ type} drain / collector layer 7
And form a pnp transistor parasitic on the MOSFET. A drain / collector electrode 8 is formed on the other surface of the p ⁺ -type drain / collector layer 7. G is a gate electrode terminal, S / E is a source / emitter electrode terminal, and D / C
Is a drain / collector electrode terminal.

FIG. 4 is a diagram showing an equivalent circuit of the CAT element of FIG. The equivalent circuit of this CAT element should be a MOSFET and pin diode D ₂ connected in series from an ideal current flow. However, in reality, the MOSFET and the parasitic npn transistor and pnp transistor are connected. It is a combination of a thyristor composed of and.

Next, the characteristics and operation of this CAT element will be described.
When the gate electrode terminal G and the source / emitter electrode terminal S / E are short-circuited and a forward bias voltage is applied between the drain / collector electrode terminal D / C and the source / emitter electrode terminal S / E, p
The in diode D ₂ is reverse biased and the reverse bias blocking characteristic appears. When a reverse bias voltage is applied between the drain / collector electrode terminal D / C and the source / emitter electrode terminal S / E, the diode D ₁ is reverse biased and the forward bias blocking characteristic appears. In this state, when a voltage higher than the threshold voltage of the MOSFET is applied between the gate electrode terminal G and the source / emitter electrode terminal S / E, a channel is formed in the p-type base region 5 and the MOSFET is activated. At the same time, the pin diode D ₂ causes a pin diode operation phenomenon, holes are injected from the p ⁺ -type drain / collector layer 7 to the drain drift layer 6, and the conductivity of the drain drift layer increases, so that the CAT element has a low on-resistance. Turn on. In order to turn off the CAT element, the gate electrode terminal G and the source / emitter electrode terminal S / E are short-circuited so that the voltage applied between these terminals is equal to or lower than the threshold voltage of the MOSFET. , The inversion region on the surface of the p-type base region 5 under the gate electrode 2 is returned to the original state, and the supply of electrons to the drain drift layer 6 is stopped. At the start of turn-off, a large amount of electrons injected until then are concentrated in the drain drift layer 6, but these electrons are injected into the p ⁺ -type drain / collector layer 7 and the current due to holes corresponding to them is generated. Flow into the p-type base region 5. If such a state continues, the concentration of electrons in the drain drift layer 6 decreases, but in order for the CAT element to turn off, the plasma of holes and electrons left must be canceled by recombination.

The above is a description of the operation of the CAT element when the thyristor area parasitic to the MOSFET does not latch at turn-on.The biggest problem with the CAT element is that the thyristor area causes a latching phenomenon at low current levels. ,
If the thyristor area latches, the gate control capability of the CAT element is lost, making it difficult to turn it off. The cause of the latching phenomenon is that the npn transistor and pnp in the thyristor region have high current density at turn-on.
This is because the transistors have a feedback effect on each other. The condition for the thyristor region to latch at turn-on is that the sum of the DC current amplifier ratios h _FE of the npn transistor and pnp transistor is> 1, and the voltage at the resistance R _S of the p-type base region 5 of the npn transistor due to the hole current. This is the case where the effect V _S becomes 0.4 to 0.8 V or more at 300 ° K.

FIG. 5 is a sectional view showing the structure of another CAT element which solves the above problems to a certain level. In the figure, a p ^{+ type} base central region 50 having a high impurity concentration is formed in the center of the p type base region 5, and an n ^{+ type} buffer layer 9 is provided between the drain drift layer 6 and the p ^{+ type} drain / collector layer 7. Has been inserted. The equivalent circuit of this CAT element is the same as the circuit shown in FIG. p ^{+ type} base central area 50
Reduces the DC current amplification factor h _FE of the parasitic npn transistor, and suppresses injection of holes from the p ^{+ type} drain / collector layer 7 to the drain drift layer 6 by the n ^{+ type} buffer layer 9 to amplify the DC current of the parasitic pnp transistor. By lowering the rate h _FE , the CAT element is less likely to latch at turn-on. That is, the latching current level is increased as compared with the CAT element shown in FIG. Also,
In Japanese Unexamined Patent Publication No. 57-120369, instead of the drain / collector layer 7 of FIG. 5, an n ^{+ type} layer and a P ^{+ type} island at a position corresponding to the gate electrode 2 on the lower surface of the n ^{+ type} layer. A CAT element provided with is disclosed. This p ^{+ type} island has almost the same width as the gate electrode, and the drain / collector layer 7 of FIG.
Has the same thickness as. Since the p ^{+ type} island is wider than the width between the base regions 5 and has the same thickness as the drain / collector layer 7, the effect of increasing the current level for latching is almost the same as that in the case of FIG.

[Problems to be Solved by the Invention] In the conventional CAT element used as a high-power, high-speed, high-frequency switching element, the thyristor region parasitic in the MOSFET has a low current level for latching, so that the CAT element operates normally. It is necessary to use this at a current level below the latching current level, and there is a problem that the gate control range is narrow.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device capable of increasing a latching current level in a thyristor region parasitic on a MOSFET and expanding a gate control range. .

[Means for Solving the Problems] A semiconductor device according to the present invention includes a first conductivity type semiconductor substrate having a first main surface and a second main surface, which serves as a drain layer and has a high impurity concentration. A first main surface of the first conductivity type semiconductor substrate, which is in contact with the first main surface, and a second main surface which faces the first main surface and which opposes each other. A conductive type semiconductor layer, a base region made of at least two second conductive type semiconductors formed in an island shape and having an exposed surface in a predetermined region of the second main surface of the first conductive type semiconductor layer; A source region made of a high-concentration first-conductivity-type semiconductor and having an exposed surface in a predetermined region of each base region and exposed in an island shape, and a second main surface of the first-conductivity-type semiconductor layer The drain region having a surface is opposed to the drain region through the drain region, and the drain region is sequentially adjacent to each side. A gate electrode is provided on the exposed surfaces of the base region and the source region through an insulating film, the exposed surface is on the second main surface of the substrate, and the bottom surface is in the substrate. Then, the bottom surface is opposed to the gate electrode, and the bottom surface is arranged in an island shape, and the width of the bottom surface corresponds to the distance between the two base regions arranged on the opposing gate electrode via the insulating film. And a second conductivity type semiconductor region having a high impurity concentration, the bottom surface of which is adjacent to the first main surface of the first conductivity type semiconductor layer and which is connected to the same potential as the drain layer of the substrate. .

[Operation] According to the present invention, the exposed surface is formed on the second main surface of the first-conductivity-type semiconductor substrate having a high impurity concentration, and the bottom surface is formed in the substrate. The bottom surface faces the gate electrode to form an island shape. The second conductivity type semiconductor region having a high impurity concentration is provided, and the width of the bottom surface of the second conductivity type semiconductor region is such that the two base regions provided on opposite gate electrodes with an insulating film interposed therebetween. Of the second conductivity type semiconductor region is connected to the drain layer of the substrate at the same potential as that of the second conductivity type semiconductor region. The injection of carriers from the conductivity type semiconductor region to the first conductivity type semiconductor layer, which is the drain layer, is suppressed, and the direct current amplification factor h _{FE of} the transistor parasitic on the MOSFET decreases. Further, the carriers pass from the second-conductivity-type semiconductor region to a narrow region restricted by the width of the second-conductivity-type semiconductor region and the distance between at least two source regions. Therefore, carrier modulation can be applied only to this narrow region. As a result, the conductivity of the first-conductivity-type drain semiconductor layer is modulated to the same level as the conventional one.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In addition,
In the description of this embodiment, the description overlapping with the description of the conventional technique will be appropriately omitted.

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element that is an embodiment of the present invention. The structure of this embodiment is the same as that of FIG. 3 except for the following points.
That is, instead of the p ⁺ -type drain / collector layer 7, the n ⁺ -type drain / collector layer is formed on the surface of the drain / collector electrode 8.
10 is formed, and the drain drift layer 6 is formed on one surface of the n ^{+ type} drain / collector layer. In addition, the n ⁺ -type drain / collector layer 10 immediately below each gate electrode 2
Has a p ⁺ -type drain / collector region 70 partially formed on the other surface thereof, and the bottom of the p ⁺ -type drain / collector region is separated from the surface of the drain drift layer 6 by the distance of n ^{+ -type.} The buffer layer 100 is formed. The width La of the p ⁺ -type drain / collector region 70 is provided corresponding to the interval LG between the p-type base regions 5. And
Similar to FIG. 5, ap ^{+ type} base central region 50 is formed in the central portion of the p type base region 5. The n ^{+ type} source / emitter region 4, the p type base region 5, the p ^{+ type} base central region 50, the drain drift layer 6, and the n ^{+ type} drain / collector layer 10 are MOSFETs.
P-type base region
5, p ^{+ type} base central region 50 and drain drift layer 6, n ^{+ type} drain / collector layer 10 and p ^{+ type} drain / collector region 70
And form a pnp transistor parasitic on the MOSFET, and these two transistors form a parasitic thyristor region.

FIG. 2 is a diagram showing an equivalent circuit of the CAT element shown in FIG. In the figure, the equivalent circuit of this CAT element is the pin between the gate electrode terminal G and the drain / collector electrode terminal D / C terminal.
It is an n-channel MOSFET that parasitizes the diode D ₂ .

Next, the operation of this CAT element will be described. A p ⁺ -type drain / collector region 70 is partially formed on the other surface of the n ⁺ -type drain / collector layer 10 directly below each gate electrode 2, and on the bottom surface of this p ⁺ -type drain / collector region.
Since the n ^{+ type} buffer layer 100 is formed, the p ^{+ type} drain / collector region 70 (p ⁺ emitter of the pnp transistor)
Holes are injected into the drain drift layer 6 from within the range of the width La, and this injection is suppressed by the n ^{+ -type} buffer layer 100. For this reason, the transport efficiency of the base region of the parasitic pnp transistor is reduced, and its DC current amplification factor h _FE is significantly reduced as compared with the conventional CAT element. Also, the holes injected into the p ⁺ -type drain / collector region 70 flow in a small amount upward through the narrowed region X in the drain drift layer 6, reach the p ^{+ -type} base central region 50, and reach the source / emitter. Get out of the electrode. Therefore, the voltage drop V _S at R _S in the base region due to the hole current is smaller than that of the conventional CAT element. Thus, in this CAT element,
Since the DC current amplification factor h _FE of the parasitic pnp transistor is reduced and the voltage drop V _{S in} the P-type base region and the p ^{+ -type} base central region 50 of the parasitic npn transistor is reduced, the conventional CA
At the latching current level in the T element, the parasitic thyristor region will not latch. That is, conventional CAT
The current level for latching will be higher than that of the device. For this reason, the turn-off of the CAT element is facilitated and the high-speed high-frequency switching characteristic is improved. Also this CA
In the T element, since the current level for latching increases as described above, the gate control range becomes wider than that of the conventional CAT element, and the current density of the CAT element can be increased correspondingly, and the chip size can be reduced. It is possible to reduce the size and cost of the CAT element. Further, regarding the conductivity modulation of the drain drift layer 6, it is effective to generate it in the portion directly below the gate electrode 2, and the p ^{+ -type} base central region 50
The conductivity modulation immediately below is unnecessary. Therefore, the p ⁺ -type drain / collector region 70 is partially narrowed down to the region X only under the gate electrode 2 to efficiently inject holes from the p ⁺ -type drain / collector region 70 into the drain drift layer 6. By doing so, the conductivity modulation effect equivalent to that of the conventional CAT element can be obtained, and the ON voltage can be lowered. Further, in the conventional CAT element, since the p ⁺ -type drain / collector layer 7 is formed over the entire drain drift layer 6, at the time of turn-off, holes accumulated in the drain drift layer 6 at the time of turn-off are p ⁺ -type drain. It was difficult to escape because it was blocked by the / collector layer 7, but in this CAT element, holes were blocked only in a narrow area at the bottom of the p ^{+ type} drain / collector region 70, and in the n ^{+ type} drain / collector layer 10 around it. It can be easily removed, which also facilitates the turn-off operation of the CAT element and improves the high-speed and high-frequency switching characteristics.

In the above embodiments, the n-type CAT element is shown, but it goes without saying that the present invention is also applicable to a p-type CAT element in which the conductivity type of each layer and each region is reversed.

[Effect of the Invention] As described above, according to the present invention, the substrate is provided with the second-conductivity-type semiconductor regions of high impurity concentration which are arranged in an island shape, and the width of the bottom surface of the second-conductivity-type semiconductor region is small. , A MOSFET corresponding to a distance between two base regions arranged on opposite gate electrodes via an insulating film, and having a bottom surface close to the first main surface of the first conductivity type semiconductor layer. It is possible to obtain a semiconductor device capable of expanding the gate control range by increasing the latching current level in the thyristor region parasitic on the.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element that is an embodiment of the present invention. Figure 2 shows
It is a figure which shows the equivalent circuit of the CAT element of FIG. FIG. 3 is a cross-sectional view showing the structure of a conventional CAT element configured monolithically. FIG. 4 is a diagram showing an equivalent circuit of a conventional CAT element. FIG. 5 is a cross-sectional view showing the structure of another conventional CAT element configured monolithically. In the figure, 1 is a source / emitter electrode, 2 is a gate electrode, 3 is an oxide film, 4 is an n ^{+ type} source / emitter region, 5 is a p type base region, 50 is a p ^{+ type} base central region, and 6 is a drain drift. A layer, 70 is a p ^{+ type} drain / collector region, 8 is a drain / collector electrode, 10 is an n ^{+ type} drain / collector layer, and 100 is an n ^{+ type} buffer layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first-conductivity-type semiconductor substrate having a first main surface and a second main surface, which serves as a drain layer and has a high impurity concentration, and a first-main surface of the first-conductivity-type semiconductor substrate. A first conductivity type semiconductor layer having a low impurity concentration and serving as a drain layer, the first conductivity type semiconductor layer having a first major surface in contact with the first major surface and a second major surface facing the first major surface. A base region made of at least two second conductivity type semiconductors having an exposed surface in a predetermined region of the second main surface and formed in an island shape, and an exposed surface in a predetermined region of each base region. A source region made of a high-concentration first conductivity type semiconductor arranged in an island shape, a drain region having an exposed surface on the second main surface of the first conductivity type semiconductor layer, and the drain region The base region and the source region are opposed to each other and are sequentially adjacent to each other. Therefore, the gate electrode is disposed on the exposed surface of these regions via the insulating film, the exposed surface is on the second main surface of the substrate, and the bottom surface is in the substrate. The bottom surface faces the gate electrode. And the width of the bottom surface is arranged in the shape of an island, and the width of the bottom surface corresponds to the distance between the two base regions arranged on the opposing gate electrodes via the insulating film. A second conductivity type semiconductor region having a high impurity concentration, which is adjacent to the first main surface of the semiconductor layer and is connected to the same potential as the drain layer of the substrate.