JPS62109365A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which hardly causes a phenomenon for losing control capacity such as a latching phenomenon, commutation failure and contains an antiparallel diodes on the same chip by composing an insulated gated type transistor of two N<-> type and P<+> type layers under a gate electrode and three P-type, N<-> type and P<+> type layers. CONSTITUTION:A collector layer 2 is not formed on the entire lower surface of a base layer 1, but formed only under a gate electrode 6, and an N<+> type layer 9 for shortcircuiting is provided as the other. The size of the layer 2 is so decided that electrons flow to the layer 2 through an inverting layer in a well layer 3 from an emitter electrode 7 by applying a voltage to a gate terminal G and implantation of holes occurs in the layer 1 from the layer 2 as a collector layer by a potential generated by a resistance by the layers 1, 9 with the current within a predetermined current. That is, functions as the control and circulation of a main current can be sufficiently satisfied without loss of control capacity due to commutation failure by at least 3 layer structure perpendicularly toward a collector C from an emitter E.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a semiconductor device having a built-in diode connected antiparallel to an insulated gate transistor on the same chip.

[Prior art and its problems]

Insulated gate transistors (IGTs) or conductivity modulation MOs have recently become popular as high-frequency semiconductor devices with low on-resistance.
A semiconductor device called 3FET has been announced. Second
The figure shows an N-channel structure of such an insulated gate transistor, with a collector layer P'i2 on the lower surface of the N-type silicon substrate l, and an N-type transistor surrounded by a P well 113 on the upper surface.
An emitter layer 4 is formed, and a gate electrode 6 is provided on the exposed upper surface of the original N base layer 1 of the substrate 1 via an insulator [5]. Emitter electrode 7 is connected to emitter 114 and P well IN! 3, collector electric bridge 8 is collector 1m
It is in contact with 52. This structure is as shown in Fig. 3, in which a P
'li2 is formed, and when a voltage is applied between the gate terminal G and the emitter terminal E so that the gate becomes positive,
An inversion layer is formed in the P-well layer 3 directly under the gate electrode, and at the same time electrons flow from the emitter layer 4 to the base N-layer 1, a positive charge is injected from the collector P-layer 2, conductivity modulation occurs in the N-layer, and the on-state is turned on. The resistance is lower than that of DMO3FET, and power loss can be reduced. FIG. 4 shows a circuit for operating a DC motor 11 with a regenerative brake, in which case a switch element 13. In order to absorb the energy accumulated in the motor 11, it is necessary to connect a freewheeling diode 16 in antiparallel to the switch element 14, which is connected in parallel to the motor. When rotating the motor 11, the element 13 is turned on and the current is turned on by the gate pulse modulation signal to operate the motor, but at this time the element 14 is turned off and the diode 16 (used as a freewheeling diode) is used for regeneration. In the braking state, the element 13 is turned off and the element 14 is turned off, and when the element 4 is turned off, the motor current returns to the DC power supply through the diode 15. In this way, the switching elements 13 and 14 are connected with diodes in antiparallel. In the DMO3FET shown in Figure 3, the source
PN is formed by the P layer on the (S) side and the N layer on the drain (D) side.
When using the IGT shown in FIG. 2, which has a built-in diode of "N" in the same hub, as the switch element 13, 14, there is a drawback that an external diode is required.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which an anti-parallel diode is built into the same chip without losing IGT performance.

[Key points of the invention]

According to the present invention, the base layer of the first conductivity type has an emitter layer of the first conductivity type surrounded by the well layer of the second conductivity type on a part of one side of the base layer, and the well layer on the outside of the emitter layer. A gate electrode is provided on the exposed portion of the well layer to the one surface via an insulating film, and on the side of the gate electrode, the emitter layer and the exposed portion of the well layer inside the emitter layer to the one surface are commonly connected to the emitter electrode. A shorting layer of a first conductivity type is in contact with the base layer, and the other side of the base layer is located in a region including immediately below the emitter layer, and a second conductivity type shorting layer is located below a portion of the base layer exposed to the first surface outside the well layer. It is covered by a conductive collector layer, both of which are in common contact with a collector electrode. As a result, anti-parallel diodes are formed by the first conductivity type layer in contact with the collector electrode, the first conductivity type base layer and the second conductivity type well layer in contact with the emitter electrode, and the above-mentioned purpose is achieved. .

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case collector M2
is not formed on the entire lower surface of the base 1111, and the gate 1
N is provided only below pole 6, and N for shorting (7)
'' layer 9 is provided.The size of the collector 712 is such that when a voltage is applied to the gate terminal G, electrons flow from the emitter electrode 7 to the base layer 1 via the inversion layer in the well layer 3, and a predetermined current is generated. It is determined that holes are injected from the P' layer 2 as the collector layer to the N layer l by this current and the potential generated by the resistance due to the N layer 1.N'' short circuit 19. However, as shown in FIG.
, N-, and P layers, when a positive voltage is applied to the emitter terminal E and a negative voltage is applied to the collector terminal C, the P N N '' junction directly under the emitter layer 4 is forward biased and a current flows, for example. , works as a freewheeling diode in motor control, and if the voltage is now reversed and the collector terminal C becomes positive and the emitter terminal E becomes negative, then N
- Since the holes injected into N1 do not disappear immediately and remain for a certain period of time (lifetime), these holes are transferred to the emitter layer 4.
N″PN-P” acts as a thyristor and commutation failure occurs, which may result in loss of control by the gate. In order to prevent this phenomenon, shortening the lifetime of the minority carriers in the N layer, along with speeding up the switching time, is somewhat effective, but it is not completely effective. Countermeasures can be taken to some extent depending on dimensions and impurity level, but reapply voltage increase rate dv/it, reverse current, reverse current decrease rate di/d
The design is difficult because the commutation ability is affected by the junction temperature. In contrast, as in the present invention shown in FIG. 1, the four-layer structure of N"PN-P" is eliminated in the vertical direction from the emitter (E) to the collector (C), and the structure is reduced to at least three layers. Therefore, it is possible to provide a semiconductor device that fully satisfies the control of the main current and the function as a freewheeling diode without losing control power due to the above-mentioned commutation failure.

【Effect of the invention】

The present invention uses an insulated gate transistor as a gate! N'PN-P'' etc. are constructed by forming the very lower two-layer part of N-P' and the three-layer part of PN-P'' (or a P channel type by reversing the conductivity type from these). Since there is no four-layer structure, even if a large current flows, phenomena such as latching and loss of control ability such as commutation failure are unlikely to occur.
The main current can be controlled by the gate signal in the same way as in the conventional ICOT. Furthermore, since the emitter is built in a two-layer diode under the rod as a freewheeling diode, when used for motor control, there is no need to externally attach a freewheeling diode, making the circuit extremely simple and economical. It is also effective for bending.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the main part of an embodiment of the present invention, Fig. 2 is a sectional view of the main part of a conventional IGT, Fig. 3 is a sectional view of the main part of a DM○5FET, and Fig. 4 is a control of a DC motor. The circuit diagram and FIG. 5 are sectional views of main parts of another configuration for explaining the present invention in detail.

Claims (1)

[Claims] 1) having a first conductivity type emitter layer surrounded by a second conductivity type well layer on a part of one side of the first conductivity type base layer;
A gate electrode is provided via an insulating film on the exposed portion of the well layer on the one surface outside the emitter layer, and a gate electrode is provided on the side of the gate electrode on the emitter layer and on the one surface of the well layer inside the emitter layer. The exposed portion of the base layer is in common contact with the emitter electrode, and the other side of the base layer is a shorting layer of the first conductivity type located in a region including immediately below the emitter layer, and a short circuit layer of the first conductivity type located in a region including immediately below the emitter layer, and a well layer that is connected to the one surface of the base layer outside the well layer. A semiconductor device characterized in that the exposed portion is covered with a collector layer of a second conductivity type located below the exposed portion, and both layers are in common contact with a collector electrode.