JPS637471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a zero-cross optical thyristor that is turned on only at or near a zero-cross.

Zero-cross optical triax, which is a type of thyristor, is manufactured by Nikkei Electronics, for example.
Published in the December 10, 1979 issue. As shown in FIG. 1, this known zero-cross optical triax consists of N-type semiconductor regions N ₁ to _{N 9} , P-type semiconductor regions P ₁ to _{P 6} , and gates G ₁ and G ₂ of MOS FETs. ,
resistance regions R ₁ , R ₂ and first and second electrodes MT ₁ ,
MT ₂ , and is configured to have the equivalent circuit shown in FIG. Note that the transistor _Q1 in Fig. 2 is composed of _N1 , P1, and N2, and the transistor Q1 is composed of N1, _P1, and _N2 .
Q ₂ consists of N ₃ , P ₂ and N ₂ , and transistor Q ₃
is composed of P ₆ , N ₂ and P ₁ , and transistor Q ₄ is
Q5, which is an enhancement type insulated gate field effect transistor ₍ FET) consisting of P ₃ , N ₂ , and P ₂ , is composed of N ₇ , P ₅ , N ₈ , and G ₂ , and FET Q ₆
is composed of N ₅ , P ₄ , N ₆ and G ₁ .

Even if light is incident on this zero-cross optical triax at a high amplitude point of the AC sinusoidal voltage,
The triac does not turn on immediately, but turns on when the voltage becomes low, that is, near the zero cross. That is, when the voltage is high, FETQ ₆ is turned on, and even if a photoexcitation current is caused to flow through light irradiation, P ₁ −N ₆ −N ₅ −
It flows along the path of MT ₁ and it is impossible to turn it on. In this way, if conduction is prevented at points other than the zero cross of the AC waveform, the noise generated during switching can be significantly reduced. However, the zero-cross optical triac shown in FIG. 1 has a disadvantage in that the structure is complicated because the zero-cross control circuit, which has hitherto been constructed as an external circuit, is integrated into the triac.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an optical thyristor having a simple configuration and a zero-crossing function.

To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments for easy understanding.
a second semiconductor region 2 of a second conductivity type adjacent to the first semiconductor region 1; and a third semiconductor region 3 of a first conductivity type adjacent to the second semiconductor region 2.
a fourth semiconductor region 4 of the second conductivity type adjacent to the third semiconductor region 3; and a fourth semiconductor region 4 of the first conductivity type surrounded by the second semiconductor region 2 with a portion exposed on the surface. and at least the second semiconductor region such that a channel of an enhancement type insulated gate field effect transistor is formed between the first semiconductor region 1 and the fifth semiconductor region 5. an insulating layer 12 provided on the surface portion 2a of 2; and a gate electrode 1 of the field effect transistor provided on the insulating layer 12.
3, and a first connection portion 1 for electrically connecting the gate electrode 13 to the third semiconductor region 3.
4, and a second connection portion 16 that electrically connects the fifth semiconductor region 5 to the second semiconductor region 2.
, a first electrode 10 connected to the first semiconductor region 1, a second electrode 11 connected to the fourth semiconductor region 4, and a light-receiving surface 8 for optical driving. This invention relates to a single or bidirectional optical thyristor having a zero-crossing function.

According to the present invention, the fifth semiconductor region 5 is provided in the second semiconductor region 2, the MOS/FET is formed between the first semiconductor region 1 and the fifth semiconductor region 5, and the fifth semiconductor region 5 is provided in the second semiconductor region 2. By simply electrically connecting the semiconductor region 5 of No. 5 and the second semiconductor region 2, a function of turning on near the zero cross is generated, making it possible to greatly simplify the configuration.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a partially cutaway perspective view illustrating a zero-cross optical thyristor according to an embodiment of the present invention. This optical thyristor, like a general electrically controlled thyristor, is of the first conductivity type (in this example, N
a first semiconductor region 1 of a second conductivity type (in this embodiment, a P type), a second semiconductor region 2 of a second conductivity type (P type in this embodiment), a third semiconductor region 3 of an N type, and a fourth semiconductor region of a P type. It has a four-layer structure consisting of a region 4, and further includes an N-type fifth semiconductor region 5 surrounded by the second semiconductor region 2 and arranged so as to surround the first semiconductor region 1 in a ring shape. have Note that the first semiconductor region 1 is a portion that functions as an N-type emitter region of the first transistor when a thyristor is represented by an equivalent circuit consisting of two transistors, and is a region with an average impurity concentration of approximately 10 ²⁰ /cm ^{3 .} It is. The second semiconductor region 2 serves as a P-type base region of the first transistor of the equivalent circuit, and has an average impurity concentration of about 5×10 ¹⁶ /cm ³ . The second semiconductor region 3 serves as an N-type base region of the second transistor of the equivalent circuit, and has an average impurity concentration of about 1×10 ¹⁴ /cm ³ . The fourth semiconductor region 4 serves as a P-type emitter region of the second transistor of the equivalent circuit, and has an average impurity concentration of about 5×10 ¹⁹ /cm ³ . The fifth semiconductor region 5 constitutes a newly provided MOS FET and is also used for electrical connection with the second semiconductor region 2, and has an average impurity concentration of about 10 ²⁰ /
with cm ³ . Further, the first, second, and fifth semiconductor regions 1, 2, and 5 are formed in a planar shape, and a portion of each is exposed on a main surface 9 provided with a light-receiving surface 8 that receives light 7.

10 is a cathode as a first electrode connected to the first semiconductor region 1, and 11 is an anode as a second electrode connected to the fourth semiconductor region 4. 12 is SiO ₂ + that constitutes a MOS type FET
It is an insulating layer made of Si ₃ N ₄ . 13 consists of Al
This is the gate electrode of the FET. The surface portion 2a of the P-type second semiconductor region 2 exposed at the surface between the N ⁺ -type first semiconductor region 1 and the N ⁺ -type fifth semiconductor region 5 is doped with a low impurity concentration by ion implantation. This is the N-channel forming region.

Enhancement type N channel consisting of surface portion 2a, insulating layer 12 and gate electrode 13
The first connecting portion 14 for connecting the gate electrode 13 of the MOS/FET to the third semiconductor region 3 is connected to the N ⁺ type connecting semiconductor region 3a formed in the third semiconductor region 3 and the wiring. It consists of a conductor 15. The second connection portion 16 for electrically connecting the fifth semiconductor region 5 and the second semiconductor region 2 is located on the outer peripheral side of the fifth semiconductor region 5 and the second semiconductor region 2.
It is formed by shorting a PN junction with a metal layer.

FIG. 4 schematically shows the arrangement of each semiconductor region on the main surface 9. As shown in FIG. As is clear from this figure, in an actual thyristor, a large number of micro thyristors, half of which are shown in FIG. It is composed of:

Next, the operation of this optical thyristor will be explained. now,
A sinusoidal AC voltage is applied between the cathode 10 and the anode 11, and the cathode 10 is negative,
At the time when the anode 11 has a positive polarity and a high sinusoidal voltage is applied, that is, at a time when a voltage other than near zero cross, for example, 6 volts or more is applied, the light 7 is projected onto the light receiving surface 8. However, this thyristor does not turn on. To explain this in detail, when the anode-cathode voltage V _AK becomes 6 volts or more, the 6 volt voltage of the anode 11 is applied to the anode 11, the fourth semiconductor region 4, the third semiconductor region 3, and the N ⁺ type semiconductor region. 3a, wiring conductor 1
5 and the gate electrode 13, and the potential of the second semiconductor region 2 is approximately equal to the potential of the cathode 10 because the N ⁺ P junction is in a forward bias state. Eventually, the potential difference between the gate electrode 13 and the second semiconductor region 2 becomes a voltage close to the cathode-anode voltage _VAK , and when this potential difference becomes about 5 volts or more, an N channel is formed in the surface portion 2a. Therefore, when the amplitude of the sinusoidal AC voltage is about 6 volts or more, the first semiconductor region 1 and the fifth semiconductor region 5 are electrically connected, and as a result, the P-type base second semiconductor region 2. An electrical circuit consisting of a second connecting portion 16 which is a shorting electrode, a fifth N ⁺ type semiconductor region 5, an N channel in the surface portion 2a, a first N ⁺ type semiconductor region 1, and a cathode 10. A circuit is formed. For this reason, irradiation with light 7 generates hole-electron pairs, resulting in a reverse bias state.
If we try to turn on the PN ^-junction , the photoexcited current will flow in the electrical circuit through the above channel, making it impossible to turn on.

However, when the irradiation of light 7 is continued and the AC voltage crosses the zero volt line in the next cycle of the AC voltage, the voltage between the anode and cathode approaches zero.
Since V _AK is 6 volts or less and the potential difference between the gate electrode 13 and the second semiconductor region 2 is also 5 volts or less, no N channel is formed in the surface portion 2a. Therefore, the photoexcitation current generated by irradiation with light 7 is effectively used to turn on the PN ^- junction, and the thyristor is immediately turned on. Once the thyristor is turned on, even if the amplitude of the AC voltage increases, the anode-cathode voltage V _AK remains low, so no MOS/FET channel is formed.

As is clear from the above, this embodiment provides the following advantages.

(a) A MOS type FET is formed between the first semiconductor region 1 and the fifth semiconductor region 5, and an N ⁺ type fifth semiconductor region 5 is formed.
The semiconductor region 5 and the P-type second semiconductor region 2 are connected by a second connection portion 16 having a short-circuit electrode structure, and the gate electrode 13 is connected to the first connection portion 14.
By simply connecting it to the third semiconductor region 3 at , it is possible to obtain an on function near the zero cross. Therefore, it becomes possible to significantly simplify the configuration of the zero-crossing optical thyristor.

(b) A fifth semiconductor region 5 is formed so as to surround the first semiconductor region 1, and a fifth semiconductor region 5 is formed between these regions.
Since a MOS/FET is provided, the effective channel width of the FET becomes larger and the on-resistance of the MOS/FET becomes lower. Therefore, a rapidly rising forward voltage is applied between the anode and cathode, causing a displacement current that tries to turn on the dv/dt.
Even if a malfunction occurs due to the effect,
MOS/FET circuits are more effective at absorbing displacement currents, increasing dv/dt withstand capability.

(c) As shown in Figure 4, since the structure is a combination of many micro thyristors, the P-type base of each micro thyristor, that is, the second semiconductor region 2,
Even though the dv/dt effect causes a displacement current to flow laterally towards the second connection part 16 of the short-circuit electrode structure, the voltage drop due to the lateral resistance of the P-type base is very small due to the short lateral distance. becomes smaller,
Malfunctions are prevented due to the DV/DT effect.

(d) As shown in FIG. 4, the combination of micro thyristors makes it possible to turn on almost all of the PN ^- junctions at the same time. Further, since the second connection portions 16 of each thyristor are connected to each other, even if the light irradiation is uneven on the main surface 9, the second semiconductor region 2 of each thyristor has the same potential. The entire surface of the element is fired almost simultaneously. Therefore, di/dt tolerance can be increased.

Next, FIG. 5, which shows a zero-crossing optical thyristor according to another embodiment of the present invention, will be described. However, since the parts indicated by numerals 1 to 5 and 7 to 16 in Fig. 5 are substantially the same as the parts indicated by the same numerals in Fig. 3,
The explanation will be omitted. In this example, the
A P-type connection semiconductor region 6 is provided in place of the N ⁺ -type semiconductor region 3a. The shortest distance between the P-type second semiconductor region 2 and the semiconductor region 6 is determined by the distance between the second semiconductor region 2 and the semiconductor region 6 when the voltage applied between the anode 11 and the cathode 10 reaches a predetermined value.
The value is set to, for example, 20 μm so that the space between the semiconductor region 6 and the sixth semiconductor region 6 is filled with a space charge layer (depletion layer). With this configuration, when the anode-cathode voltage V _AK reaches approximately 20 volts during the period when the thyristor is blocked from turning on by the MOS/FET, the depletion layer extending from the PN ^- junction will reach region 6. Even if V _AK increases further, the potential difference between region 2 and gate electrode 13 increases slowly. Therefore, it is possible to prevent the MOS/FET from being destroyed during the thyristor-on blocking period.

FIG. 6 explains the effect of the P-type semiconductor region 6. Now, if we apply 0 volts to the anode 11 and a negative voltage V _K to the cathode 10 to increase the voltage between the anode and cathode, the potential V _A of the second semiconductor region 2 will almost follow the change in the cathode voltage V _K. Change. In addition, the surface potential of the P-type semiconductor region 6
When the gap between regions 2 and 6 is filled with a depletion layer, V _B, that is, the potential of the gate electrode 13, acts like a guard ring effect and becomes a state where the cathode voltage V _K is divided at a constant ratio. , changes as shown by V _B in FIG. This makes the difference between V _A and V _B
V _AB remains approximately constant, and by increasing V _AK
MOS/FET will not be destroyed, MOS/FET will be
V _AK will not be destroyed even if it reaches 1000 volts. In addition,
The parts other than the area 6 of the optical thyristor in FIG.
Since the structure is similar to that shown in FIG. 4 and FIG. 4, it has the same advantages as the previous embodiment.

Next, FIG. 7 showing still another embodiment of the present invention will be described. However, since the parts indicated by reference numerals 1 to 16 have the same configuration as the parts indicated by the same reference numerals in FIGS. 3 and 5, the explanation thereof will be omitted. This embodiment is an application of the present invention to a bidirectionally controllable zero-crossing optical thyristor or triax. Therefore, the first thyristor portion on the left half and the second thyristor portion on the right half, which are separated by a chain line, are connected in antiparallel. In the case of this triax as well, the same effects as those of a unidirectionally controlled thyristor can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto and can be further modified. For example, it is also applicable to a thyristor with a completely planar structure. Also, connection part 1
Although 4 is shown as a wire for explanatory purposes, it is of course possible to use a cross wiring or the like. Further, a photodiode or the like may be integrated to provide the light 7.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional zero-cross optical triax, FIG. 2 is an equivalent circuit diagram of the triax shown in FIG. 1, and FIG. 4 is a plan view showing a large number of semiconductor regions on the main surface of the thyristor shown in FIG. 3; FIG. 5 is a diagram showing a zero-cross light according to another embodiment of the present invention. FIG. 6 is a characteristic diagram of the thyristor shown in FIG. 5, and FIG. 7 is a sectional view showing a zero-cross optical thyristor according to still another embodiment of the present invention. In the symbols used in the drawings, 1 is the first semiconductor region, 2 is the second semiconductor region, 2a
is a surface portion, 3 is a third semiconductor region, 4 is a fourth semiconductor region, 5 is a fifth semiconductor region, 6 is a connecting semiconductor region, 7 is light, 8 is a light-receiving surface, 9 is a main surface,
10 is a first electrode (cathode), 11 is a second electrode (anode), 12 is an insulating layer, 13 is a gate electrode, 14 is a first connection part, 15 is a wiring conductor, 1
6 is the second connection part.

Claims (1)

[Claims] 1: a first semiconductor region 1 of a first conductivity type; a second semiconductor region 2 of a second conductivity type adjacent to the first semiconductor region 1; and the second semiconductor region 2. a third semiconductor region 3 of the first conductivity type adjacent to the third semiconductor region 3; a fourth semiconductor region 4 of the second conductivity type adjacent to the third semiconductor region 3; a fifth semiconductor region 5 of the first conductivity type surrounded by the second semiconductor region 2; and an enhancement type insulated gate field effect transistor between the first semiconductor region 1 and the fifth semiconductor region 5; an insulating layer 12 provided on at least the surface portion 2a of the second semiconductor region 2 so that a channel is formed; a gate electrode 13 of the field effect transistor provided on the insulating layer 12; The gate electrode 13 is connected to the third semiconductor region 3.
a first connecting part 14 for electrically connecting to
a second connection portion 16 that electrically connects the fifth semiconductor region 5 to the second semiconductor region 2; a first electrode 10 connected to the first semiconductor region 1; A single or bidirectional optical thyristor with a zero-cross function, comprising: a second electrode 11 connected to a fourth semiconductor region 4; and a light-receiving surface 8 for optical driving. 2. The first connection portion 14 connects the second conductivity type connection semiconductor region 6 provided so as to be surrounded by the third semiconductor region 3, the gate electrode 13, and the connection semiconductor region 6. The optical thyristor according to claim 1, which comprises a wiring conductor 15. 3. The fifth semiconductor region 5 is arranged so as to be exposed on the surface of the side where the first semiconductor region 1 is exposed, and is formed so as to surround the first semiconductor region 1 in a ring shape. An optical thyristor according to claim 1 or 2.