JPS6035571A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the titled device of combination of an element having P-N junction stably actig with an insulation gate FFT by a method wherein this device is so constructed that the voltage impressed on a gate electrode is controlled by a depletion layer generating at a narrow part when a reverse voltage is impressed between the first semiconductor region and the second one. CONSTITUTION:When a positive voltage is impressed on the anode 8 of a thyristor, and a negative one on the cathode 7, the gate voltage is impressed through the route of the anode 8, forth semiconductor region 4, first semiconductor region 1, narrow part 1a, a connecting semiconductor region 16, a joining electrode 13, a connection conductor 14, and the gate electrode 12, a channel being formed in the surface part 2a, and ON at the part other than the zero-cross of the thyristor being then blocked. Besides, the narrow part 1a impressed with a high anode-gate voltage is filled with the depletion layer, and accordingly the increase of the voltage impressed on the gate electrode 12 is restricted. In other words, the depletion layer shares in the increment of voltage, resulting in the restriction of the increase of voltage in which an insulation film 11 under the electrode 12 shares. Thereby, the breakdown of the insulation film 11 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an insulated gate field effect transistor (FET)
The present invention relates to semiconductor devices such as zero-cross optical thyristors.

Prior Art The applicant of this application has filed Japanese Patent Application No. 56-203586 (Japanese Unexamined Patent Publication No. 58
-105572), we proposed a zero-cross optical thyristor with a structure that prevented the breakdown of the FET insulating film. As shown in FIG. 1, this zero-cross optical zyristor tz has a first semiconductor region +1 of one conductivity type (N- type in this embodiment).
1, a second semiconductor region (2) of the other conductivity type (P type in this example), and a third semiconductor region (31) of N type.
It has a four-layer structure consisting of a P-type fourth semiconductor region (4), and is further surrounded by the second semiconductor region t2+ and arranged so as to surround the third semiconductor region (3) in a ring shape. The third semiconductor region (3) is shown as an equivalent circuit consisting of two thyristor transistors. The second semiconductor region +21 acts as the N-type emitter region of the first transistor in the case, and the second semiconductor region +21 acts as the P-type base region of the I transistor of il in the above equivalent circuit. The semiconductor region (11 is a part that works as the NW base 1m region of the second transistor in the above equivalent circuit, and the fourth semiconductor region +41 is a part that works as a 1) type emitter chain acid of the second transistor in the above equivalent circuit. and the fifth semiconductor region (51 is a MOS type F
This is the kth region that constitutes the ET and is also used for electrical connection with the second semiconductor region +21, and is the gate connection region of the sixth semiconductor region (61k FET.This zero-cross optical thyristor is Similar to a general original thyristor, the third semiconductor region +31 has a cathode (
7), and a 20' FI7 in the fourth semiconductor region (4).
It has 7 nodes (81Y) as the L pole, and the IC is configured to project light (91 points (IOIK) as the gate signal. Also, there is a MOS for zero cross-mi! function.
- 5j02 + 5jBN formed by FET.

A gate insulating film (+11 is provided on the second semiconductor region +21 between at least the third semiconductor region (3) and the fifth semiconductor region (51), and this gate insulating film)
Gate electrode made of upper AI [121f) - P-type sixth
A conductor (141) is connected to the electrode U' on the semiconductor region +61 of the semiconductor region +61.

Also, in order to form a bypass circuit for gate No. 18,
The second semiconductor region (21) and the comb end portion of the fifth semiconductor region (51) are connected to each other by a shorting electrode u51.

Additionally, a channel forming surface portion (2aJ) of the P-type second semiconductor region (21) exposed on the surface between the N-type third semiconductor region is said to have a low impurity concentration through ion implantation.

By the way, if this zero-cross optical thyristor is made of PET
If L-1 is not provided, the first semiconductor region I
When light (1×) is projected onto the PN junction between II and the second semiconductor region (21), the thyristor changes to the on-state VC. ) and the anode I) 11 substantially independently of the voltage value, ie independently of the zero crossing of the alternating voltage.

However, in reality, 4
Since OS-F F and T are provided, AC i
a; IE (At the D zero cross, the sirisk does not turn on. Next, this will be explained in detail. Now, a sine wave AC voltage is applied between the cathode (71) and the 7 node t8+, and the cathode (7) is negative, 7 nodes (8)
Which polarity is positive? with a sinusoidal high voltage (e.g. 6V
At the moment when 1tZEE) is applied, light (9)
Even if the thyristor is projected, this thyristor will not turn on. When the anode-cathode voltage VAK becomes 6 volts or more, the voltage of 6 volts at the 7th node (81
8j, fourth semiconductor region (4j, first semiconductor region +1
1. A path consisting of the sixth semiconductor region (6), the conductor I, and the gate electrode is applied to the gate 'Kametoshi' (in order), and the potential of the second semiconductor region +21 is such that the NP junction is in a forward bias state. Therefore, the potential of the cathode (7) becomes almost equal to that of the cathode (7), and as a result, the potential of the gate electrode (lz and the second semiconductor region 1
The voltage difference between the 7 node and the cathode is vA.
When the voltage becomes close to K, and this potential difference becomes about 5 volts or more, an N channel is formed on the surface portion (2aJ. Therefore, the amplitude of the sinusoidal AC voltage is about 6 volts).In the case of J2J, the third semiconductor The region +31 and the fifth semi-iL body region (51 are connected to the tb, Okiichi VC, and eventually the Pm-based second semiconductor region (2;, the fifth semi-iL body region (51) region (51% surface area (2a) of the hemi-type channel, N-type third semiconductor region (3).

and cathode [71.

For this reason, even if a hole-electron pair is generated by irradiation with light (91) and an attempt is made to turn on one junction to P in a reverse bias state, the photo-excited current flows in the electrical circuit passing through the above channel and ends up turning on. It is impossible to do 5J.

On the other hand, the light (9) continues to emit light, and when the AC voltage crosses the zero volt line at the second cycle of the AC voltage and reaches the point near zero crossing, the dragon pressure VAK between the 7th node and the cathode becomes below 6 volts V. , gate-Ht, ft3. The m-potential difference between +121 and the second semiconductor region (21 is also less than 5 volts, and no N channel is formed in the surface portion (2a). The photo-excited current is effectively used to turn on the PN-junction, and the thyristor turns on immediately. Once the thyristor is turned on, even if the amplitude of the alternating voltage becomes high, the 7-node cathode width Since the pressure VA is kept low, the MOS
- No FET channel is formed.

In the device shown in FIG. 1, the distance between the sixth semiconductor region (6) and the second semiconductor region (21) is further set small, and when a high voltage is applied to the 7-node cathode curve, the depletion layer is formed. It is set to 5 to fill up.For this reason, 7 nodes
Cathode tune 11IH: Following the increase in vAK, the increase in voltage applied to the gate electrode U force is restricted, and destruction of the insulating film (111) is prevented. It was found that the zero-crossing operation may not occur.The reason for this is that when the voltage applied to the 7-node cathode curve is turned on and off, the FCN type first semiconductor region (Moon and Pm sixth semiconductor region t61 This is presumed to be due to the movement of carriers through the PN fin formed between the two.

In addition to the above-mentioned gap M, the cellocross optical thyristor of FIG. 1 has a second semiconductor region (21 and 6
In order to fill the gap with the semiconductor region (61), it is necessary to bring both regions close to each other, and the precision of the mask pattern must be increased, which is 5t+4J'tjD.

I just mentioned the zero-cross optical thyristor.

A thyristor with a gate electrode or its (tlJ P
A similar problem exists in a device combining an N-junction element and MOS-F E'I'.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a device having a stable cut-out junction to a jP and an insulated gate FET are combined.

Structure of the Invention To achieve the above object, the present invention is easy to understand.
3-1G (see reference numerals in drawings) 1G, one first semiconductor region il of η1□ type
+, and is provided in the first semiconductor region tl+ of AiJ so that a narrow portion (1a) reaching the surface of the semiconductor substrate is formed in the first semiconductor region +i+, and is wider than the first semiconductor region il+. A single unit that is set to a high impurity Q degree
Alternatively, the plurality of second semiconductor regions +21, the four linking poles (131) fully connected to the narrow width portion (1a), and the gate' electrode f1 connected to the linking electrode +131
Including three insulated gate field effect transistors,
and the first semiconductor region ti+ and njlN (2 second
When a reverse voltage is applied between the semiconductor region (21) of i
The voltage applied to the iJ gate electrode σ is the narrow part +1
It is limited by the depletion layer that occurs in aJ. The present invention relates to a device that is characterized by the fact that it has an angle of τ.

Effects of the Invention According to the above invention, the first semiconductor region 11+ and the gate'
Since the electrode U is connected to the electrode U without making a PN junction, and it is connected through the narrow part (1a)'g of the first semiconductor region (11), the first semiconductor region (11 and the second Semiconductor area+
The FET can be controlled with a stable relationship to the reverse voltage applied to the PN junction with 21.

Embodiment Next, referring to FIGS. 2 to 5, a zero-cross optical thyristor according to an embodiment of the present invention will be described.

However, in FIGS. 2 and 3, the parts indicated by the symbols (L to (51, and (7) to 115) have substantially the same structure as the parts indicated by the same symbols in FIG. 1. , operate substantially the same, so the explanation thereof will be omitted.

The zero-cross optical thyristor of this embodiment does not include a portion corresponding to the sixth semiconductor region t6+ shown in FIG. A narrow portion (including 1aJ) of the i-type first semiconductor region +1+ provided in the exposed portion 5. In this narrow portion (1a), a connecting N-type semiconductor region 1 is provided.
The linking electrode 031 is also connected via 161.

The planar pattern of each semiconductor region is as shown in FIG. In other words, the thyristor! + (the first part of the hemlock that becomes the body part)
A P-type second semiconductor region (2) is formed in the form of an island in the semiconductor region il+, and a third N-type semiconductor region (X3) is formed in the form of an island in the second semiconductor region +21. Completely formed,
A fifth semiconductor region (5
) is formed as a source in the semi-2y body region of 1Φjr < 143 so as to surround 31 in a ring shape, and the second half-4 body region of type ■】 (21 is the ly<narrow part (IR) of the radius d).
'l;ll;l It is shaped like a commercial opportunity.

The gate electrode (121) and the contact electrode (151 are the third
It is formed into a ring shape according to the pattern shown in the figure.

To illustrate the degree of impurity in each region made of silicon, the first semiconductor region of N1y (the impurity concentration of 11 is about I x 10"7 cm", the second semiconductor region of P type (210 Sono degree is approx. 5 x I O"7cm"
, the third semiconductor region (3; and the connection semiconductor region ab+
The surface impurity concentration of the fourth semiconductor region 14+ is approximately I x 107cm, and the average impurity concentration of the fourth semiconductor region 14+ is approximately 5 x 10''/
am". Again.

The depth of diffusion in the second semiconductor region +21 is approximately 20 μm.

FIG. 4 shows l1va d in the narrow portion (1a) and the gate voltage V of the FET. Figure 5 shows the relationship between the width d and the maximum electric field strength EMAX in the narrow part (1aJ '7)7.
show. The characteristic line in Figure 4 (Al) and the 11 gonads in Figure 5 (
at indicates the case where the connection semiconductor region surrounding (diffusion mask width is 10 μm and the diffusion depth is 5 μm), and the characteristic line (I3) in FIG. 4 and the characteristic line in FIG. 5 (bl is the diffusion mask width lOμm). This shows the case where the depth of diffusion is reduced to 1O/7m.

This data is obtained when the pressure between the 7 nodes and the cathode is set to 1000 V, and the impurity concentration in each region is set to the values described above. As is clear from FIG. 4, if the width d of the narrow portion (1aJ) is reduced by 8 times, the gate voltage V.χ can be lowered accordingly. However, if the width d is made extremely small,
The maximum electric field strength EMAX largely depends on 1. Therefore, 1 width d
You can't make it small at the end of the day.

When a positive voltage is applied to the anode (8) of the thyristor configured as described above and a negative voltage is applied to the cathode +71, 7 nodes (8j, semiconductor region of block 4 (41, first semiconductor region)
1), narrow portion (1a), connection semiconductor region (1b1,
For coordination @ pole t131. Connection exclusive 041. Gate electrode f1
Gate voltage is applied through path 21. This 5 surface area (2a)
A channel is formed in the thyristor zero cross J2
J Outside Te's on is prevented. Further, the narrow portion 11aJ to which the sieving anode-to-gate voltage is applied is filled with a depletion layer.

The increase in voltage applied to the gate electrode U is limited.

In other words, the increase in voltage is shared by the depletion layer, and the gate electrode (I2
The rise of the insulating film (+11) under the insulating film 1-i'1LIE is limited. Therefore, destruction of the insulating film αυ is prevented.

In this example, the first semiconductor region (the moon and the gate electrode u2
Since there is no PN junction between VC and VC, the operation of turning on the thyristor at zero cross does not become unstable.

Further, since both sides of the narrow portion (]aJ are the second semiconductor regions (2) having the same potential, the depletion layer spreads from both sides.

Therefore, it is possible to fill the narrow part (1aJ7) with a depletion layer at a low voltage, making it unnecessary to make the width of the narrow part (1aJ extremely narrow), and to crystallize the mask pattern for each pattern depending on the width of the mask pattern. There's no need.

First, a zero-cross optical thyristor according to another embodiment of the present invention will be briefly described. However, in Figures 6 to 10
C. 1- Stone parts common to those in FIGS. 41 to 3 are given the same reference numerals and explanations thereof will be omitted.

In Example 1 of FIG. 6, the N-type connection semiconductor region t11
Since i+Y is not provided, the electrodes (131 are formed of low resistance Si polycrystal, and the gate electrode u21 is also formed of Si polycrystal. In this case, VC is the N-type semiconductor region 116) are used, so a low voltage is used. The narrow portion (1aJ) is filled with a depletion layer.

Figure 7 shows a +196 narrow portion (1aJy:!: modified embodiment).

In this embodiment, the narrow portion (1aJ) surrounding the F-type connecting semiconductor region (1G) is not completely surrounded by the P-type second semiconductor region +21. If the periphery of the type connection semiconductor region a(-) is filled with a depletion layer, the operation will be exactly the same as in FIGS. 2 and 3.

FIG. 8 shows an embodiment in which a plurality of second semiconductor regions f217 are provided. Second semiconductor region on the right side of P type (2h)
is discontinuous in the second semiconductor region (2) on the left side in the substrate, and is provided independently in the form of an island within the N-type semiconductor region. However, they are electrically connected by the external connection conductor (171). Therefore, the two P-type semiconductor regions 1
21 (2b) works equivalently to a continuous area, and the narrow part (
1a) can be filled with a depletion layer.

FIG. 9 shows an embodiment applied to a zero-crossing optical thyristor or triac capable of bilateral self-control (ilI+).

This triac is the first half of the left half separated by the dashed line.
The thyristor part of the thyristor part and the second thyristor part of the right half are connected in antiparallel. In the case of this triac as well, Tx, f'F-
You can get the effect of using it.

Modifications The present invention is not limited to the embodiments described above, and the following modifications are possible, for example.

As shown in the CAllO diagram, one gate electrode may be provided to supply an electrical gate signal instead of an optical gate signal.In this way, the same applies to the case where a gate signal is provided by one electrical signal. You can get the following effect.

([11 As shown in FIG. 11, P ~ consisting of an N type silk semiconductor region (1;
A narrow portion +18) is provided in the bonding element, a semiconductor region t16+ for N-type connection and an electrode u4 for linkage are provided there, and a linking electrode (13I conductor (141TM, o S -F E
It may be connected to the gate electrode uZ of T. In this FIG. 10, M
3a), a positive N-type semiconductor region (5) as a drain, and an insulating layer), and P
The P-type semiconductor region <2c) is electrically connected to the P-type semiconductor region (21).

(〇 It is also possible to provide a large number of micro-sized IJ stans on one board and connect them in parallel.

[Brief explanation of the drawing]

Is Figure 1 a conventional zero-cross optical thyristor? A cross-sectional view showing,
Figure 2 shows the zero-crossing optical thyristor according to the first implementation of the QIJ of this invention, and the cross-section σD diagram corresponding to line II-II in Figure 'i-N'3, and Figure 3 shows the zero-crossing optical thyristor in Figure 2. The plan view, Figure 4, shows the relationship between the width d of the 11@ narrow portion S and the gate voltage; Figure 6 is a sectional view showing a zero-crossing optical thyristor of another embodiment, and Figures 7 and 8 are partial diagrams of a zero-crossing optical thyristor of another embodiment. FIG. 9 is a plan view, FIG. 9 is a sectional view showing a zero-cross optical triac of another embodiment, and FIGS. 10 and 11 are sectional views showing modified semiconductor devices. +11...First semiconductor region, (1aJ...Narrow width portion, (21...W; 2nd semiconductor region, (2a)...
・Surface portion, (31... third semiconductor region, (4j・
...Fourth semiconductor region, (5)...Fifth semiconductor region, (force...cathode, (8j...anode, ul
...Insulating film, σZ°・°gate electrode, ushio...linking electrode, (1 building...connection conductor, [151...short circuit electrode, tllil...semiconductor region for N-type connection. Substitute Person Noritaka Naono d (／'m＞ Figure 5 d (μm) In the 11th total

Claims (1)

[Claims] II+ A first semiconductor region fi+ of one conductivity type. The narrow portion (1aJ) reaching the surface of the semiconductor substrate is formed in the first semiconductor region (11), and is provided in the first semiconductor region fi+ and is located in the first semiconductor region II+.
one or more second semiconductor regions +21 whose impurity concentration is set higher than that of the second semiconductor region +21, a linking EL pole u31 connected to the narrow opening a), and a linking electrode U31 connected to the narrow opening a). an insulated gate field effect transistor having a connected gate electrode (12), and when a reverse voltage is applied between the first semiconductor region (moon and the @2 semiconductor region (21) the gate electrode A semiconductor device characterized in that the voltage applied to the σ force is limited by a depletion layer generated in the narrow width portion (la) Ic. (2) The field effect transistor is formed in the second semiconductor region ( 21. The semiconductor device according to claim 1, wherein the semiconductor device is formed in the first semiconductor region (II is a base portion of the cyrisk), and the second semiconductor region (2) 3. The semiconductor device according to claim 1, wherein is a base region to which a gate No. 46 of said thyristor is supplied.