JPS6112072A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a highly integrated semiconductor device in a structure; wherein the control part and the main driving part can be insulated in a DC way in a monolithic structure, the main driving part can be controlled even when the potential thereof is in a floating state, and moreover, the control current can be lessened; by a method wherein specific first - fourth regions and specific first - fourth electrodes are respectively provided in the main surface 9 of one side of the semiconductor device. CONSTITUTION:In case the potential A2 of terminals G3 and G4 is lower than that of a terminal B2, a p channel is formed in the surface of an nB region 15 under a third electrode 33 and positive holes flow into a pB region 13 from a pE<-> region 16. As a result, an injection of electrons into the pB region 13 from an nE region 14 is promoted, the nEpBnB transistor part is turned to ON and electrons flow into the nB region 15. Accordingly, after that, an injection of positive holes into the nB region 15 from the pE<-> region 16 is promoted and the pEnBpE transistor part is turned to ON. As the collector currents of the nEpBnB transistor part and the pEnBpE transistor part mutually become the base current of the other transistor part, a positive feedback is generated, and finally, both transistor parts result in being turned to ON as a thyristor pEnBpBnE.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to an electrically coupled semiconductor device in which a control section and a main drive section are electrically insulated.

[Background of the invention]

In recent years, with the advancement of various electronics in industry, there has been an increasing need to drive large amounts of electric power with minute control signals. For this kind of needs, electrical isolation of the control part and the main drive part is necessary. A typical semiconductor device that meets this need is an optical coupling device (commonly known as a photocoupler). Among them, the optically coupled thyristor has the ability to block the forward and rainy directions. It has the advantages of ■low power loss after switching, and ■has a self-holding function, and is widely used in electronic exchange switches and solid state relays. However, it has some important problems. This will be explained in detail below, including the principle of operation.

FIG. 2 shows a typical basic circuit configuration using optically coupled thyristors.

When the switch 1 is closed, current flows through the light emitting element 2 and light is emitted. This light generates a photocurrent in the photothyristor 3, and when the photothyristor is placed in a forward bias state by the AC power source 4, it is ignited by this photocurrent. In this case, since the photothyristor and the light emitting element are electrically DC-insulated, this method has the following advantages, unlike the normal electrical coupling method. f#JS.

6.7 is a resistor, and 8 is a DC power supply.

(a) Even if a potential difference exists between the terminal B and the terminal B, control is possible, that is, ignition operation, etc. is possible.

(b) The current flowing through the light emitting element 2 does not flow into the thyristor side. Nor does the reverse occur.

On the other hand, it has a purchasing point between:

(1) Photothyristor 3 and transistor 1 are completely S
However, the light-emitting element is manufactured using an m-v group or I-VI group compound semiconductor represented by QaA8 or the like. Because of these different materials, it is necessary to use a wide IC configuration, which requires precise assembly work and increases costs. The fact that the manufacturing technology and processing technology for compound semiconductors are not as good as those for Si also contributes to higher costs.

(2) Light emitting efficiency of light emitting diode, light receiving efficiency of photothyristor 9 The efficiency of transmitting light from the light emitting diode to the photothyristor is low. For this reason, the optical coupling efficiency obtained by combining these efficiencies is small, and it is necessary to flow a large control current of about several milliamperes through the light emitting element to drive the photothyristor.

Special Publication No. Sho 42-24863, Special Publication No. Sho 53-4658
Publication No. 9 describes pnpn as a MOS gate or MOS/FE.
An example of turning on at T is disclosed. Also, Tokukai Sho 5
No. 7-196626 discloses an embodiment in which both on and off driving is performed using MO5@FET. All of these have the feature that the gate and the main switch are insulated, but if the potential of the main switch is in the 70-ting state, it cannot be turned on. In other words, it can only be turned on when the gate potential is higher or lower than the cathode potential of the main switch. Therefore, it is impossible to achieve the same functionality as a photocoupler.

[Purpose of departure]

The object of the present invention is to provide a highly integrated semiconductor that has a monolithic structure and can insulate the control section and the main drive section in terms of direct current, and also allows control even when the potential of the main drive section is in a floating state, and also allows the control current to be small. The goal is to provide equipment.

[Summary of the invention]

The semiconductor device of the present invention that achieves the above object is characterized by having a pair of main surfaces, at least a portion of which includes a first region of a first conductivity type exposed on at least one of the main surfaces; a second region of the second conductive layer formed within the first region such that a first pn junction formed between the first region and the first region terminates on the one main surface; a third region of the first conductivity type formed within the second region such that a second pn junction formed between the region terminates at the one main surface; The third formed between
a semiconductor substrate having a fourth region of a second conductive layer formed in such a way that a pn junction of the second conductor is formed so as to terminate at least on one main surface of the semiconductor body at a distance from the first pn junction; a first electrode in low resistance contact with at least a portion of the third region; a second electrode in low resistance contact with at least a portion of the third region; and a first electrode in low resistance contact with at least a portion of the third region; 2
a third region provided on at least a portion of the first region so as to extend over at least a portion of the first region and the third region;
and an electrode provided on at least a portion of the second region so as to extend over at least a portion of the first region and the third region via an insulating film on the one main surface. and a fourth electrode.

[Embodiments of the invention]

The present invention will be explained in detail below based on examples.

<Example 1> FIG. 1 is a schematic sectional view showing a first example of the present invention.

15 is a first region n! which is buried in the polycrystalline silicon 20 via the insulating film 17 in the form of an island and is exposed on one main surface 22 of the semiconductor substrate 23. l (n-type base) region,
13 is a first pn formed between the n11 region 15
n11 region 15 so that the bond terminates on one major surface 22.
I)m (I) which is the second region formed within (I) base)
The second region 14 is formed between the pII region 13 and the pII region 13.
The third region (n-type emitter) region 12 is formed within the 9m region 13 so that the pn junction of the region terminates at one main surface 22. A pz (n-type emitter) region is a fourth region formed in the n3 region 15 such that the pn junction of No. 3 terminates on one main surface 22 apart from the first pn junction. 16 is n
The fifth region 1) x- (low impurity concentration n-type emitter) region 21 is provided in the p region 12 so as to face the 9m region 13 via the B region 15, and the nB region 15 is insulated. This is a high concentration n1 region formed in a portion in contact with the film 17.

40 is an insulating film formed on one main surface 22 of semiconductor substrate 23, 31 is a first electrode that makes low resistance contact with at least a part of 1) m region 12, and A! It becomes a terminal. 32
is a second region in low resistance contact with at least a portion of the n-kaku area 14.
This electrode is the B2 terminal. A third electrode 33 is provided on at least a portion of the n11 region 15 via the insulating film 40, and is represented as a G8 terminal. The third electrode 33 connects to at least a portion of the 9m region 13 via the insulating film 40.
It is provided so as to extend over at least a portion of the w-region 16. A fourth electrode 34 is provided on at least a portion of the pI+ region 13 via an insulating film 40, and serves as a G4 terminal. The fourth electrode 34 is provided so as to extend over at least a portion of the nl region 15 and at least a portion of the nl region 14 via the insulating film 40 . Between the first electrode 31 and the fourth electrode 34, there is a third electrode adjacent to the first electrode 31.
The second electrode 32 is adjacent to the fourth electrode 34.
are arranged so that they are lined up. The G3 terminal and the G4 terminal are connected to the same potential by wiring such as At.

The semiconductor device of this embodiment has, for example, F, H, LEE:
IEEE '['transactions on E
electrompevices vom ED-15,4
9, 1968, p645.
It is formed independently within a single-crystal island of a dielectric isolation substrate created by an al passivated integrated circuit (EPIC) process.

Specific examples of each dimension etc. in this example are shown below.

The depth of the first pn junction and the third pn junction is approximately 5 μm1 The depth of the second pn junction is approximately 3 μm S pB region 13 and pv
- the distance to region 16 is approximately 55 μm; n11 area 1
The impurity concentration of No. 5 is 2 x 10"cm-".

The p1+- region 160 surface impurity concentration is 7×10” sub-3
It is. 1) B region 13 under the fourth electrode 34 is nI+
10” since it is between area 14 and the self-line structure.
It is possible to reduce the surface impurity concentration to less than 1 cm.

Insulating film 40 under the third electrode 33 and fourth electrode 34'
The thicknesses are 0.9 μm and 0.7 μm, respectively. However, 3rd.
In order to alleviate electric field concentration at the ends of the fourth electrodes 33 and 34, the insulating film 40 at the ends of these electrodes has a thickness of about 2.7 cm.
It is made as thick as μm.

The operating mechanism and features will be explained below using FIG. First, the operating mechanism when turning on will be explained.

When switch 1 is open, the circuit between Am and B1 is in an off state. When switch 1 is closed and a voltage higher than the threshold voltage is applied to power supply 8, υG, terminal, and G4 terminal, AC power supply 4
When the forward bias state is established between A2 and B1, it turns on. At this time, Gs, the potential of the G4 terminal and the B2. Although As and Bs can be turned on regardless of the level relationship of the potentials of the Al terminals, the operating mechanism differs depending on the relative relationship of the potentials between the terminals.

Gs, the potential of the G4 terminal is Al, B! If the potential is lower than that of the terminal, p is applied to the surface of the n11 region 15 under the third electrode 33.
A channel is formed from pffi-region 16 to p-region 1
Holes flow into 3. As a result, n, territory area 4 to 1) +
Electron injection into region 13 is promoted and n! ipm nm
) The gingister portion turns on and electrons flow into the nII region 15. Therefore, next from pz-region 16 to nB region 1
The injection of holes into 5 is promoted and 1) m n++ I) B
) The transistor part turns on.

ng p+ ns ) transistor part and pg n+
+ pm) Since the collector currents of the transistor parts mutually become the base currents of other transistor parts, positive feedback occurs, and finally the thyristor Ilf nn I)l n
It turns on as x.

When the potential of the Gs and G4 terminals is higher than the potential of the Bz and All terminals, an n channel is formed on the surface of the p+ region 13 under the fourth electrode 34, and from the nt region 14 to the nl region 15
Electrons flow into. As a result, px-pz containing region 16
The injection of holes from the region 12 to the nl region 15 is promoted and p
l nn pm ) The transistor part turns on and the hole becomes p
It flows into the H region 13.

Therefore, the injection of electrons from the nE region 14 to the 9m region 13 is promoted, and the nMpIInB transistor section is turned on, causing the above-mentioned positive feedback and the thyristor pv nmp++'
n'z turns on.

Gs, the potential of the G4 terminal is higher than the potential of the B2 terminal, and A
When the potential is lower than the potential of the two terminals, the operations in both of the above cases occur and the thyristor pz nm 1) s nr+ is turned on.

In this embodiment, when Ω is connected to the resistor 10 between the 9m region 13 and the nl region 14 to increase the noise tolerance, G3
A2. by setting the terminal potential to about 4V. The inventor has confirmed that it is possible to turn on between the Bs terminals. The inventor has also confirmed that by setting the potential of the G4 terminal to about 7V, it is possible to turn on the terminals As and Bs. Therefore, in this case, in order to connect the Q and G4 terminals and turn on the Al and B2 terminals, the voltage potential needs to be about 7.

Next, withstand voltage will be explained using FIGS. 3 and 4. First, a case will be described in which the switch 1 is closed and the potential of the GslG4 terminal is fixed to a low potential that does not turn on Ax and B. Since the Al1B2 terminals are 70-Tig, the withstand voltage varies depending on the potentials of these terminals and the potentials of the Gs and G4 terminals.

If the potential of the Gs and Ga terminals is lower than the potential of the Am and Bz terminals, n and region 1 in both forward and reverse bias.
Since the depletion layer on the 5 side is expanded by the Gs and G4 electrodes near the surface, a high breakdown voltage can be ensured. The dotted line in FIG. 3 shows a schematic diagram of the depletion layer ends in the n11 region 15 and the 9m region 13 during forward bias.

Since the third and fourth electrodes 33, 34 have a lower potential than the nu region 15, positive charges are induced on the surface of the nl region 15 below these electrodes 33, 34, the concentration decreases, and the depletion layer tends to expand. The third and fourth electrodes 33.34 are 9m area 1
Although the potential is lower than that in pB region 13, the impurity concentration in pB region 13 is sufficiently higher than in nB region 15, so that the influence of induced positive charges is small. As a result, the depletion layer is expanded on the surface of the nB region 5, and the electric field is relaxed.
A high withstand voltage that is regulated within the 3i bulk can be ensured. On the other hand, a schematic diagram of the depletion layer edge in nB, pm, and pz- at the time of reverse bias is shown by a dashed-dotted line in FIG. It will be expanded to 1) In the E-region 16, the concentration increases due to the induced positive charge, and the spread of the depletion layer becomes smaller than when the third electrode 33 does not exist on the pE-region 16, but the depletion layer on the nIl region 15 side is forward biased. Since the voltage spreads to the same extent as in the case of forward bias, it is possible to secure a breakdown voltage of the same extent as in the case of forward bias. Since the reverse bias is applied under the first electrode 31, the potential of the first electrode 31 is n, lower than the potential of the region 15, and therefore nB
Positive charges are induced on the surface of the region 15, and the depletion layer tends to expand. As a result of the above, it is possible to ensure a high breakdown voltage that is regulated within the Si bulk. In this embodiment, the order reverse breakdown voltage is also 400V, for example.

Next, G3. The potential of the G4 terminal is A2. In this case, the depletion layer near the surface on the nB region 15 side is the third.
and a fourth electrode 33,34 is induced on the surface. Contracted by negative charge. At the time of forward bias, the depletion layer collapses as indicated by the dotted line in FIG. 4, and the withstand voltage is regulated by the electric field concentration on the surface, resulting in a decrease. In this embodiment, for example, about 150
It is V. On the other hand, at the time of reverse bias, as shown by the dashed line in FIG. 4, the n! On the surface of the first region 15, the depletion layer is contracted, but in the pv- region 16 under the third electrode 33, the concentration is reduced by the induced negative charge, and the depletion layer is sufficiently expanded. Therefore, the electric field strength near the bottom of the third electrode 33 can be made lower than the electric field strength in the bulk. n! under the first electrode 31! Since the surface of the l region 15 is reverse biased, the potential of the first electrode 31 is n! The potential is lower than that of the I region 15, so positive charges are induced on the surface of the nIl region 15, the depletion layer is likely to expand, and the electric field strength can be lowered. As a result of the above, it is possible to realize a high breakdown voltage at the time of reverse bias, which is regulated within the 3i bulk. In this embodiment, the voltage is approximately 360V, for example.

As described above, when the potentials of the third and fourth electrodes 33 and 34 are fixed, a high breakdown voltage of 150 V or more can be ensured when forward biased and 360 V or more when reverse biased. Switch 1 is open and G3. When the potential of the G4 terminal is not fixed, the above-mentioned induced charges are hardly generated and the withstand voltage can be approximately 220V when forward biased and approximately 400V when reverse biased.

Note that Gs, G4 terminal, ! of this embodiment. :A2 ・B
The DC insulation voltage between the two terminals is, for example, about 650V.

Further, after being turned on, the potential difference between A2 and 8g when 100 mA was applied, that is, the on voltage was about 1.3 V.

Further, the on-resistance is 8Ω.

<Embodiment 2> FIG. 5 is a schematic plan view showing a second embodiment of the present invention, and FIG.
The figure is a schematic sectional view taken along the line AA' in FIG.

This embodiment differs from the first embodiment in the following three points, and the rest is essentially the same as the first embodiment.

(1) The p++ region 14 includes a bar (low impurity concentration p-type base) region 1B having the same surface impurity concentration as the sixth region and the px- region 16 near the main surface in contact with the nII region. The pB- region 18 functions as an electric field relaxation layer to improve forward breakdown voltage, and becomes a channel region under the fourth electrode 34.

A fifth electrode 35 is provided between the second electrode 32 and the third electrode 33 and is in low resistance contact with a part of the 9m area 13, and is connected to a protection circuit (not shown).

(3) By providing the pm-region 18, the distance between the nE region 14 and the pE region on the main surface increases to 90 μm.

The turning-on mechanism between the Ag and Bx terminals of this embodiment is the same as that of the first embodiment except for the following points.

(1) Gs, the potential of the G4 terminal is A2. When the potential is lower than the potential of the Bz terminal, the p-type region 18 becomes pm"+"+
It acts as the drain of the p-channel MO3) transistor section composed of px- and contributes to the ON operation between the Ai and *Bt terminals.

(2) When the potential of the G3 and G4 terminals is higher than the potential of the AJ and B2 terminals, in addition to the pB region 13, the pll- region 18 is also composed of nir pm"'+ pm, 11+ 5, n-channel MO3 ) It acts as a channel part of the resistor and contributes to the ON operation between the AJ and Bz terminals.

Next, the effect of the pm-region 18 on the forward breakdown voltage will be explained. In the first embodiment, when the potential of the Gs + Ga terminal is higher than the potential of the AJ and Bg terminals, AJ - B1
Since the depletion layer in the vicinity of the surface of the nII region 15 under the third and fourth electrodes 33, 34 is compressed when the voltage is forward biased, the forward breakdown voltage is, for example, about 150V. In this embodiment, the depletion layer is shortened near the surface of the nB region 15 as in the first embodiment, but the surface concentration is reduced near the surface of the plI- region 18 under the third electrode 33 because negative charges are induced. This makes it easier for the depletion layer to expand. As a result, the electric field strength can be reduced significantly. On the other hand, the third and fourth electrodes 33 of the p11-region 18
．． 34, the low impurity concentration is also effective and the depletion layer expands, thereby relaxing the electric field strength near the surface junction. As a result of the above, electric field concentration during forward bias is alleviated, so that in the case of this embodiment, the forward breakdown voltage can be improved to, for example, about 360 cm.

<Embodiment 3> FIG. 7 is a schematic plan view showing a third embodiment of the present invention. Compared to the second embodiment, by improving the forward breakdown voltage without providing the pm-region 1B, Ax *
This embodiment is characterized by a reduction in on-resistance between 13g and 13g.

As is clear from a comparison with FIG. 5, the third and fourth electrodes 33 and 34 are comb-shaped, and the second
The electrodes 35 are also comb-shaped so that they interlock with each other. The second embodiment is the same as the second embodiment except that the electrode pattern is improved, the PM-region 18 is removed, and the distance between the NG region 14 and the PX region 12 is set to about 75 μm.

First, withstand voltage will be explained. A2. When the voltage between Bz and Bz is forward biased, the second and fifth electrodes 32 and 35 extending over the nl region 15 act as field plates to relieve the electric field concentration on the surface of the n1 region 15. This is because the potentials of the second and fifth electrodes 32', 35 are lower than the potential of the nB region 15, so positive charges are induced on the surface of the nB region 15, and the surface concentration of the nB region 15 is reduced. On the other hand, Am t
82-41'l1lj When the bias is applied, the potential of the third and fourth electrodes 33°34 is the same as that of the first and second electrodes 31.32
It was explained in the first embodiment that when the potential is higher than , the withstand voltage is low. This was due to negative charges being induced on the surface of the n11 region 15 by the third and fourth electrodes 33 and 34. However, in this embodiment, as a result of interlocking the third and fourth electrodes 33.34 with the second and fifth electrodes 32.35, a third electrode is formed on the surface of the region 15 in the area n.
and the negative charge induced by the fourth electrode 33.34 is n
It is rejected from the surface by a lateral leakage field by the second and fifth electrodes 32,35 extending in region B 15.

During forward bias when A2 and Bt are in the off state and a high voltage is applied, the potential of the A3 terminal, that is, the nII region 15
The potential of Gs, G4 is sufficiently higher than the potential of the B2 terminal.
This value is closer to the terminal potential. Therefore, the negative charges induced by the third and fourth electrodes 33, 34 are almost completely rejected by the second and fifth electrodes 32,35. As a result, the concentration of the surface of the nII region 15 is reduced, and the depletion layer expands easily9, making it possible to achieve a high breakdown voltage.

In this embodiment, when the distance between the second and fifth electrodes 32.35 and the third and fourth electrodes 33.34 is set to about 8 μm, for example, a forward breakdown voltage of about 370 V can be achieved. The reverse breakdown voltage is approximately 400V, which is not affected by the comb-shaped structure.
It is.

Note that in this embodiment, p3-region 18 is deleted and n, region 14 is deleted.
As a result of reducing the distance between the p-type region 12 and the p-type region 12 to about 75 μm, the on-resistance can be reduced. For example, 30
The on-resistance when mA current is applied is about 6Ω, which is about 1.5Ω smaller than that of the second embodiment.

<Embodiment 4> FIG. 8 is a schematic sectional view showing a fourth embodiment of the present invention. When compared with the second embodiment, it is almost the same except for the following four points.

(1) pB- only in the position opposite to the pv- region 16
Point where region 18 was formed, (2) nz 14. pi+ 13.1)n-18,n
n-channel MO3-FET (
(3) p+r region 1, in which the third electrode 33 is provided so that the Df yarn part is formed at a position facing the pE- region 16, and the third and fourth electrodes are connected and integrated;
(4 ) Protection circuit against steep voltage noise (not shown)
The contact portion of the fifth electrode 35 for connection is placed in the 2M region 12.
Provided on the 9m area 13 on the side not facing the nl area 14
, 9M The point where the distance between the regions 12 is reduced to 55 μm.

In this embodiment, as in the second embodiment, the electric field concentration under the third and fourth electrodes 33 can be relaxed in the 1) m'' region 18, so that the breakdown voltage is approximately the same, that is, for example, the breakdown voltage is about 365V,
Reverse breakdown voltage of approximately 400V can be obtained.

On the other hand, the on-resistance (when 30mA is applied) is in the nN range of 14.2
As a result of the distance between the g regions 12 being reduced, it can be reduced to about 4.52, which is about 3Ω smaller.

<Embodiment 5> FIG. 9 is a schematic sectional view of a fifth embodiment of the present invention.

This embodiment differs from the first embodiment shown in FIG.
The rest is the same as the first embodiment except that there is no m-region.

<Embodiment 6> FIG. 10 is a schematic sectional view of a sixth embodiment of the present invention.

The difference between this embodiment and the fifth embodiment shown in FIG. 9 is as follows.
The fourth region 9g region 12 is provided so as to surround the region 15, and the first electrode 31 is provided on the other main surface 24 of the semiconductor substrate 23.

9m area 12. pm area i3. The junction depths of the nxm regions 14 are about 25 μm, about 25 μm, and about 15 μm, respectively. n
The impurity concentration of l region 15 is 1×10"tyn-". The I)m region 13 under the fourth electrode 34 is formed by diffusion of gallium only, and other pII regions 13 and I)
) The IT region 12 and the p region 12-1 are formed by only boron or by double diffusion of polo/and gallium. As is well known, gallium exhibits significant out-diffusion, so the concentration near the surface can be kept low. Therefore, an n-channel can be formed with a low gate voltage. In this embodiment, the concentration near the surface under the fourth electrode 34 is set to approximately 5×101stm.
-”.When G3 and G4 terminals are connected, A2
, B! To turn on between the terminals, it is necessary to set the Gs and G4 terminal voltage to 15V. However, an external resistor of Ω is connected between the nN region 14 and the pB region 13. In this embodiment, A2. The on-voltage when 5A is applied between the B2 terminals is, for example, about 1.35V. Also, the forward and reverse blocking voltage between A2 and Bz terminals is approximately 200 V, and between Gz and G3 terminals and A
! The insulation voltage between the life B3 terminals is approximately 800V.

This embodiment has a vertical groove structure, and since the first electrode 31 can be brought into direct contact with the heat sink, the thermal resistance can be reduced.

Therefore, it has the characteristic that power loss can be reduced.

As described above, according to this embodiment, the number of pz nu 1)w nz elements is n.

As a result of being able to drive with a p-channel MOS @FET, it is possible to realize the same function as an optically coupled thyristor with a monolithic structure, and to significantly reduce the control current. Furthermore, under the gate electrode, 1) a px- region with a lower impurity concentration than the l region (in some cases, a pm' region with a lower impurity concentration than pl on the pE side as well);
''), the reverse breakdown voltage (or forward breakdown voltage in some cases) can be significantly improved.

It is obvious to those skilled in the art that the present invention is not limited to the embodiments described above, and that various modifications and applications can be made based on the same idea.

〔Effect of the invention〕

According to the present invention, the control section and the main drive section can be isolated in terms of direct current with a monolithic structure, the potential of the unipolar element can be controlled reliably even in a floating state, the control current can be reduced, and the A semiconductor device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view showing a first implementation hook of the present invention, and FIG.
The figure is a circuit diagram showing a conventional example, Figures 3 and 4 are schematic cross-sectional views for explaining the effects of the first embodiment, and Figures 5 and 6 are diagrams showing a second embodiment of the present invention. 7 is a schematic plan view showing a third embodiment of the present invention, and FIG. 8 is a schematic sectional view showing a fourth embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing the fifth embodiment of the present invention;
FIG. 0 is a schematic sectional view showing the present invention and a sixth embodiment. 12... pz area 13... p1 area, 14...
ng region 15... nII region, 31... first electrode, 32... second electrode, 33... third electrode, 3
4...Fourth electric plan 1 Pleasure plan 2 Figure 1 D Mistake 3 Mouth too 4th Day 5 Cheer too C(2) Mo cl Nikkatsu 10 mouth

Claims (10)

[Claims] 1. It has a pair of main surfaces, a first region of a first conductivity type exposed on at least one of the main surfaces, and a first pn junction formed between the first region and the first region. a second region of a second conductivity type formed in the first region so as to terminate on the one main surface; a second pn junction formed between the second region; a third region of the first conductivity type formed in the second region so as to terminate on the main surface of the third region; a third pn junction formed between the first region and the first region; a semiconductor substrate having a fourth region of a second conductivity type formed so as to terminate on at least one main surface apart from the pn junction; and a first region in resistive contact with at least a portion of the fourth region. a second electrode in low resistance contact with at least a portion of the third region;
A third portion provided on at least a portion of the first region so as to extend over at least a portion of the second region and the third region via an insulating film on the one main surface. an electrode, provided on at least a portion of the second region so as to extend over at least a portion of the first region and the third region via an insulating film on the one main surface of the electrode; A semiconductor device comprising: a fourth electrode. 2. The semiconductor device according to claim 1, wherein the fourth region is provided within the first region. 3. The semiconductor device according to claim 1, wherein the fourth region is provided so as to surround the first region. 4. In claim 1, the fourth region includes a fifth region having a low impurity concentration in a region opposite to the second region.
A semiconductor device characterized by having a region. 5. Claims 1 or 4 are characterized in that the second region has a sixth region with a low impurity concentration near the one main surface in contact with the first region. semiconductor device. 6. 6. The semiconductor device according to claim 5, wherein impurity concentrations in the fifth region and the sixth region are approximately equal. 7. Claim 1 or 2 is characterized in that the first electrode, the second electrode, the third electrode, and the fourth electrode are provided on the one main surface. semiconductor device. 8. In claim 3, the second electrode,
A semiconductor device, wherein the third electrode and the fourth electrode are provided on one main surface, and the first electrode is provided on the other main surface. 9. A semiconductor device according to claim 1, further comprising a fifth electrode that makes low resistance contact with a portion of the second region. 10. The semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are integrated.