JPS6248072A - Semiconductor device - Google Patents

Abstract

PURPOSE:To extend a gate control range by partly forming the second conductivity type semiconductor region of high impurity density region corresponding to a gate region on the other surface of a substrate, and spacing an interval between the bottom of the second conductivity type region and the first conductivity type drain semiconductor layer. CONSTITUTION:Since a P<+> type drain/collector region 70 is partly formed on the other surface of an N<+> type drain/collector layer 10 directly under a gate electrode 2 and an N<+> type buffer layer 100 is formed on the bottom surface of the P<+> type drain/collector region, holes are partly implanted from the region 70 to a drain drift layer 6, and the implanting is suppressed by the layer 100. Thus, the transporting efficiency of the base region of a parasitic PNP transistor is decreased to reduce a DC current amplification factor hFE, thereby increasing a gate control range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a high-power, high-speed, high-frequency switching element is monolithically realized.

[Prior Art] Several types of high-power, high-speed, high-frequency switching elements with low on-resistance have been used in the past, such as one shown in FIG. 3, for example.

FIG. 3 is a cross-sectional view showing the structure of a conventional monolithically constructed conductivity modulated metal oxide semiconductor field effect transistor (hereinafter referred to as a CAT device). First this CA
The configuration of the T element will be explained. J3 in the diagram, CAT
The structure of the device is such that the n+ type drain substrate and the p+ type drain/collector layer of a conventional double-diffused metal nitride semiconductor field effect transistor (hereinafter referred to as MOSFET) are replaced. To explain in detail, p1
On one surface of the type drain/collector 8i7, train drifts 1 to 6 made of, for example, an n-type epitaxial layer are formed.
is formed. A plurality of p-type base regions 5 are formed at intervals on the surface of the train drift layer 6, and two 01-type source/emitter regions 4 are formed at intervals on the surface of the p-type base region 5. are formed separately. Train drift between p-type base regions 5 [layer 6 surface, p-type base i'i [5 peripheral surface, and n+
An oxide film 3 made of silicon dioxide, for example, is formed on a part of the surface of the shaped source/emitter region 4 . Oxidation 1
A gate made of metal inside 3! 1wA2 is formed, and this gate electrode is connected to the o1 type source/emitter region 4.
It extends to the top. In addition, the source/emitter 1! is formed on the central surface of the rectangular base region [5, another part of the 0+ type source/emitter 1j14m4 surface, and the surface of the oxide film 3]. Pole 1 is formed. Here, n+ type source/emitter region 1
44, p-type base region 5, and drain drift layer 6 are M
Prepare the parasitic npn transistor in the OSFET,
The p-type base region 5, the drain drift layer 6, and the 01-type drain/collector layer 7 constitute a pnp t-latching parasitic to the M03FE. A drain/collector electrode 8 is formed on the other surface of the p1 type drain/collector l117. Further, G is a gate electrode terminal, S/E is a source/emitter electrode terminal, and D/C is a drain/collector electrode terminal.

FIG. 4 is a diagram showing an equivalent circuit of the CAT element of FIG. 3. Considering the ideal current flow, the equivalent circuit of this CAT element should be a series (connection d) of a MOSFET and a pin diode D2, but in reality it is ~IO
It is a combination of a 3FET and a thyristor consisting of a parasitic npn t-latching and pnp transistor.

Next, the operation of this CAT element will be explained.

When the gate electrode terminal G and the source/emitter electrode terminal S/E are short-circuited and a reverse bias voltage is applied between the drain/collector electrode terminal D/C and the source/emitter electrode terminal S,/2, the pin diode D2 reverses. It becomes a bias and reverse bias blocking characteristics appear.

Furthermore, when a forward bias voltage is applied between the drain/collector electrode terminal D/C and the source/emitter electrode terminal S/E, the diode D becomes reverse biased and a forward bias blocking characteristic appears. In this state, when a voltage higher than the threshold voltage of the MOSFET is applied between the gate electrode terminal G and the source/emitter north terminal S/day, a channel is formed in the p-type base region 5 and the MOSFET is activated. At the same time as it enters the operating state, the pin diode D2 causes a pin diode operation phenomenon, and the p+ type drain/collection 92
Holes are injected from the layer 7 into the drain drift 116 to increase the conductivity of the drain drift layer 116 and turn on the CAT device with low resistance. Also, in order to turn off the CAT element, the gate! By short-circuiting the pole terminal G and the source/emitter terminal S/E, the voltage applied between these terminals is lower than the threshold voltage of the M03FET. Return the inverted region on the surface of the base region 5 to its original state and drain drain i.
- Stop the supply of electrons to layer 6. At the start of turn-off, the electrons injected up to that point into the drain drain l layer 6 are concentrated, but these single electrons are injected into the p+ type drain/'collector 117, and a corresponding number of holes are generated. A current flows through the p-type base region 5. If this state continues, the concentration of electrons in the drain drift layer 6 will decrease, but in order for the CAT element to turn off, the remaining holes and electron plasma must cancel each other out through recombination.

The above is an explanation of the operation of the CAT device when the thyristor region parasitic to the MOSFET does not latch at turn-on, but the biggest problem with the CAT device is that the thyristor region causes a latching phenomenon at low current levels. When the thyristor region latches, the gate control ability of the GA device is lost and it becomes difficult to turn it off. The cause of the latching phenomenon is that the npn transistor in the thyristor region and the pnp t-latching interact with each other at high current density during turn-on. The conditions for the thyristor region to latch when turned on are that the sum of the DC current amplifier factors hrt of each of the npn transistor and pnp transistor is >1, and the npn
This is the case when the voltage effect V at the resistor R8 of the p-type base region 5 of the transistor is 0.4 to 0.8 V or more at 300'K.

Figure 5 shows another CAT! that has solved the above problems to a certain level! FIG. 3 is a cross-sectional view showing the structure of the child. In the figure, p4 with high impurity concentration is located in the center of the p-type base region [5].
A shaped base central gA region 50 is formed, and an n+ type buffer 1119 is inserted between the drain drift [6 and the p + type drain and the in 7399917. Also, this CA
The equivalent circuit of the T element is the same as the circuit shown in FIG. p
The DC current amplification factor hrε of the parasitic npn 1-transistor is lowered by the + type base center vA region 50, and the injection of holes from the ρ1 type drain/collector layer 7 to the drain drift layer 6 is suppressed by the n+ type buffer 119 to suppress the parasitic pn
By lowering the DC current amplification factor h of p t-transistor ε, the CAT element is made less likely to latch when turned on.In other words, the latching N current bell is raised compared to the CAT element shown in Figure 3. .

18Jm points that CR Ming tries to solve] Conventional C and A used as high power high speed high frequency switching elements
The problem with the T element is that the current level at which the thyristor region parasitic to the jνIO3FET latches is low, and in order for the CAT element to operate normally it must be used at a current level below the latching level, and its gate N range is narrow. There was a point.

This invention was made in order to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device that can increase the latching current level of the thyristor region parasitic to the MOSFET and widen the gate Jtll range. do.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a first conductivity type drain semiconductor substrate with a high impurity concentration and a first conductivity type train semiconductor with a low impurity concentration formed on one surface of the substrate. layer and
A MOS type electric field comprising a first conductivity type source semiconductor fj4 region of high impurity aa formed on the surface of this first conductivity type drain semiconductor layer, and a gate region formed at a predetermined position on the first conductivity type drain semiconductor layer surface. In the effect transistor, a second conductivity type semiconductor region with high impurity concentration of 1 degree is partially formed on the other surface of the substrate corresponding to the gate region, and the bottom of the second conductivity type semiconductor region is formed as a first conductivity type drain. It is arranged to be spaced apart from the semiconductor layer.

[Function] In the present invention, a second conductivity type half body lj region having a high impurity concentration of 1 degree is partially formed on the other surface of the first conductivity type drain semiconductor substrate having a high impurity concentration, corresponding to the gate region, Since the bottom of the second conductivity type semiconductor layer is separated from the first conductivity type drain semiconductor layer, injection of carriers from the second conductivity type semiconductor region to the first conductivity type drain semiconductor layer is suppressed, and the MOSFET The direct current amplification factor hrE of the transistor parasitic to the current decreases. Also, the carrier is the second
Since it is efficiently injected into the first conductivity type drain semiconductor layer from the first conductivity type semiconductor region, the conductivity of the first conductivity type drain semiconductor layer is modulated to the same degree as in the prior art.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing the structure of a heptagonally constructed CAT element according to an embodiment of the present invention. The configuration of this embodiment is the same as that of FIG. 3 except for the following points. That is, an n+ type drain/collector layer 10 is formed on the surface of the drain/collector electrode 8 instead of the p+ type drain/collector layer 7, and a drain drift 116 is formed on one surface of this n1 type drain/collector layer. There is. In addition, a D" type drain/collector region 70 is partially formed on the other surface of the n" type drain/collector layer 10 directly under each gate electrode 2, and the bottom of this p+ type drain/collector region is a drain drift layer 6. A space is separated from the surface, and this space is one layer of n+ type buff 10
0 is formed.

Also, as shown in FIG. 5, a p''-type base central portion [50 is formed in the center of the p-type base f!4 region 5.

n+ type source/emitter region 4 and p type base@region 5, t
++-shaped base central region 50 and train drift [6, n
+-type drain/collector 1110 constitutes the npn l-run risk parasitic to the MOSFET, and the p-type base compensation area 5. The p+ type base central region 50, the drain drift layer 6, the 0+ type train/collector Ili'IO, and the p' type drain/collector region 70 constitute a parasitic pnp t-run risk in the MOSFET, and both these transistors are parasitic. It constitutes the thyristor area.

FIG. 2 is a diagram showing an equivalent circuit of the CAT element of FIG. 1. In the figure, the equivalent circuit of this CAT element is an n-channel MO3 with a parasitic pin diode D2 between the gate electrode terminal G and the drain/collector electrode terminal D/C terminal.
It is an FET.

Next, the operation of this CAT element will be explained.

p+ type drain/this 99m11fu0 each gate electrode 2
Since it is partially formed on the surface of the n+ type drain 7/collector region immediately below, and the 01 type buffer w1100 is formed on the bottom surface of this p1 type drain/collector region, the O+ type drain 7/collector region! [! 70(pn
Holes are partially injected from the 9+ emitter of the ρ transistor into the drain drift layer 6, and this injection is suppressed by the 1)"-shaped buffer layer 100. Therefore, the transport efficiency of the base region of the parasitic 1Jnp transistor decreases. Then, the DC current IJI width factor, ε is the conventional C
It is significantly lower than the AT element. In addition, the holes in the p+ type drain/collector 111 and the like are drain ('
The holes flow straight upwards with the ζ lift layer 6 being squeezed, and most of the holes reach the periphery of the p-type base region 5, and some of them reach the p+-type base central region 50 and form the 0+-type source/'emitter. Exit to territory 144. Therefore, the voltage drop at R8 in the base region due to the Hall current vs.
It is 10 times smaller than the AT element. In this way, this CA
In the T element, the DC current amplification factor hrE of the L-run risk decreases, and the parasitic npn L-run risk's p-type base region, center 1d5 of the p+-type base
Since the voltage drop (2) at zero becomes small, the parasitic si-risk region will not latch at the current level that would cause latching in a conventional CAT element. That is, the latching current level is increased compared to the conventional CA lower element. Therefore, the turn-off of the CAT element becomes easy, and high-speed high-frequency switching characteristics are improved. Also, this C
In AT elements, the latching current level increases as mentioned above, so the gate control range is wider than in conventional CAT elements, and this also makes it possible to increase the current density of CAT elements, making it possible to reduce the chip size. It is possible to reduce the size and cost of the CΔT resistor.

Regarding the conductivity modulation of the train drift layer 6,
It is effective to generate the conductivity directly under the gate electrode 2, and conductivity modulation directly under the p+ type base central region 50 is unnecessary. Therefore, p+ type drain/collector a region 7
0 is partially formed just under the gate electrode 2 to form a p" type drain/collector region [70 to drain drift l1
Holes are efficiently injected into 16, thereby achieving a conductivity modulation effect equivalent to that of a conventional CAT element and lowering the on-state voltage. Furthermore, in the conventional CAT device, since the p'' type drain/collector layer 7 is formed over the entire area of the drain drift layer 6, holes accumulated in the drain drift layer 1 and layer 6 at the time of turn-off and turn-on are transferred to the p+ type drain layer 6. /Collector M7 blocked the hole and it was difficult to handle, but in this CAT element, holes are blocked only in a narrow area at the bottom of the ρ-shaped drain/collector region 70, and even if the n+-type Todo 112 around it is The turn-off operation of the CAT element becomes easy, and the high-speed high-frequency switching characteristics are improved.

In the above embodiment, the CAT element is of n-type, but it goes without saying that the present invention can also be applied to a p-type CAT element in which the conductivity types of each layer and each region of FIG. 1 are reversed.

[Effects of the Invention] As described above, according to the present invention, a first conductivity type drain semiconductor substrate with a high impurity concentration, a first conductivity type train semiconductor layer with a low impurity concentration formed on one surface of this substrate,
High impurity v formed on the surface of the first conductivity type drain semiconductor layer
A MOS field effect transistor comprising a first conductivity type source semiconductor region having a JJ concentration and a gate region formed at a predetermined position on the surface of the first conductivity type drain semiconductor layer,
A second conductivity type semiconductor region with a high impurity concentration is partially formed on the other surface of the substrate corresponding to the gate region, and
Since the bottom of the conductive type semiconductor region is separated from the first conductive type drain semiconductor layer, the MOS FET
Accordingly, it is possible to obtain a semiconductor device in which the range of gate control a can be expanded by increasing the level of the latching current in the thyristor region parasitic to the thyristor region.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit of the CAT element shown in FIG. 1. Third
The figure is a cross-sectional view showing the structure of a conventional monolithically constructed CA element. FIG. 4 is a diagram showing an equivalent circuit of a conventional CΔF element. 13 is a cross-sectional view showing the structure of another CAT element formed monolithically. In the figure, 1 is a source/emitter electrode, 2 is a gate electrode, 3 is a gate electrode, 4 is an n+ type source/emitter region, and 5 is a CAT element.
is a p-type base region, 50 is a p+-type base central region, 6 is a drain drift layer, 70 is a p+-type drain/'collector region, 8 is a drain/'collector electrode, 10 is an n+-type drain/collector layer 100 is an n+-type It is a buffer layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A first conductivity type semiconductor substrate having a high impurity concentration and serving as a drain layer; a first conductivity type semiconductor layer having a low impurity concentration formed on one surface of the substrate and serving as a drain layer; A MOS type field effect transistor comprising: a first conductivity type semiconductor region with a high impurity concentration formed on a surface of a conductivity type semiconductor layer and serving as a source region; and a gate region formed at a predetermined position on the surface of the first conductivity type semiconductor layer. A second conductivity type semiconductor region with a high impurity concentration is partially formed on the other surface of the substrate corresponding to the gate region, and a bottom of the second conductivity type semiconductor region is connected to the first conductivity type semiconductor layer. A semiconductor device characterized in that the semiconductor device is spaced apart from each other.