FR2462025A1 - MONOLITHIC INTEGRATED CIRCUIT WITH COMPLEMENTARY MOS TRANSISTORS - Google Patents
MONOLITHIC INTEGRATED CIRCUIT WITH COMPLEMENTARY MOS TRANSISTORS Download PDFInfo
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- FR2462025A1 FR2462025A1 FR8016206A FR8016206A FR2462025A1 FR 2462025 A1 FR2462025 A1 FR 2462025A1 FR 8016206 A FR8016206 A FR 8016206A FR 8016206 A FR8016206 A FR 8016206A FR 2462025 A1 FR2462025 A1 FR 2462025A1
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- 230000000295 complement effect Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 230000005669 field effect Effects 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 11
- 238000002347 injection Methods 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 6
- 230000037452 priming Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000003874 inverse correlation nuclear magnetic resonance spectroscopy Methods 0.000 abstract 1
- 244000045947 parasite Species 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
L'INVENTION CONCERNE UN CIRCUIT INTEGRE CMOS A ISOLEMENT PAR JONCTION P-N POLARISEE EN INVERSE, LE TRANSISTOR A CANAL N 5, 10 ETANT PAR EXEMPLE DIFFUSE DANS UN CAISSON D'ISOLEMENT DE TYPE P 2 CREE DANS LE SUBSTRAT OU LA COUCHE EPITAXIALE N 1 A COTE DU TRANSISTOR A CANAL P 6, 9 ET, PLUS PARTICULIEREMENT, DES MOYENS DE PROTECTION CONTRE L'AMORCAGE D'UN THYRISTOR PARASITE ENTRE LES DEUX TRANSISTORS CONNECTES EN INVERSEUR FONDAMENTAL. CES MOYENS COMPRENNENT AU MOINS UN CONTACT A BARRIERE DE SCHOTTKY 3 ENTRE LE CAISSON P ET LE CONDUCTEUR DE CONNEXION DES DRAINS, CE CONTACT AYANT UNE TENSION DE SEUIL INFERIEURE A CELLE DE LA JONCTION 5-2 DE SORTE QUE LE DRAIN 5 NE PEUT AGIR EN EMETTEUR AUXILIAIRE DECLENCHANT UNE CONDUCTION PAR AVALANCHE A TRAVERS LES QUATRE COUCHES 9-1-2-10 SOUS L'INFLUENCE D'UNE BRUSQUE DESCENTE DU POTENTIEL DE DRAIN DUE, PAR EXEMPLE, AU COUPLAGE CAPACITIF GRILLE-DRAIN DU TRANSISTOR A CANAL N. UNE INJECTION DE TROUS PAR LE DRAIN 6 EST MOINS PROBABLE MAIS ELLE PEUT EGALEMENT ETRE EVITEE PAR UN SECOND CONTACT A BARRIERE DE SCHOTTKY 4 PARALLELE A LA JONCTION 6-1.THE INVENTION CONCERNS AN INTEGRATED CMOS CIRCUIT WITH AN INVERSE POLARIZED PN JUNCTION INSULATION, THE CHANNEL TRANSISTOR N 5, 10 BEING FOR EXAMPLE DIFFUSED IN A TYPE P 2 INSULATION BOX CREATED IN THE SUBSTRATE OR THE EPITAXIAL LAYER N 1 A SIDE OF THE P 6, 9 CHANNEL TRANSISTOR AND, MORE PARTICULARLY, MEANS OF PROTECTION AGAINST THE PRIMING OF A PARASITE THYRISTOR BETWEEN THE TWO TRANSISTORS CONNECTED AS A BASIC INVERTER. THESE MEANS INCLUDE AT LEAST ONE SCHOTTKY BARRIER CONTACT 3 BETWEEN THE P-BOX AND THE DRAIN CONNECTION CONDUCTOR, THIS CONTACT HAVING A THRESHOLD VOLTAGE LOWER THAN THAT OF JUNCTION 5-2 SO THAT DRAIN 5 CANNOT ACT IN AUXILIARY TRANSMITTER TRIGGERING AN AVALANCHE CONDUCTION THROUGH THE FOUR LAYERS 9-1-2-10 UNDER THE INFLUENCE OF A SHARP LOWERING OF THE DRAIN POTENTIAL DUE, FOR EXAMPLE, TO THE CAPACITIVE GRID-DRAIN COUPLING OF THE TRANSISTOR TO CHANNEL N. A INJECTION OF HOLES THROUGH DRAIN 6 IS LESS LIKELY BUT IT MAY ALSO BE AVOIDED BY A SECOND CONTACT AT SCHOTTKY BARRIER 4 PARALLEL TO JUNCTION 6-1.
Description
- 1 - La présente invention concerne un circuit intégré monolithiqueThe present invention relates to a monolithic integrated circuit
incluant une paire de transistors à effet de champ à grille isolée dont les types de conductivité sont complémentaires, ou inverseur CMOS. Dans l'inverseur CMOS le plus simple, un transistor d'un premier type de conductivité est formé de façon classique par diffusion de régions source et drain à la surface d'un substrat du type de conductivité including a pair of insulated gate field effect transistors with complementary conductivity types, or CMOS inverter. In the simplest CMOS inverter, a transistor of a first conductivity type is conventionally formed by diffusion of source and drain regions on the surface of a conductivity type substrate.
opposé et les régions source et drain du transistor complémen- opposite and the source and drain regions of the complementary transistor
taire sont implantés dans un îlot du premier type de conducti- are located in an island of the first type of
vité préalablement diffusé à la surface du substrat. Le signal d'entrée commande les deux transistors dont les drains sont reliés par une liaison galvanique sur laquelle est prise la previously scattered on the surface of the substrate. The input signal controls the two transistors whose drains are connected by a galvanic connection on which is taken the
sortie de l'inverseur et dont les sources sont reliées res- output of the inverter and whose sources are connected
pectivement aux pôles de la source d'alimentation, comme l'explique, par exemple, le journal technique allemand respectively at the poles of the power source, as explained, for example, in the German technical journal
"Elektronic", (1971) N0 4, p. 111 à 116. "Elektronic", (1971) No. 4, p. 111 to 116.
Il a été remarqué que si un circuit intégré monoli- It has been noted that if a monolithic integrated circuit
thique CMOS de ce type reçoit des impulsions de tension ou impulsions parasites à front très raide, il peut en résulter un court-circuit à travers le circuit intégré monolithiqueCMOS, such CMOS-type receives voltage pulses or very steep-edge spurious pulses, it may result in a short circuit across the monolithicCMOS integrated circuit,
ce qui est susceptible d'entraîner sa destruction. Le phénomè- which is likely to lead to its destruction. The phenomenon
ne s'observe surtout dans les circuits CMOS comprenant des électrodes de commande en aluminium ayant une tension de seuil élevée, et qui sont destinés à fonctionner à des tensions is mainly observed in CMOS circuits comprising aluminum control electrodes having a high threshold voltage, and which are intended to operate at voltages
d'alimentation élevées.high power supply.
Il a été admis que ceci était dû aux capacités formées par le chevauchement des électrodes de commande et des régions drains. En fait, dans le cas de l'inverseur CMOS, les It was recognized that this was due to the capacitances formed by overlapping control electrodes and drain regions. In fact, in the case of the CMOS inverter, the
électrodes de commande et les électrodes de drain des transis- control electrodes and the drain electrodes of the transistors
tors à canal n et à canal p sont reliées entre elles par des motifs conducteurs en aluminiủm obtenus par évaporation. Donc, The n-channel and p-channel tors are interconnected by aluminous conductive patterns obtained by evaporation. So,
durant le processus- de commutation, une partie de la varia- during the switching process, part of the variation
tion de tension sur l'électrode de commande est transférée par la capacité de chevauchement de l'électrode de commande, Voltage on the control electrode is transferred by the overlap capacitance of the control electrode,
à la région drain des transistors. to the drain region of the transistors.
Un échelon de tension de pente infinie VG à l'élec- A voltage step of infinite slope VG at the elec-
trode de commande entraîne donc une variation de tension sur l'électrode de drain:A UD = A UDmax xAuG Cu, control trode thus causes a voltage variation on the drain electrode: A UD = A UDmax xAuG Cu,
CU représentant la capacité de chevauchement entre l'électro- CU representing the capacity of overlap between the electro-
de de commande et la région drain, et CK la capacité totale -2 of control and the drain region, and CK the total capacity -2
du drain y compris Cu.of the drain including Cu.
Si l'on considère le cas o le potentiel de la grille saute de sa valeur "la plus positive" à sa valeur "la plus négative",le potentiel de drain du transistor à canal n sautera de 0 à - D à cause de cette division de tension capacitive. Puisque l'îlot p, quand il est à l'état de repos, est relié à la masse, il en résulte une différence de potentiel entre l'îlot et le drain qui, selon un certain calcul, peut être d'environ 2 V. La région drain devient négative par rapport à l'îlot et commence à consommer un courant direct quand UD > 0,7 V, c'est-à-dire supérieur à la tension de seuil de la jonction pn du drain. Quand cela est le cas, un courant direct circule à travers cette jonction pn et, comme on le sait bien, entaine une injection de porteurs de charge du côté à plus grande résistivité, c'est-à-dire dans la partie de l'îlot p adjacente à la jonction pn. Puisqu'au voisinage de cette jonction on trouve la jonction pn polarisée en sens inverse entre l'îlot et le substrat, cette dernière joue le rôle d'une jonction collectrice pour les électrons injectés par la région drain dans l'îlot de type p. A une vitesse d'injection suffisamment forte, la jonction pn entre l'îlot et le substrat perd son effet de barrière et provoque ainsi la commutation à travers la structure à quatre couches transistor canal n/îlot p/substrat n/transistor canal p, ce If we consider the case where the potential of the gate jumps from its "most positive" value to its "most negative" value, the drain potential of the n-channel transistor will jump from 0 to -D because of this capacitive voltage division. Since the island p, when in the idle state, is connected to ground, the result is a potential difference between the island and the drain which, according to a certain calculation, may be about 2 V The drain region becomes negative with respect to the island and begins to consume a direct current when UD> 0.7 V, that is to say greater than the threshold voltage of the pn junction of the drain. When this is the case, a direct current flows through this pn junction and, as is well known, entails an injection of charge carriers on the higher resistivity side, that is to say in the part of the island p adjacent to the pn junction. Since in the vicinity of this junction there is the reverse-polarized pn junction between the island and the substrate, the latter plays the role of a collector junction for the electrons injected by the drain region into the p-type island. At a sufficiently high injection speed, the pn junction between the island and the substrate loses its barrier effect and thus causes the switching through the four-channel transistor structure n / island transistor p / n-substrate / p-channel transistor, this
qu'on désigne généralement sous le nom d"'effet thyristor". usually referred to as the "thyristor effect".
La reconnaissance de cet effet est le point de départ de la présente invention. pour permettre à l'effet thyristor de s'établir, il est nécessaire de satisfaire à la condition suivante: Recognition of this effect is the starting point of the present invention. to allow the thyristor effect to be established, it is necessary to satisfy the following condition:
AU0> 0,7 VAU0> 0.7 V
en pratique, UD n'atteindra pas tout à fait sa valeur théorique maximale UDmax =AVG x Cu la différence potentiel résultante entre la région drain et la région source du transistor à effet de champ à canal n commençant immédiatement à se compenser par la circulation du courant à travers le transistor qui est encore dans l'état conducteur, les parties "source" et "drain" étant interverties en raison des conditions de potentiel durant in practice, UD will not quite reach its maximum theoretical value UDmax = AVG x Cu the resulting potential difference between the drain region and the source region of the n-channel field effect transistor immediately starting to compensate for itself by the flow of the current through the transistor which is still in the conducting state, the "source" and "drain" portions being inverted due to potential conditions during
cette phase de compensation.this phase of compensation.
3 - 24620253 - 2462025
Quand/\UD n'a pas excédé durant cette Phase la valeur critique nécessaire à l'amorçage de l'effet thyristor, c'est-à-dire: AU7V l'effet thyristor ne se produit pas et la commutation s'opère normalement: le transistor à canal p est rendu conducteur, When / \ UD did not exceed during this Phase the critical value necessary for the priming of the thyristor effect, ie: AU7V the thyristor effect does not occur and the switching normally takes place : the p-channel transistor is made conductive,
le transistor à canal n est rendu non-conducteur et le poten- the n-channel transistor is rendered non-conductive and the potential
tiel de drain (à la sortie de l'inverseur), atteint la valeur "la plus positive" UB* Evidemment, l'effet thyristor peut également être supprimé, soit en ralentissant la commande et en appliquant des impulsions de tension à fronts moins raides aux électrodes de commande, soit par une conception extrêmement résistante de l'étage de commande (faible rapport largeur sur longueur de canal), soit par extension de la capacité C K obtenue, nar exemple, en agrandissant les surfaces des régions drains drain of the drain (at the output of the inverter), reaches the value "most positive" UB * Obviously, the thyristor effect can also be suppressed, either by slowing down the control and by applying voltage pulses with less steep fronts to the control electrodes, either by an extremely robust design of the control stage (low width to channel length ratio), or by extension of the capacitance CK obtained, for example, by enlarging the surfaces of the drains
diffusées ou en réduisant l'effet d'injection région drain- diffused or reducing the effect of injection region drain-
îlot-substrat, bien que ceci ne soit pas sans présenter quelque difficulté ni sans entraîner certains inconvénients, island-substrate, although this is not without presenting some difficulty or without causing certain disadvantages,
tels qu'une diminution de la vitesse de commutation. such as a decrease in the switching speed.
L'objet de l'invention est donc de fournir un circuit intégré monolithique CMOS dans lequel l'effet thyristor non désiré dont il est fait mention ci-dessus soit évité,de façonà The object of the invention is therefore to provide a CMOS monolithic integrated circuit in which the undesired thyristor effect mentioned above is avoided, so that
empêcher que le dispositif ne soit détruit par-des impulsions. prevent the device from being destroyed by pulses.
Dans le cas d'un circuit intégré monolithique CMOS fabriqué dans un substrat en silicium,l'invention consiste à utiliser un contact à barrière de Schottky, par exemple en Al-Si, qui empêche le potentiel de la région drain de descendre en-dessous du potentiel de l'îlot p d'une quantité supérieure à la tension de seuil de Schottky. Toutefois, il est également possible d'utiliser d'autres métaux pour établir le contact à barrière de Schottky comme l'expliquent, par exemple, les journaux techniques "Solid-State Electronics" Vol. 14 (1971) p. 71 à 75 et "IEEE Transactions on Electron Devices" Vol. ED-16 N0 1 (Jan. 1969) p. 58 à 63. De cette manière il est garanti que la tension de seuil (tension de seuil dans le sens direct) du contact à barrière de Schottky In the case of a CMOS monolithic integrated circuit manufactured in a silicon substrate, the invention consists in using a Schottky barrier contact, for example Al-Si, which prevents the potential of the drain region from falling below the potential of the island p of a quantity greater than the Schottky threshold voltage. However, it is also possible to use other metals to establish Schottky barrier contact as explained, for example, in the "Solid-State Electronics" technical journals Vol. 14 (1971) p. 71 to 75 and "IEEE Transactions on Electron Devices" Vol. ED-16 No. 1 (Jan. 1969) p. 58 to 63. In this way it is ensured that the threshold voltage (threshold voltage in the forward direction) of the Schottky barrier contact
reste en-dessous de celle de la jonction pn. remains below that of the pn junction.
La tension de seuil de Schottky étant, par consé- The threshold voltage of Schottky being, therefore,
quent, inférieure à celle de la jonction pn de la région drain, le courant, sans porteurs minoritaires, s'écoulant à travers le contact à barrière de Schottky, va entraîner une décharge du côté drain, ce qui va empêcher une circulation de courant direct avec injection à travers la jonction pn de la less than that of the pn junction of the drain region, the current, without minority carriers, flowing through the Schottky barrier contact, will cause a discharge on the drain side, which will prevent a direct current flow with injection through the pn junction of the
région drain.drain area.
Par analogie, et selon une autre caractéristique du circuit intégré monolithique CMOS de la présente invention, il est également possible de fournir un contact à barrière de Schottky entre la région drain du transistor à canal p et le substrat. Dans la plupart des cas, cependant, un seul contact à barrière de Schottky du côté du transistor à effet de champ à canal n sera suffisant, car dans ce cas le danger d'une injection dans la jonction pn entre l'îlot et la région drain est plus grand (y plus élevé}, que s'il devait partir de la région drain du transistor à effet de champ à canal p. L'invention sera mieux comprise à la lecture de la By analogy, and according to another characteristic of the CMOS monolithic integrated circuit of the present invention, it is also possible to provide a Schottky barrier contact between the drain region of the p-channel transistor and the substrate. In most cases, however, only one Schottky barrier contact on the n-channel field effect transistor side will be sufficient, since in this case the danger of an injection into the pn junction between the island and the region drain is larger (y higher), than if it were to leave the drain region of the p-channel field effect transistor The invention will be better understood on reading the
description détaillée qui va suivre, faite à titre d'exemple following detailed description, given as an example
non limitatif en se reportant aux figures annexées 1 à 4, qui représentent: - Fig. 1: une vue partielle en coupe verticale d'un circuit intégré monolithique inverseur CMOS de type classique; non-limiting with reference to the appended figures 1 to 4, which represent: FIG. 1: a partial vertical sectional view of a conventional monolithic CMOS inverter integrated circuit;
- Fig. 2a à 2c: trois schémas de circuits équiva- - Fig. 2a to 2c: three equivalent circuit diagrams
lents concernant le trajet du courant entre les points aux potentiels O et VB à travers l'îlot et le substrat; slow in the current path between the points at the O and VB potentials across the island and the substrate;
- Fig. 3: une réalisation du circuit intégré mono- - Fig. 3: an embodiment of the mono-integrated circuit
lithique inverseur CMOS,conforme à l'invention, comportant deux contacts à barrière de Schottky et - Fig. 4a et b: deux schémas de circuits équivalents concernant respectivement l'utilisation d'une diode à barrière de Schottky sur l'îlot dopé de type p et sur le substrat de CMOS inverter lithic, according to the invention, comprising two Schottky barrier contacts and FIG. 4a and b: two equivalent circuit diagrams respectively concerning the use of a Schottky barrier diode on the p-type doped island and on the substrate of
type n.type n.
La fig. 1, en coupe verticale, représente un circuit intégré monolithique CMOS du type classique, connecté comme un inverseur. Pour former un transistor à effet de champ à canal n, on a ménagé un îlot semiconducteur 2 de type p dans un substrat 1 de type n. Ceci peut être réaliséde la manière Fig. 1, in vertical section, represents a monolithic CMOS integrated circuit of the conventional type, connected as an inverter. To form an n-channel field effect transistor, a p-type semiconductor island 2 has been formed in an n-type substrate 1. This can be realized in the way
classique par utilisation d'un procédé de diffusion planar. conventional using a planar diffusion method.
Dans cet îlot 2 se trouvent la région drain 5 et la région source 10, alors qu'à côté de l'îlot 2 (à gauche sur la figure), qui forme une jonction pn 7 avec le substrat 1, la région drain 6 et la région source 9 du transistor à effet de In this island 2 are the drain region 5 and the source region 10, while next to the island 2 (left in the figure), which forms a pn junction 7 with the substrate 1, the drain region 6 and the source region 9 of the solid-state transistor
-5 - 2462025-5 - 2462025
champ à canal o ont été Produites par diffusion olanar. Le signal d'entrée est appliqué en U à la connexion galvanique o-channel field were produced by olanar scattering. The input signal is applied in U to the galvanic connection
existant entre les deux électrodes de commande 11 et 12. L'ali- existing between the two control electrodes 11 and 12.
mentation UB>0 est appliquée au substrat et à la région source 9 d'un côté, et,de l'autre côté,l'îlot 2 est mis au UB> 0 is applied to the substrate and the source region 9 on one side, and on the other side, the island 2 is set to
potentiel zéro.zero potential.
Les fig. 2a à 2c représentent trois schémas de circuits équivalents pour la fig. 1, comprenant les trois diodes pn entres les régions respectives 9, 1, 2 et 10, dont les références numériques sont attribuées aux connexions existant entre les diodes pn. La fig. 2a concerne le cas idéal o O<UD <UB avec au moins - 0,7-eUDZB + 0,7 V. La fig. 2b concerne le cas o l'effet thyristor est Figs. 2a to 2c show three equivalent circuit diagrams for FIG. 1, comprising the three pn diodes between the respective regions 9, 1, 2 and 10, whose numerical references are attributed to the connections existing between the pn diodes. Fig. 2a relates to the ideal case where <UD <UB with at least - 0.7-eUDZB + 0.7 V. FIG. 2b concerns the case where the thyristor effect is
"amorcé" par le transistor npn parasite, l'amorçage s'effec- "primed" by the parasitic npn transistor, the priming
tuant à travers la région drain 5, qui, pour ainsi dire, doit être considérée comme une région émettrice auxiliaire d'un thyristor présentant la succession de régions suivantes: killing through the drain region 5, which, so to speak, should be considered as an auxiliary emitting region of a thyristor having the following succession of regions:
région source 10/1lot 2/substrat 1/région source 9. Par consé- source region 10 / 1lot 2 / substrate 1 / source region 9. As a result,
quent, la région drain 5 doit être considérée comme la zone émettrice d'un transistor parasite équivalent Tl auquel on quent, the drain region 5 must be considered as the emitting zone of an equivalent parasitic transistor Tl which is
applique pendant un certain temps une tensionUD = &UD<- 0,7V. applies for a certain time a voltage UD = & UD <- 0.7V.
La fig. 2c concerne le cas o un thyristor est amorcé par un transistor parasite pnp T2 utilisant la région Fig. 2c relates to the case where a thyristor is initiated by a parasitic transistor pnp T2 using the region
drain 6 comme-région émettrice. On lui applique, pour l'amor- drain 6 as-emitting region. It is applied, for the amor-
çage, la tension UD = UB +y\UD>UB + 0,7 V à condition que, comme d'habitude, on utilise du silicium comme matériau semi-conducteur. La fig. 3 est une vue en coupe correspondant à la fig. 1, qui représente un circuit intégré monolithique CMOS selon l'invention qui utilise un contact à barrière de Schottky 3 ou 4 connecté à la région drain 5 du transistor à effet de champ à canal n ou à la région drain 6 du transistor à effet de champ à canal p, respectivement. Dans la plupart des cas, cependant, on peut omettre le contact à barrière de Schottky 4 sur le substrat 2, parce que normalement la région drain 5 du transistor à effet de champ à canal n se trouvera beaucoup plus proche de la jonction pn 7 - qui agit comme jonction collectrice du thyristor mentionné plus haut, c'est-à-dire entre l'îlot 2 et le substrat 1 - que la région drain 6 du transistor à effet de champ à canal p. -6- the voltage UD = UB + y \ UD> UB + 0.7 V provided that, as usual, silicon is used as the semiconductor material. Fig. 3 is a sectional view corresponding to FIG. 1, which represents a monolithic CMOS integrated circuit according to the invention which uses a Schottky barrier contact 3 or 4 connected to the drain region 5 of the n-channel field effect transistor or to the drain region 6 of the p-channel field, respectively. In most cases, however, it is possible to omit the Schottky barrier contact 4 on the substrate 2, because normally the drain region 5 of the n-channel field effect transistor will be much closer to the pn junction 7. which acts as a collector junction of the thyristor mentioned above, that is to say between the island 2 and the substrate 1 - that the drain region 6 of the p-channel field effect transistor. -6-
La fig. 4a représente le schéma de circuit équiva- Fig. 4a represents the equivalent circuit diagram
lent concernant le contact à barrière de Schottky 3 sur l'ilot 2, avec un transistor parasite Tl et la région drain 5 constituant son émetteur, alors que la fig. 4b représente le schéma de circuit équivalent concernant le cas o le contact à barrière de Schottky 4 est disposé sur le substrat 1 avec slow on the Schottky barrier contact 3 on the island 2, with a parasitic transistor T1 and the drain region 5 constituting its emitter, while FIG. 4b represents the equivalent circuit diagram concerning the case where the Schottky barrier contact 4 is disposed on the substrate 1 with
le transistor T2, respectivement.the transistor T2, respectively.
Il est bien évident que la description qui précède It is obvious that the foregoing description
n'a été faitequ'à titre d'exemple non limitatif et-que d'autres variantes peuvent être envisagées sans sortir pour has been made only as a non-limitative example and that other variants can be envisaged without going out for
autant du cadre de l'invention.as much of the scope of the invention.
- 7 -- 7 -
Claims (2)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2929869A DE2929869C2 (en) | 1979-07-24 | 1979-07-24 | Monolithic integrated CMOS inverter circuitry |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2462025A1 true FR2462025A1 (en) | 1981-02-06 |
FR2462025B1 FR2462025B1 (en) | 1983-11-18 |
Family
ID=6076567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8016206A Granted FR2462025A1 (en) | 1979-07-24 | 1980-07-23 | MONOLITHIC INTEGRATED CIRCUIT WITH COMPLEMENTARY MOS TRANSISTORS |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5618459A (en) |
DE (1) | DE2929869C2 (en) |
FR (1) | FR2462025A1 (en) |
GB (1) | GB2054955B (en) |
IE (1) | IE50350B1 (en) |
IT (1) | IT1193544B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57177554A (en) * | 1981-04-27 | 1982-11-01 | Hitachi Ltd | Semiconductor integrated circuit device |
EP0166386A3 (en) * | 1984-06-29 | 1987-08-05 | Siemens Aktiengesellschaft | Integrated circuit of the complementary circuit technique |
EP0213425B1 (en) * | 1985-08-26 | 1992-05-06 | Siemens Aktiengesellschaft | Complementary integrated circuit with a substrate bias voltage generator and a schottky diode |
US9853643B2 (en) | 2008-12-23 | 2017-12-26 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
US8476689B2 (en) | 2008-12-23 | 2013-07-02 | Augustine Wei-Chun Chang | Super CMOS devices on a microelectronics system |
US11955476B2 (en) | 2008-12-23 | 2024-04-09 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
US11342916B2 (en) | 2008-12-23 | 2022-05-24 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
EP3216051A4 (en) * | 2014-10-10 | 2018-06-06 | Schottky Lsi, Inc. | SUPER CMOS (SCMOStm) DEVICES ON A MICROELECTRONIC SYSTEM |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2106614A1 (en) * | 1970-09-18 | 1972-05-05 | Rca Corp |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS568501B2 (en) * | 1973-05-12 | 1981-02-24 | ||
JPS5211885A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
JPS6043666B2 (en) * | 1976-10-18 | 1985-09-30 | 株式会社日立製作所 | Complementary MIS semiconductor device |
JPS53105985A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Conmplementary-type insulating gate field effect transistor |
-
1979
- 1979-07-24 DE DE2929869A patent/DE2929869C2/en not_active Expired
-
1980
- 1980-06-19 GB GB8020110A patent/GB2054955B/en not_active Expired
- 1980-07-18 JP JP9860980A patent/JPS5618459A/en active Pending
- 1980-07-23 IE IE1530/80A patent/IE50350B1/en unknown
- 1980-07-23 FR FR8016206A patent/FR2462025A1/en active Granted
- 1980-07-23 IT IT23632/80A patent/IT1193544B/en active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2106614A1 (en) * | 1970-09-18 | 1972-05-05 | Rca Corp |
Non-Patent Citations (1)
Title |
---|
EXBK/78 * |
Also Published As
Publication number | Publication date |
---|---|
FR2462025B1 (en) | 1983-11-18 |
DE2929869A1 (en) | 1981-02-19 |
IT8023632A0 (en) | 1980-07-23 |
IE50350B1 (en) | 1986-04-02 |
GB2054955A (en) | 1981-02-18 |
GB2054955B (en) | 1983-05-11 |
JPS5618459A (en) | 1981-02-21 |
IE801530L (en) | 1981-01-24 |
DE2929869C2 (en) | 1986-04-30 |
IT8023632A1 (en) | 1982-01-23 |
IT1193544B (en) | 1988-07-08 |
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