FR2462025A1 - MONOLITHIC INTEGRATED CIRCUIT WITH COMPLEMENTARY MOS TRANSISTORS - Google Patents

Abstract

THE INVENTION CONCERNS AN INTEGRATED CMOS CIRCUIT WITH AN INVERSE POLARIZED PN JUNCTION INSULATION, THE CHANNEL TRANSISTOR N 5, 10 BEING FOR EXAMPLE DIFFUSED IN A TYPE P 2 INSULATION BOX CREATED IN THE SUBSTRATE OR THE EPITAXIAL LAYER N 1 A SIDE OF THE P 6, 9 CHANNEL TRANSISTOR AND, MORE PARTICULARLY, MEANS OF PROTECTION AGAINST THE PRIMING OF A PARASITE THYRISTOR BETWEEN THE TWO TRANSISTORS CONNECTED AS A BASIC INVERTER. THESE MEANS INCLUDE AT LEAST ONE SCHOTTKY BARRIER CONTACT 3 BETWEEN THE P-BOX AND THE DRAIN CONNECTION CONDUCTOR, THIS CONTACT HAVING A THRESHOLD VOLTAGE LOWER THAN THAT OF JUNCTION 5-2 SO THAT DRAIN 5 CANNOT ACT IN AUXILIARY TRANSMITTER TRIGGERING AN AVALANCHE CONDUCTION THROUGH THE FOUR LAYERS 9-1-2-10 UNDER THE INFLUENCE OF A SHARP LOWERING OF THE DRAIN POTENTIAL DUE, FOR EXAMPLE, TO THE CAPACITIVE GRID-DRAIN COUPLING OF THE TRANSISTOR TO CHANNEL N. A INJECTION OF HOLES THROUGH DRAIN 6 IS LESS LIKELY BUT IT MAY ALSO BE AVOIDED BY A SECOND CONTACT AT SCHOTTKY BARRIER 4 PARALLEL TO JUNCTION 6-1.

Description

The present invention relates to a monolithic integrated circuit

  including a pair of insulated gate field effect transistors with complementary conductivity types, or CMOS inverter. In the simplest CMOS inverter, a transistor of a first conductivity type is conventionally formed by diffusion of source and drain regions on the surface of a conductivity type substrate.

  opposite and the source and drain regions of the complementary transistor

  are located in an island of the first type of

  previously scattered on the surface of the substrate. The input signal controls the two transistors whose drains are connected by a galvanic connection on which is taken the

  output of the inverter and whose sources are connected

  respectively at the poles of the power source, as explained, for example, in the German technical journal

  "Elektronic", (1971) No. 4, p. 111 to 116.

  It has been noted that if a monolithic integrated circuit

  such CMOS-type receives voltage pulses or very steep-edge spurious pulses, it may result in a short circuit across the monolithicCMOS integrated circuit,

  which is likely to lead to its destruction. The phenomenon

  is mainly observed in CMOS circuits comprising aluminum control electrodes having a high threshold voltage, and which are intended to operate at voltages

high power supply.

  It was recognized that this was due to the capacitances formed by overlapping control electrodes and drain regions. In fact, in the case of the CMOS inverter, the

  control electrodes and the drain electrodes of the transistors

  The n-channel and p-channel tors are interconnected by aluminous conductive patterns obtained by evaporation. So,

  during the switching process, part of the variation

  Voltage on the control electrode is transferred by the overlap capacitance of the control electrode,

  to the drain region of the transistors.

  A voltage step of infinite slope VG at the elec-

  control trode thus causes a voltage variation on the drain electrode: A UD = A UDmax xAuG Cu,

  CU representing the capacity of overlap between the electro-

  of control and the drain region, and CK the total capacity -2

of the drain including Cu.

  If we consider the case where the potential of the gate jumps from its "most positive" value to its "most negative" value, the drain potential of the n-channel transistor will jump from 0 to -D because of this capacitive voltage division. Since the island p, when in the idle state, is connected to ground, the result is a potential difference between the island and the drain which, according to a certain calculation, may be about 2 V The drain region becomes negative with respect to the island and begins to consume a direct current when UD> 0.7 V, that is to say greater than the threshold voltage of the pn junction of the drain. When this is the case, a direct current flows through this pn junction and, as is well known, entails an injection of charge carriers on the higher resistivity side, that is to say in the part of the island p adjacent to the pn junction. Since in the vicinity of this junction there is the reverse-polarized pn junction between the island and the substrate, the latter plays the role of a collector junction for the electrons injected by the drain region into the p-type island. At a sufficiently high injection speed, the pn junction between the island and the substrate loses its barrier effect and thus causes the switching through the four-channel transistor structure n / island transistor p / n-substrate / p-channel transistor, this

  usually referred to as the "thyristor effect".

  Recognition of this effect is the starting point of the present invention. to allow the thyristor effect to be established, it is necessary to satisfy the following condition:

AU0> 0.7 V

  in practice, UD will not quite reach its maximum theoretical value UDmax = AVG x Cu the resulting potential difference between the drain region and the source region of the n-channel field effect transistor immediately starting to compensate for itself by the flow of the current through the transistor which is still in the conducting state, the "source" and "drain" portions being inverted due to potential conditions during

this phase of compensation.

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  When / \ UD did not exceed during this Phase the critical value necessary for the priming of the thyristor effect, ie: AU7V the thyristor effect does not occur and the switching normally takes place : the p-channel transistor is made conductive,

  the n-channel transistor is rendered non-conductive and the potential

  drain of the drain (at the output of the inverter), reaches the value "most positive" UB * Obviously, the thyristor effect can also be suppressed, either by slowing down the control and by applying voltage pulses with less steep fronts to the control electrodes, either by an extremely robust design of the control stage (low width to channel length ratio), or by extension of the capacitance CK obtained, for example, by enlarging the surfaces of the drains

  diffused or reducing the effect of injection region drain-

  island-substrate, although this is not without presenting some difficulty or without causing certain disadvantages,

  such as a decrease in the switching speed.

  The object of the invention is therefore to provide a CMOS monolithic integrated circuit in which the undesired thyristor effect mentioned above is avoided, so that

  prevent the device from being destroyed by pulses.

  In the case of a CMOS monolithic integrated circuit manufactured in a silicon substrate, the invention consists in using a Schottky barrier contact, for example Al-Si, which prevents the potential of the drain region from falling below the potential of the island p of a quantity greater than the Schottky threshold voltage. However, it is also possible to use other metals to establish Schottky barrier contact as explained, for example, in the "Solid-State Electronics" technical journals Vol. 14 (1971) p. 71 to 75 and "IEEE Transactions on Electron Devices" Vol. ED-16 No. 1 (Jan. 1969) p. 58 to 63. In this way it is ensured that the threshold voltage (threshold voltage in the forward direction) of the Schottky barrier contact

  remains below that of the pn junction.

  The threshold voltage of Schottky being, therefore,

  less than that of the pn junction of the drain region, the current, without minority carriers, flowing through the Schottky barrier contact, will cause a discharge on the drain side, which will prevent a direct current flow with injection through the pn junction of the

drain area.

  By analogy, and according to another characteristic of the CMOS monolithic integrated circuit of the present invention, it is also possible to provide a Schottky barrier contact between the drain region of the p-channel transistor and the substrate. In most cases, however, only one Schottky barrier contact on the n-channel field effect transistor side will be sufficient, since in this case the danger of an injection into the pn junction between the island and the region drain is larger (y higher), than if it were to leave the drain region of the p-channel field effect transistor The invention will be better understood on reading the

  following detailed description, given as an example

  non-limiting with reference to the appended figures 1 to 4, which represent: FIG. 1: a partial vertical sectional view of a conventional monolithic CMOS inverter integrated circuit;

  - Fig. 2a to 2c: three equivalent circuit diagrams

  slow in the current path between the points at the O and VB potentials across the island and the substrate;

  - Fig. 3: an embodiment of the mono-integrated circuit

  CMOS inverter lithic, according to the invention, comprising two Schottky barrier contacts and FIG. 4a and b: two equivalent circuit diagrams respectively concerning the use of a Schottky barrier diode on the p-type doped island and on the substrate of

type n.

  Fig. 1, in vertical section, represents a monolithic CMOS integrated circuit of the conventional type, connected as an inverter. To form an n-channel field effect transistor, a p-type semiconductor island 2 has been formed in an n-type substrate 1. This can be realized in the way

  conventional using a planar diffusion method.

  In this island 2 are the drain region 5 and the source region 10, while next to the island 2 (left in the figure), which forms a pn junction 7 with the substrate 1, the drain region 6 and the source region 9 of the solid-state transistor

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  o-channel field were produced by olanar scattering. The input signal is applied in U to the galvanic connection

  existing between the two control electrodes 11 and 12.

  UB> 0 is applied to the substrate and the source region 9 on one side, and on the other side, the island 2 is set to

zero potential.

  Figs. 2a to 2c show three equivalent circuit diagrams for FIG. 1, comprising the three pn diodes between the respective regions 9, 1, 2 and 10, whose numerical references are attributed to the connections existing between the pn diodes. Fig. 2a relates to the ideal case where <UD <UB with at least - 0.7-eUDZB + 0.7 V. FIG. 2b concerns the case where the thyristor effect is

  "primed" by the parasitic npn transistor, the priming

  killing through the drain region 5, which, so to speak, should be considered as an auxiliary emitting region of a thyristor having the following succession of regions:

  source region 10 / 1lot 2 / substrate 1 / source region 9. As a result,

  quent, the drain region 5 must be considered as the emitting zone of an equivalent parasitic transistor Tl which is

  applies for a certain time a voltage UD = & UD <- 0.7V.

  Fig. 2c relates to the case where a thyristor is initiated by a parasitic transistor pnp T2 using the region

  drain 6 as-emitting region. It is applied, for the amor-

  the voltage UD = UB + y \ UD> UB + 0.7 V provided that, as usual, silicon is used as the semiconductor material. Fig. 3 is a sectional view corresponding to FIG. 1, which represents a monolithic CMOS integrated circuit according to the invention which uses a Schottky barrier contact 3 or 4 connected to the drain region 5 of the n-channel field effect transistor or to the drain region 6 of the p-channel field, respectively. In most cases, however, it is possible to omit the Schottky barrier contact 4 on the substrate 2, because normally the drain region 5 of the n-channel field effect transistor will be much closer to the pn junction 7. which acts as a collector junction of the thyristor mentioned above, that is to say between the island 2 and the substrate 1 - that the drain region 6 of the p-channel field effect transistor. -6-

  Fig. 4a represents the equivalent circuit diagram

  slow on the Schottky barrier contact 3 on the island 2, with a parasitic transistor T1 and the drain region 5 constituting its emitter, while FIG. 4b represents the equivalent circuit diagram concerning the case where the Schottky barrier contact 4 is disposed on the substrate 1 with

the transistor T2, respectively.

  It is obvious that the foregoing description

  has been made only as a non-limitative example and that other variants can be envisaged without going out for

as much of the scope of the invention.

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Claims (2)

  A monolithic integrated circuit including a pair of insulated gate field effect transistors having complementary conductivity types (CMOS circuit), wherein the source region and the drain region of one of said field effect transistors a first type of conductivity is inserted on the surface of a substrate of the other type of conductivity, the source and drain regions of the complementary type field effect transistor are arranged on the surface of an island of the first type formed the surface of the substrate, the control electrodes of the two transistors are connected by a galvanic connection transmitting the signal   input and the regions of the two transistors are also   connected by a galvanic connection, characterized in that the island is connected to a Schottky barrier contact whose threshold voltage is lower than that of the pn junction between said island and the drain region of the field effect transistor arranged on said island and said Schottky barrier contact is connected to the galvanic connection   between the two drains.   2. CMOS monolithic integrated circuit according to claim 1, characterized in that the substrate is connected to another Schottky barrier contact whose threshold voltage is lower than that of the pn junction between the drain region of the effect transistor. field disposed on the substrate and said substrate, and said other Schottky barrier contact is connected to the galvanic connection   between the two drains.