FR2406303A2 - Procede pour fabriquer une cellule de memoire a un transistor - Google Patents

Procede pour fabriquer une cellule de memoire a un transistor

Info

Publication number
FR2406303A2
FR2406303A2 FR7824156A FR7824156A FR2406303A2 FR 2406303 A2 FR2406303 A2 FR 2406303A2 FR 7824156 A FR7824156 A FR 7824156A FR 7824156 A FR7824156 A FR 7824156A FR 2406303 A2 FR2406303 A2 FR 2406303A2
Authority
FR
France
Prior art keywords
memory cell
transistor
procedure
manufacturing
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7824156A
Other languages
English (en)
Other versions
FR2406303B2 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2406303A2 publication Critical patent/FR2406303A2/fr
Application granted granted Critical
Publication of FR2406303B2 publication Critical patent/FR2406303B2/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/901—Capacitive junction

Abstract

L'invention concerne un, procédé pour fabriquer une cellule de mémoire à un transistor. Dans un substrat semi-conducteur H, on réalise des zones dopées U1 , U2 et un renfoncement V, avec formation de zones définitives Z1 , Z2 , moyennant l'utilisation d'un masque constitué par le masque de dopage formé de couches isolantes I 1 ,I2 et qui a servi pour la réalisation de l'une desdites zones. Application notamment à la réalisation d'éléments de mémoire du type VMOS.
FR7824156A 1977-08-23 1978-08-18 Procede pour fabriquer une cellule de memoire a un transistor Granted FR2406303A2 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772738008 DE2738008A1 (de) 1977-08-23 1977-08-23 Verfahren zum herstellen einer eintransistor-speicherzelle

Publications (2)

Publication Number Publication Date
FR2406303A2 true FR2406303A2 (fr) 1979-05-11
FR2406303B2 FR2406303B2 (fr) 1984-02-24

Family

ID=6017099

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7824156A Granted FR2406303A2 (fr) 1977-08-23 1978-08-18 Procede pour fabriquer une cellule de memoire a un transistor

Country Status (5)

Country Link
US (1) US4227297A (fr)
JP (1) JPS5445579A (fr)
DE (1) DE2738008A1 (fr)
FR (1) FR2406303A2 (fr)
GB (1) GB2003322B (fr)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268952A (en) * 1979-04-09 1981-05-26 International Business Machines Corporation Method for fabricating self-aligned high resolution non planar devices employing low resolution registration
GB2049273B (en) * 1979-05-02 1983-05-25 Philips Electronic Associated Method for short-circuting igfet source regions to a substrate
JPH0793365B2 (ja) * 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
USRE40790E1 (en) * 1992-06-23 2009-06-23 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US5753947A (en) * 1995-01-20 1998-05-19 Micron Technology, Inc. Very high-density DRAM cell structure and method for fabricating it
US5789758A (en) * 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US6420725B1 (en) 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
US5879955A (en) * 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
JP3363154B2 (ja) * 1995-06-07 2003-01-08 ミクロン テクノロジー、インコーポレイテッド 不揮発性メモリセル内のマルチステート材料と共に使用するスタック／トレンチダイオード
US5869843A (en) * 1995-06-07 1999-02-09 Micron Technology, Inc. Memory array having a multi-state element and method for forming such array or cells thereof
US5751012A (en) * 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US5831276A (en) * 1995-06-07 1998-11-03 Micron Technology, Inc. Three-dimensional container diode for use with multi-state material in a non-volatile memory cell
US5837564A (en) * 1995-11-01 1998-11-17 Micron Technology, Inc. Method for optimal crystallization to obtain high electrical performance from chalcogenides
US6653733B1 (en) 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US6025220A (en) 1996-06-18 2000-02-15 Micron Technology, Inc. Method of forming a polysilicon diode and devices incorporating such diode
US6337266B1 (en) 1996-07-22 2002-01-08 Micron Technology, Inc. Small electrode for chalcogenide memories
US5814527A (en) * 1996-07-22 1998-09-29 Micron Technology, Inc. Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories
US5789277A (en) 1996-07-22 1998-08-04 Micron Technology, Inc. Method of making chalogenide memory device
US5985698A (en) * 1996-07-22 1999-11-16 Micron Technology, Inc. Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell
US5998244A (en) * 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US5808340A (en) * 1996-09-18 1998-09-15 Advanced Micro Devices, Inc. Short channel self aligned VMOS field effect transistor
US5812441A (en) * 1996-10-21 1998-09-22 Micron Technology, Inc. MOS diode for use in a non-volatile memory cell
US6015977A (en) 1997-01-28 2000-01-18 Micron Technology, Inc. Integrated circuit memory cell having a small active area and method of forming same
US5952671A (en) * 1997-05-09 1999-09-14 Micron Technology, Inc. Small electrode for a chalcogenide switching device and method for fabricating same
US6087689A (en) 1997-06-16 2000-07-11 Micron Technology, Inc. Memory cell having a reduced active area and a memory array incorporating the same
US6031287A (en) * 1997-06-18 2000-02-29 Micron Technology, Inc. Contact structure and memory element incorporating the same
US6440837B1 (en) 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US6563156B2 (en) * 2001-03-15 2003-05-13 Micron Technology, Inc. Memory elements and methods for making same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930300A (en) * 1973-04-04 1976-01-06 Harris Corporation Junction field effect transistor
US4065783A (en) * 1976-10-18 1977-12-27 Paul Hsiung Ouyang Self-aligned double implanted short channel V-groove MOS device

Also Published As

Publication number Publication date
GB2003322B (en) 1982-03-17
US4227297A (en) 1980-10-14
JPS5445579A (en) 1979-04-10
GB2003322A (en) 1979-03-07
FR2406303B2 (fr) 1984-02-24
DE2738008A1 (de) 1979-03-01

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