FR2399096A1 - Circuit de lecture pour des elements de memoire numeriques - Google Patents

Circuit de lecture pour des elements de memoire numeriques

Info

Publication number
FR2399096A1
FR2399096A1 FR7820292A FR7820292A FR2399096A1 FR 2399096 A1 FR2399096 A1 FR 2399096A1 FR 7820292 A FR7820292 A FR 7820292A FR 7820292 A FR7820292 A FR 7820292A FR 2399096 A1 FR2399096 A1 FR 2399096A1
Authority
FR
France
Prior art keywords
memory elements
digital memory
reading circuit
amplifier
read circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7820292A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2399096A1 publication Critical patent/FR2399096A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Amplifiers (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un circuit de lecture pour des éléments de mémoire numériques. Dans ce circuit de lecture, qui comporte des conducteurs de bits BL, BL', reliés à des conducteurs de mots WL, WL' ainsi qu'à des étages amplificateurs T1, T2; T3, T4 reliés à des commutateurs S, S', S1, S4 et à une tension d'alimentation UDD , l'entrée (par exemples a ) d'un étage amplificateur est reliée à la sortie (par exemple c) du second étage amplificateur et réciproquement, par des condensateurs respectifs C1 , C2 ).. Application notamment aux modules de mémoire intégrés.
FR7820292A 1977-07-28 1978-07-07 Circuit de lecture pour des elements de memoire numeriques Withdrawn FR2399096A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772734137 DE2734137A1 (de) 1977-07-28 1977-07-28 Leseschaltung fuer digitale speicherelemente

Publications (1)

Publication Number Publication Date
FR2399096A1 true FR2399096A1 (fr) 1979-02-23

Family

ID=6015077

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7820292A Withdrawn FR2399096A1 (fr) 1977-07-28 1978-07-07 Circuit de lecture pour des elements de memoire numeriques

Country Status (5)

Country Link
US (1) US4162539A (fr)
JP (1) JPS5425641A (fr)
DE (1) DE2734137A1 (fr)
FR (1) FR2399096A1 (fr)
GB (1) GB1573728A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547685A (en) * 1983-10-21 1985-10-15 Advanced Micro Devices, Inc. Sense amplifier circuit for semiconductor memories
DE3773286D1 (de) * 1986-07-24 1991-10-31 Siemens Ag Integrierbare bewerterschaltung.
US5332931A (en) * 1991-06-24 1994-07-26 Harris Corporation High speed differential comparator
JP2007141399A (ja) * 2005-11-21 2007-06-07 Renesas Technology Corp 半導体装置
CN111033620B (zh) * 2017-08-24 2023-11-21 株式会社半导体能源研究所 读出放大器、半导体装置及它们的工作方法以及电子设备
FR3146234A1 (fr) * 2023-02-24 2024-08-30 Universite De Montpellier Circuit de lecture comprenant un amplificateur de lecture, et dispositif mémoire correspondant.

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3354449A (en) * 1960-03-16 1967-11-21 Control Data Corp Digital to analog computer converter
GB982119A (en) * 1962-09-24 1965-02-03 Internat Systems Control Ltd Improvements in or relating to electrical apparatus
US3249748A (en) * 1962-10-30 1966-05-03 Frederick R Fluhr Generalized analog integrator
US3441913A (en) * 1966-04-12 1969-04-29 James J Pastoriza Multiple signal sampling and storage elements sequentially discharged through an operational amplifier

Also Published As

Publication number Publication date
US4162539A (en) 1979-07-24
DE2734137A1 (de) 1979-02-08
GB1573728A (en) 1980-08-28
JPS5425641A (en) 1979-02-26

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Legal Events

Date Code Title Description
ST Notification of lapse