FR2357958A1 - Dispositif de multiplication des nombres presentes en code complementaire - Google Patents

Dispositif de multiplication des nombres presentes en code complementaire

Info

Publication number
FR2357958A1
FR2357958A1 FR7720935A FR7720935A FR2357958A1 FR 2357958 A1 FR2357958 A1 FR 2357958A1 FR 7720935 A FR7720935 A FR 7720935A FR 7720935 A FR7720935 A FR 7720935A FR 2357958 A1 FR2357958 A1 FR 2357958A1
Authority
FR
France
Prior art keywords
register
storing
control unit
additional code
multiplication system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7720935A
Other languages
English (en)
Other versions
FR2357958B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GUSEV VALERY
Original Assignee
GUSEV VALERY
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GUSEV VALERY filed Critical GUSEV VALERY
Publication of FR2357958A1 publication Critical patent/FR2357958A1/fr
Application granted granted Critical
Publication of FR2357958B1 publication Critical patent/FR2357958B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Ce dispositif comporte un registre 1 stockant un multiplicateur, un registre 2 stockant un multiplicande, raccordé à une unité arithmétique 4, qui est raccordée à un registre de décalage 6. L'unité arithmétique 4 est également raccordée à une unité de commande 8 et à un registre de transfert 34, raccordé à un circuit logique << NON-ET >> 36. Celui-ci est raccordé à l'unité 4 et au registre 6 connecté au bloc de commande 8, au registre 1 qui est raccordé à l'un des registres 17 stockant le nombre predéterminé de bits du multiplicateur, et, par l'intermédiaire d'un groupe de circuits logiques << NON-ET >> 25, 26 et 27 à un autre registre 16 stockant le nombre prédéterminé de bits du multiplicateur. Les registres 16 et 17 sont raccordés à l'unité de commande 8, à laquelle est aussi raccordé le registre 1. Le dispositif comporte un compteur 11, raccordé au groupe de circuits logiques 25, 26, 27 et à l'unité de commande 8.
FR7720935A 1976-07-07 1977-07-07 Dispositif de multiplication des nombres presentes en code complementaire Granted FR2357958A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762379678A SU651341A1 (ru) 1976-07-07 1976-07-07 Устройство дл умножени

Publications (2)

Publication Number Publication Date
FR2357958A1 true FR2357958A1 (fr) 1978-02-03
FR2357958B1 FR2357958B1 (fr) 1980-03-07

Family

ID=20668226

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7720935A Granted FR2357958A1 (fr) 1976-07-07 1977-07-07 Dispositif de multiplication des nombres presentes en code complementaire

Country Status (10)

Country Link
JP (1) JPS5317043A (fr)
BG (1) BG29702A1 (fr)
DD (1) DD131420A1 (fr)
DE (1) DE2730793A1 (fr)
FR (1) FR2357958A1 (fr)
GB (1) GB1540945A (fr)
IN (1) IN147436B (fr)
PL (1) PL108592B1 (fr)
RO (1) RO80742A (fr)
SU (1) SU651341A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334284A (en) * 1979-12-31 1982-06-08 Sperry Corporation Multiplier decoding using parallel MQ register
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit

Also Published As

Publication number Publication date
SU651341A1 (ru) 1979-03-05
DD131420A1 (de) 1978-06-21
FR2357958B1 (fr) 1980-03-07
BG29702A1 (en) 1981-01-15
PL108592B1 (en) 1980-04-30
PL199449A1 (pl) 1978-03-28
IN147436B (fr) 1980-02-23
DE2730793A1 (de) 1978-01-19
RO80742B (ro) 1983-05-30
GB1540945A (en) 1979-02-21
JPS5317043A (en) 1978-02-16
RO80742A (fr) 1983-06-01

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Legal Events

Date Code Title Description
ST Notification of lapse