RO80742B - DISPOZITIV PENTRU îNMULTIREA NUMERELOR PREZENTATE îN COD COMPLEMENTAR - Google Patents

DISPOZITIV PENTRU îNMULTIREA NUMERELOR PREZENTATE îN COD COMPLEMENTAR

Info

Publication number
RO80742B
RO80742B RO90966A RO9096677A RO80742B RO 80742 B RO80742 B RO 80742B RO 90966 A RO90966 A RO 90966A RO 9096677 A RO9096677 A RO 9096677A RO 80742 B RO80742 B RO 80742B
Authority
RO
Romania
Prior art keywords
coupled
register
multiplier
input
information
Prior art date
Application number
RO90966A
Other languages
English (en)
Other versions
RO80742A (ro
Inventor
Valery Fedorovich Gusev
Nikolaevich Ivanov Gennady
Vladimir Yakovlevich Kontarev
Genrikh Isaevich Krengel
Mansur Zachirovich Shagivaleev
Vyacheslav Yakovlevich Kremlev
Jury Ivanovich Schetinin
Usmannovich Yarmukhametov Azat
Original Assignee
Valery Fedorovich Gusev
Nikolaevich Ivanov Gennady
Vladimir Yakovlevich Kontarev
Genrikh Isaevich Krengel
Mansur Zachirovich Shagivaleev
Vyacheslav Yakovlevich Kremlev
Jury Ivanovich Schetinin
Usmannovich Yarmukhametov Azat
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valery Fedorovich Gusev, Nikolaevich Ivanov Gennady, Vladimir Yakovlevich Kontarev, Genrikh Isaevich Krengel, Mansur Zachirovich Shagivaleev, Vyacheslav Yakovlevich Kremlev, Jury Ivanovich Schetinin, Usmannovich Yarmukhametov Azat filed Critical Valery Fedorovich Gusev
Publication of RO80742B publication Critical patent/RO80742B/ro
Publication of RO80742A publication Critical patent/RO80742A/ro

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Prezenta inventie se refera la un dispozitiv pentru înmultirea numerelor prezentate în cod complementar, si poate fi folosita în procesoarele calculatoarelor electronice numerice. Dispozitivul contine registre pentru pastrarea numarului rangurilor înmultitorului, a carui intrare pentru informatii este cuplata cu registrul pentru pastrarea înmultitorului, iar iesirile pentru informatii si intrarea de comanda a acestui registru este cuplata cu blocul de comanda prin acestea intrarile pentru informatii ale registrului pentru pastrarea numarului rangurilor înmultitorului dat cuplate cu iesirile grupelor elementelor logice "SI-NU" ale caror intrari sunt cuplate la registrul pentru pastrarea înmultitorului, iar intrarile de comanda ale acestora sunt cuplate cu iesirea contorului, cuplat cu alt registru pentru pastrarea numarului rangurilor înmultitorului dat, a carui intrare de comanda si iesire pentru informatii sunt cuplate la blocul de comanda si în afara de aceasta blocul mai contine un element logic "SI-NU", a carui intrare de comanda este cuplata la iesirea de comanda a blocului aritmetic, intrarea pentru informatii a sa fiind cuplata la registrul de transport, iar iesirea fiind cuplata cu o alta intrare de comanda a registrului de deplasare.
RO7790966A 1976-07-07 1977-07-07 Dispozitiv pentru inmultirea numerelor prezentate in cod complementar RO80742A (ro)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762379678A SU651341A1 (ru) 1976-07-07 1976-07-07 Устройство дл умножени

Publications (2)

Publication Number Publication Date
RO80742B true RO80742B (ro) 1983-05-30
RO80742A RO80742A (ro) 1983-06-01

Family

ID=20668226

Family Applications (1)

Application Number Title Priority Date Filing Date
RO7790966A RO80742A (ro) 1976-07-07 1977-07-07 Dispozitiv pentru inmultirea numerelor prezentate in cod complementar

Country Status (10)

Country Link
JP (1) JPS5317043A (ro)
BG (1) BG29702A1 (ro)
DD (1) DD131420A1 (ro)
DE (1) DE2730793A1 (ro)
FR (1) FR2357958A1 (ro)
GB (1) GB1540945A (ro)
IN (1) IN147436B (ro)
PL (1) PL108592B1 (ro)
RO (1) RO80742A (ro)
SU (1) SU651341A1 (ro)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334284A (en) * 1979-12-31 1982-06-08 Sperry Corporation Multiplier decoding using parallel MQ register
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit

Also Published As

Publication number Publication date
SU651341A1 (ru) 1979-03-05
DD131420A1 (de) 1978-06-21
FR2357958B1 (ro) 1980-03-07
BG29702A1 (en) 1981-01-15
PL108592B1 (en) 1980-04-30
PL199449A1 (pl) 1978-03-28
IN147436B (ro) 1980-02-23
DE2730793A1 (de) 1978-01-19
FR2357958A1 (fr) 1978-02-03
GB1540945A (en) 1979-02-21
JPS5317043A (en) 1978-02-16
RO80742A (ro) 1983-06-01

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