FR2357065A1 - Procede de fabrication permettant de minimiser les conduits entre deux regions semi-conductrices de type different - Google Patents

Procede de fabrication permettant de minimiser les conduits entre deux regions semi-conductrices de type different

Info

Publication number
FR2357065A1
FR2357065A1 FR7717613A FR7717613A FR2357065A1 FR 2357065 A1 FR2357065 A1 FR 2357065A1 FR 7717613 A FR7717613 A FR 7717613A FR 7717613 A FR7717613 A FR 7717613A FR 2357065 A1 FR2357065 A1 FR 2357065A1
Authority
FR
France
Prior art keywords
ducts
minimize
manufacturing process
different type
semiconductor regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7717613A
Other languages
English (en)
French (fr)
Other versions
FR2357065B1 (enExample
Inventor
Klaus D Beyer
Gobinda Das
Michael R Poponiak
Tsu-Hsing Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2357065A1 publication Critical patent/FR2357065A1/fr
Application granted granted Critical
Publication of FR2357065B1 publication Critical patent/FR2357065B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/214—Recoil-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
FR7717613A 1976-07-02 1977-06-02 Procede de fabrication permettant de minimiser les conduits entre deux regions semi-conductrices de type different Granted FR2357065A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/701,789 US4069068A (en) 1976-07-02 1976-07-02 Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions

Publications (2)

Publication Number Publication Date
FR2357065A1 true FR2357065A1 (fr) 1978-01-27
FR2357065B1 FR2357065B1 (enExample) 1979-03-23

Family

ID=24818687

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7717613A Granted FR2357065A1 (fr) 1976-07-02 1977-06-02 Procede de fabrication permettant de minimiser les conduits entre deux regions semi-conductrices de type different

Country Status (7)

Country Link
US (1) US4069068A (enExample)
JP (1) JPS535965A (enExample)
CA (1) CA1090005A (enExample)
DE (1) DE2728985A1 (enExample)
FR (1) FR2357065A1 (enExample)
GB (1) GB1521879A (enExample)
IT (1) IT1114884B (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4133701A (en) * 1977-06-29 1979-01-09 General Motors Corporation Selective enhancement of phosphorus diffusion by implanting halogen ions
US4131487A (en) * 1977-10-26 1978-12-26 Western Electric Company, Inc. Gettering semiconductor wafers with a high energy laser beam
US4144099A (en) * 1977-10-31 1979-03-13 International Business Machines Corporation High performance silicon wafer and fabrication process
US4144100A (en) * 1977-12-02 1979-03-13 General Motors Corporation Method of low dose phoshorus implantation for oxide passivated diodes in <10> P-type silicon
US4170492A (en) * 1978-04-18 1979-10-09 Texas Instruments Incorporated Method of selective oxidation in manufacture of semiconductor devices
US4320312A (en) * 1978-10-02 1982-03-16 Hewlett-Packard Company Smaller memory cells and logic circuits
US4231809A (en) * 1979-05-25 1980-11-04 Bell Telephone Laboratories, Incorporated Method of removing impurity metals from semiconductor devices
JPS5617011A (en) * 1979-07-23 1981-02-18 Toshiba Corp Semiconductor device and manufacture thereof
US4249962A (en) * 1979-09-11 1981-02-10 Western Electric Company, Inc. Method of removing contaminating impurities from device areas in a semiconductor wafer
US4257827A (en) * 1979-11-13 1981-03-24 International Business Machines Corporation High efficiency gettering in silicon through localized superheated melt formation
JPS5693367A (en) * 1979-12-20 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
JPS58132922A (ja) * 1982-02-01 1983-08-08 Toshiba Corp 半導体装置の製造方法
US4569120A (en) * 1983-03-07 1986-02-11 Signetics Corporation Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation
JPS60501927A (ja) * 1983-07-25 1985-11-07 アメリカン テレフオン アンド テレグラフ カムパニ− 浅い接合の半導体デバイス
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
JPS6084813A (ja) * 1983-10-17 1985-05-14 Toshiba Corp 半導体装置の製造方法
JPS6295869A (ja) * 1985-10-22 1987-05-02 Nec Corp 半導体装置
US4837172A (en) * 1986-07-18 1989-06-06 Matsushita Electric Industrial Co., Ltd. Method for removing impurities existing in semiconductor substrate
US4796073A (en) * 1986-11-14 1989-01-03 Burr-Brown Corporation Front-surface N+ gettering techniques for reducing noise in integrated circuits
US4849365A (en) * 1988-02-16 1989-07-18 Honeywell Inc. Selective integrated circuit interconnection
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
US5840590A (en) * 1993-12-01 1998-11-24 Sandia Corporation Impurity gettering in silicon using cavities formed by helium implantation and annealing
CA2487859A1 (en) * 2002-05-29 2004-05-13 The Board Of Trustees Of The Leland Stanford Junior Unversity Solid oxide electrolyte with ion conductivity enhancement by dislocation
JP2004304099A (ja) * 2003-04-01 2004-10-28 Toshiba Corp 半導体装置
US20060220112A1 (en) * 2005-04-01 2006-10-05 International Business Machines Corporation Semiconductor device forming method and structure for retarding dopant-enhanced diffusion
US20080204068A1 (en) * 2007-02-28 2008-08-28 International Business Machines Corporation Method for estimating defects in an npn transistor array

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2191272A1 (enExample) * 1972-06-27 1974-02-01 Ibm France

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3457632A (en) * 1966-10-07 1969-07-29 Us Air Force Process for implanting buried layers in semiconductor devices
US3540925A (en) * 1967-08-02 1970-11-17 Rca Corp Ion bombardment of insulated gate semiconductor devices
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
US3663308A (en) * 1970-11-05 1972-05-16 Us Navy Method of making ion implanted dielectric enclosures
AU464038B2 (en) * 1970-12-09 1975-08-14 Philips Nv Improvements in and relating to semiconductor devices
JPS5226433B2 (enExample) * 1971-09-18 1977-07-14
US3756861A (en) * 1972-03-13 1973-09-04 Bell Telephone Labor Inc Bipolar transistors and method of manufacture
JPS5630704B2 (enExample) * 1973-05-24 1981-07-16
US3948694A (en) * 1975-04-30 1976-04-06 Motorola, Inc. Self-aligned method for integrated circuit manufacture
US4025364A (en) * 1975-08-11 1977-05-24 Fairchild Camera And Instrument Corporation Process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2191272A1 (enExample) * 1972-06-27 1974-02-01 Ibm France

Also Published As

Publication number Publication date
DE2728985A1 (de) 1978-01-05
US4069068A (en) 1978-01-17
GB1521879A (en) 1978-08-16
CA1090005A (en) 1980-11-18
IT1114884B (it) 1986-01-27
FR2357065B1 (enExample) 1979-03-23
JPS535965A (en) 1978-01-19

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Legal Events

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ST Notification of lapse