FI922351A - Persondator med lokalbussfoermedling - Google Patents

Persondator med lokalbussfoermedling Download PDF

Info

Publication number
FI922351A
FI922351A FI922351A FI922351A FI922351A FI 922351 A FI922351 A FI 922351A FI 922351 A FI922351 A FI 922351A FI 922351 A FI922351 A FI 922351A FI 922351 A FI922351 A FI 922351A
Authority
FI
Finland
Prior art keywords
bus
local processor
input
output data
coupled directly
Prior art date
Application number
FI922351A
Other languages
English (en)
Other versions
FI922351A0 (fi
Inventor
Daniel Paul Fuoco
Luis Antonio Hernandez
Eric Mathisen
Dennis Lee Moeller
Jonathan Henry Raymond
Esmaeil Tashakori
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of FI922351A0 publication Critical patent/FI922351A0/fi
Publication of FI922351A publication Critical patent/FI922351A/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Multi Processors (AREA)
FI922351A 1991-05-28 1992-05-22 Persondator med lokalbussfoermedling FI922351A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70660291A 1991-05-28 1991-05-28

Publications (2)

Publication Number Publication Date
FI922351A0 FI922351A0 (fi) 1992-05-22
FI922351A true FI922351A (fi) 1992-11-29

Family

ID=24838300

Family Applications (1)

Application Number Title Priority Date Filing Date
FI922351A FI922351A (fi) 1991-05-28 1992-05-22 Persondator med lokalbussfoermedling

Country Status (14)

Country Link
EP (1) EP0518504B1 (fi)
JP (1) JPH05101001A (fi)
KR (1) KR950008229B1 (fi)
CN (1) CN1029165C (fi)
AT (1) ATE169135T1 (fi)
AU (1) AU1519992A (fi)
CA (1) CA2064162C (fi)
DE (1) DE69226403T2 (fi)
ES (1) ES2118792T3 (fi)
FI (1) FI922351A (fi)
MX (1) MX9202526A (fi)
MY (1) MY114652A (fi)
NO (1) NO922092L (fi)
SG (1) SG46187A1 (fi)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377331A (en) * 1992-03-26 1994-12-27 International Business Machines Corporation Converting a central arbiter to a slave arbiter for interconnected systems
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5666516A (en) * 1993-12-16 1997-09-09 International Business Machines Corporation Protected programmable memory cartridge having selective access circuitry
JPH07210465A (ja) * 1993-12-30 1995-08-11 Internatl Business Mach Corp <Ibm> ペナルティのないキャッシュとメモリとのインタフェース
CN1049752C (zh) * 1994-09-16 2000-02-23 联华电子股份有限公司 可编程多重总线优先仲裁装置
JP2591502B2 (ja) * 1994-12-09 1997-03-19 日本電気株式会社 情報処理システムおよびそのバス調停方式
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
CN100356355C (zh) * 2003-08-01 2007-12-19 上海奇码数字信息有限公司 仲裁器和仲裁方法
US10223312B2 (en) 2016-10-18 2019-03-05 Analog Devices, Inc. Quality of service ordinal modification

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4470114A (en) * 1982-03-01 1984-09-04 Burroughs Corporation High speed interconnection network for a cluster of processors
EP0606102A1 (en) * 1986-09-19 1994-07-13 International Business Machines Corporation An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5083259A (en) * 1988-12-07 1992-01-21 Xycom, Inc. Computer bus interconnection device
GB9019001D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station including a direct memory access controller and interfacing means to microchannel means

Also Published As

Publication number Publication date
MX9202526A (es) 1992-11-01
JPH05101001A (ja) 1993-04-23
CA2064162A1 (en) 1992-11-29
CN1029165C (zh) 1995-06-28
SG46187A1 (en) 1998-02-20
FI922351A0 (fi) 1992-05-22
NO922092D0 (no) 1992-05-26
DE69226403D1 (de) 1998-09-03
DE69226403T2 (de) 1999-03-25
MY114652A (en) 2002-12-31
ES2118792T3 (es) 1998-10-01
KR920022112A (ko) 1992-12-19
KR950008229B1 (ko) 1995-07-26
CA2064162C (en) 2002-07-09
NO922092L (no) 1992-11-30
EP0518504A1 (en) 1992-12-16
EP0518504B1 (en) 1998-07-29
CN1067323A (zh) 1992-12-23
ATE169135T1 (de) 1998-08-15
AU1519992A (en) 1992-12-03

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