ES2118792T3 - Ordenador personal con arbitraje de una linea de transmision local. - Google Patents

Ordenador personal con arbitraje de una linea de transmision local.

Info

Publication number
ES2118792T3
ES2118792T3 ES92304511T ES92304511T ES2118792T3 ES 2118792 T3 ES2118792 T3 ES 2118792T3 ES 92304511 T ES92304511 T ES 92304511T ES 92304511 T ES92304511 T ES 92304511T ES 2118792 T3 ES2118792 T3 ES 2118792T3
Authority
ES
Spain
Prior art keywords
bus
local processor
arbitration
input
output data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92304511T
Other languages
English (en)
Inventor
Daniel Paul Fuoco
Luis Antonio Hernandez
Eric Mathisen
Dennis Lee Moeller
Jonathan Henry Raymond
Esmaeil Tashakori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2118792T3 publication Critical patent/ES2118792T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
  • Multi Processors (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)

Abstract

LA INVENCION SE REFIERE A ORDENADORES PERSONALES, Y MAS PARTICULARMENTE A LOS ORDENADORES PERSONALES EN LOS QUE SU RENDIMIENTO SE MEJORA HACIENDO POSIBLE EL ARBITRAJE DEL CONTROL SOBRE UN BUS DEL PROCESADOR LOCAL ENTRE UNA PLURALIDAD DE DISPOSITIVOS MAESTROS ACOPLADOS DIRECTAMENTE AL BUS DEL PROCESADOR LOCAL. EL SISTEMA DE ORDENADOR PERSONAL DE ACUERDO CON ESTA INVENCION TIENE UN BUS DE DATOS DEL PROCESADOR LOCAL DE ALTA VELOCIDAD; UN BUS DE DATOS DE ENTRADA / SALIDA; AL MENOS DOS DISPOSITIVOS MAESTROS ACOPLADOS DIRECTAMENTE AL BUS DEL PROCESADOR LOCAL; Y UN CONTROLADOR DE LA INTERFACE DEL BUS ACOPLADO DIRECTAMENTE AL BUS DEL PROCESADOR LOCAL Y DIRECTAMENTE AL BUS DE DATOS DE ENTRADA / SALIDA PARA PROVEER LAS COMUNICACIONES ENTRE EL BUS DEL PROCESADOR LOCAL Y EL BUS DE DATOS DE ENTRADA / SALIDA, CON EL CONTROLADOR DE LA INTERFACE DEL BUS REALIZANDO EL ARBITRAJE ENTRE LOS DISPOSITIVOS MAESTROS ACOPLADOS DIRECTAMENTE AL BUS DEL PROCESADOR LOCAL PARA ACCEDER AL BUS DEL PROCESADOR LOCAL, Y REALIZANDO EL ARBITRAJE ENTRE EL BUS DEL PROCESADOR LOCAL Y CUALQUIERA DE LOS DISPOSITIVOS ACOPLADOS DIRECTAMENTE AL BUS DE DATOS DE ENTRADA / SALIDA PARA ACCEDER AL BUS DE DATOS DE ENTRADA / SALIDA.
ES92304511T 1991-05-28 1992-05-19 Ordenador personal con arbitraje de una linea de transmision local. Expired - Lifetime ES2118792T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70660291A 1991-05-28 1991-05-28

Publications (1)

Publication Number Publication Date
ES2118792T3 true ES2118792T3 (es) 1998-10-01

Family

ID=24838300

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92304511T Expired - Lifetime ES2118792T3 (es) 1991-05-28 1992-05-19 Ordenador personal con arbitraje de una linea de transmision local.

Country Status (14)

Country Link
EP (1) EP0518504B1 (es)
JP (1) JPH05101001A (es)
KR (1) KR950008229B1 (es)
CN (1) CN1029165C (es)
AT (1) ATE169135T1 (es)
AU (1) AU1519992A (es)
CA (1) CA2064162C (es)
DE (1) DE69226403T2 (es)
ES (1) ES2118792T3 (es)
FI (1) FI922351A (es)
MX (1) MX9202526A (es)
MY (1) MY114652A (es)
NO (1) NO922092L (es)
SG (1) SG46187A1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377331A (en) * 1992-03-26 1994-12-27 International Business Machines Corporation Converting a central arbiter to a slave arbiter for interconnected systems
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5666516A (en) * 1993-12-16 1997-09-09 International Business Machines Corporation Protected programmable memory cartridge having selective access circuitry
JPH07210465A (ja) * 1993-12-30 1995-08-11 Internatl Business Mach Corp <Ibm> ペナルティのないキャッシュとメモリとのインタフェース
CN1049752C (zh) * 1994-09-16 2000-02-23 联华电子股份有限公司 可编程多重总线优先仲裁装置
JP2591502B2 (ja) * 1994-12-09 1997-03-19 日本電気株式会社 情報処理システムおよびそのバス調停方式
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
CN100356355C (zh) * 2003-08-01 2007-12-19 上海奇码数字信息有限公司 仲裁器和仲裁方法
US10223312B2 (en) 2016-10-18 2019-03-05 Analog Devices, Inc. Quality of service ordinal modification

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4470114A (en) * 1982-03-01 1984-09-04 Burroughs Corporation High speed interconnection network for a cluster of processors
EP0606102A1 (en) * 1986-09-19 1994-07-13 International Business Machines Corporation An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5083259A (en) * 1988-12-07 1992-01-21 Xycom, Inc. Computer bus interconnection device
GB9019001D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station including a direct memory access controller and interfacing means to microchannel means

Also Published As

Publication number Publication date
FI922351A0 (fi) 1992-05-22
KR920022112A (ko) 1992-12-19
KR950008229B1 (ko) 1995-07-26
CN1029165C (zh) 1995-06-28
NO922092D0 (no) 1992-05-26
JPH05101001A (ja) 1993-04-23
SG46187A1 (en) 1998-02-20
CA2064162C (en) 2002-07-09
CA2064162A1 (en) 1992-11-29
FI922351A (fi) 1992-11-29
DE69226403T2 (de) 1999-03-25
MY114652A (en) 2002-12-31
EP0518504B1 (en) 1998-07-29
CN1067323A (zh) 1992-12-23
AU1519992A (en) 1992-12-03
NO922092L (no) 1992-11-30
DE69226403D1 (de) 1998-09-03
ATE169135T1 (de) 1998-08-15
MX9202526A (es) 1992-11-01
EP0518504A1 (en) 1992-12-16

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