ES2187535T3 - Sistema de transferencia asincrona de datos y de control de trafico de origen. - Google Patents

Sistema de transferencia asincrona de datos y de control de trafico de origen.

Info

Publication number
ES2187535T3
ES2187535T3 ES94929268T ES94929268T ES2187535T3 ES 2187535 T3 ES2187535 T3 ES 2187535T3 ES 94929268 T ES94929268 T ES 94929268T ES 94929268 T ES94929268 T ES 94929268T ES 2187535 T3 ES2187535 T3 ES 2187535T3
Authority
ES
Spain
Prior art keywords
bus
field
transfer
clock
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES94929268T
Other languages
English (en)
Inventor
Daniel C Upp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Transwitch Corp
Original Assignee
Transwitch Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transwitch Corp filed Critical Transwitch Corp
Application granted granted Critical
Publication of ES2187535T3 publication Critical patent/ES2187535T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H04L12/4035—Bus networks with centralised control, e.g. polling in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5603—Access techniques
    • H04L2012/5609—Topology
    • H04L2012/5613—Bus (including DQDB)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5615—Network termination, e.g. NT1, NT2, PBX
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Abstract

UN SISTEMA DE CONTROL DE TRANSMISION DE DATOS ASINCRONOS Y DE TRAFICO FUENTE INCLUYE UN BUS MAESTRO (100) Y UNA PLURALIDAD DE USUARIOS DE BUS (112, 114, 116) ACOPLADOS A UN BUS DE DATOS BIDIRECCIONAL (120-128). EL BUS MAESTRO (100) PROPORCIONA DOS SEÑALES DE RELOJ (120, 122) A CADA USUARIO DE BUS (112, 114, 116), UN RELOJ DE SISTEMA (120) Y UN RELOJ DE TRAMA (122). EL RELOJ DE TRAMA DESIGNA EL INICIO DE UNA TRAMA. UN FORMATO DE TRAMA INCLUYE PREFERIBLEMENTE QUINCE O DIECISEIS CICLOS DE RELOJ DEL SISTEMA, EN EL PRIMERO DE LOS CUALES SE DESIGNA COMO EL CAMPO DE PETICION Y EL ULTIMO DE LOS CUALES INCLUYE UN CAMPO DE TRANSFERENCIA. A UNO O MAS CICLOS SE LES PUEDE ASIGNAR INFORMACION DE CONTROL Y/O DIRECCION Y EL RESTO DE LOS CICLOS COMPRENDE UN CAMPO DE DATOS DE LONGITUD FIJA. DURANTE EL CAMPO DE PETICION, CUALQUIER NUMERO DE USUARIOS DE BUS (112, 114, 116) PUEDE SOLICITAR ACCESO EL CUAL ES RECIBIDO POR EL BUS MAESTRO (100). DURANTE EL CAMPO DE TRANSFERENCIA, EL BUS MAESTRO (100) TRANSFIERE ACCESO A UN USUARIO DE BUS SELECCIONADO (112, 114, 116) PARA LA PORCION DE DATOS COMPLETA DE LA SIGUIENTE TRAMA. A QUE USUARIO (112, 114, 116) SE LE TRANSFIERE ACCESO A LA SIGUIENTE TRAMA ES DETERMINADO DE ACUERDO CON UN ALGORITMO DE ARBITRAJE EN EL BUS MAESTRO (100) QUE PUEDE SER DESCONOCIDO A LOS USUARIOS DE BUS (112, 114, 116). EL SISTEMA DE CONTROL TRANSFERENCIA DE DATOS ASINCRONOS Y DE CONTROL DE TRAFICO FUENTE TIENE PARTICULAR APLICACION EN ADAPTACION DE LA TRANSFERENCIA DE LOS CONTENIDOS DE CELDAS ATM UTILIZADAS EN SISTEMAS BRDSI.
ES94929268T 1993-09-20 1994-09-20 Sistema de transferencia asincrona de datos y de control de trafico de origen. Expired - Lifetime ES2187535T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12388193A 1993-09-20 1993-09-20
US21339894A 1994-03-14 1994-03-14

Publications (1)

Publication Number Publication Date
ES2187535T3 true ES2187535T3 (es) 2003-06-16

Family

ID=26822004

Family Applications (1)

Application Number Title Priority Date Filing Date
ES94929268T Expired - Lifetime ES2187535T3 (es) 1993-09-20 1994-09-20 Sistema de transferencia asincrona de datos y de control de trafico de origen.

Country Status (11)

Country Link
US (1) US5901146A (es)
EP (1) EP0724796B1 (es)
JP (1) JP3516684B2 (es)
CN (1) CN1088299C (es)
AU (1) AU7838894A (es)
CA (1) CA2170602C (es)
DE (1) DE69431846T2 (es)
DK (1) DK0724796T3 (es)
ES (1) ES2187535T3 (es)
PT (1) PT724796E (es)
WO (1) WO1995008887A1 (es)

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US6104724A (en) * 1993-09-20 2000-08-15 Transwitch Corp. Asynchronous data transfer and source traffic control system
US5729546A (en) * 1995-06-21 1998-03-17 Cisco Systems, Inc. Expandable communication cell bus for multiplexing and concentrating communication cell traffic onto high speed lines
WO1998026509A2 (en) * 1996-11-27 1998-06-18 Dsc Telecom L.P. Method and apparatus for high-speed data transfer that minimizes conductors
IT1290337B1 (it) * 1997-02-17 1998-10-22 Italtel Spa Sistema per la trasmissione di dati tra una unita' centrale e una pluralita' di unita' periferiche per il tramite di un bus sincrono ad
IT1290336B1 (it) * 1997-02-17 1998-10-22 Italtel Spa Metodo di comunicazione tra una unita' centrale e una pluralita' di unita' periferiche per il tramite di un bus sincrono ad alta velocita,
US6160653A (en) * 1997-03-26 2000-12-12 Sun Microsystems, Inc. Optical computer bus with dynamic bandwidth allocation
US6119188A (en) * 1997-05-27 2000-09-12 Fusion Micromedia Corp. Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system
GB2327579B (en) * 1997-07-22 2000-06-07 Motorola Israel Ltd Apparatus for controlling of data transportation and a method
US6480498B1 (en) * 1998-07-01 2002-11-12 National Semiconductor Corporation High speed network switch bus clock
US6535520B1 (en) * 1998-08-14 2003-03-18 Cisco Technology, Inc. System and method of operation for managing data communication between physical layer devices and ATM layer devices
US6724772B1 (en) * 1998-09-04 2004-04-20 Advanced Micro Devices, Inc. System-on-a-chip with variable bandwidth
US6639899B1 (en) * 1999-10-14 2003-10-28 Alcatel Canada Inc. Method and apparatus for providing integral cell payload integrity verification in ATM Telecommunication devices
FR2820921A1 (fr) 2001-02-14 2002-08-16 Canon Kk Dispositif et procede de transmission dans un commutateur
KR100441606B1 (ko) * 2001-10-05 2004-07-23 삼성전자주식회사 복수의 모듈들간의 데이터 송수신 시스템 및 송수신제어방법
US7313151B2 (en) * 2002-02-06 2007-12-25 Transwitch Corporation Extendible asynchronous and synchronous interface bus for broadband access
US20030206550A1 (en) * 2002-04-30 2003-11-06 Transwitch Corporation Methods and apparatus for increasing the number of UTOPIA ports in an ATM device
US7120327B2 (en) * 2002-11-27 2006-10-10 International Business Machines Corporation Backplane assembly with board to board optical interconnections
US7274657B2 (en) * 2002-12-23 2007-09-25 Transwitch Corporation Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system
US7342885B2 (en) * 2003-01-15 2008-03-11 Transwitch Corporation Method and apparatus for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system
EP1445704A1 (en) * 2003-02-06 2004-08-11 STMicroelectronics S.r.l. Synchronization method of data interchange of a communication network and corresponding circuit and architecture
US7430201B1 (en) 2003-03-21 2008-09-30 Transwitch Corporation Methods and apparatus for accessing full bandwidth in an asynchronous data transfer and source traffic control system
US7350002B2 (en) * 2004-12-09 2008-03-25 Agere Systems, Inc. Round-robin bus protocol
FR2907930B1 (fr) * 2006-10-27 2009-02-13 Viaccess Sa Procede de detection d'une utilisation anormale d'un processeur de securite.
DE502007002941D1 (de) * 2007-08-23 2010-04-08 Siemens Ag Verfahren zur Datenübertragung
CN102347877A (zh) * 2010-07-30 2012-02-08 中兴通讯股份有限公司 总线调度方法及装置
TWI490698B (zh) * 2013-05-10 2015-07-01 Integrated Circuit Solution Inc 高速資料傳輸架構
US9563590B2 (en) * 2014-03-17 2017-02-07 Nxp Usa, Inc. Devices with arbitrated interface busses, and methods of their operation
CN106874237B (zh) * 2017-03-08 2019-08-27 上海冉能自动化科技有限公司 基于二总线的数据同步方法及系统

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Also Published As

Publication number Publication date
PT724796E (pt) 2003-04-30
DE69431846D1 (de) 2003-01-16
EP0724796B1 (en) 2002-12-04
CA2170602C (en) 2004-03-23
WO1995008887A1 (en) 1995-03-30
EP0724796A1 (en) 1996-08-07
JP3516684B2 (ja) 2004-04-05
CA2170602A1 (en) 1995-03-30
CN1088299C (zh) 2002-07-24
AU7838894A (en) 1995-04-10
DK0724796T3 (da) 2003-03-31
EP0724796A4 (en) 1999-11-24
JPH09504919A (ja) 1997-05-13
DE69431846T2 (de) 2003-07-17
US5901146A (en) 1999-05-04
CN1134207A (zh) 1996-10-23

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