UY23414A1 - Computadora personal con control de reset del procesador - Google Patents
Computadora personal con control de reset del procesadorInfo
- Publication number
- UY23414A1 UY23414A1 UY23414A UY23414A UY23414A1 UY 23414 A1 UY23414 A1 UY 23414A1 UY 23414 A UY23414 A UY 23414A UY 23414 A UY23414 A UY 23414A UY 23414 A1 UY23414 A1 UY 23414A1
- Authority
- UY
- Uruguay
- Prior art keywords
- bus
- input
- local processor
- output data
- data bus
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Mobile Radio Communication Systems (AREA)
- Multi Processors (AREA)
- Debugging And Monitoring (AREA)
- Retry When Errors Occur (AREA)
- Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
- Nitrogen Condensed Heterocyclic Rings (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
El presente invento se refiere a computadoras personales en las que se proporciona la capacidad para continuar el procesamiento a través de una señal de RESET evitando al mismo tiempo fallas del sistema. El sistema de computadora personal tiene un bus de procesador de datos de alta velocidad; un bus de datos de entrada/salida; un microprocesador reseteable acoplado directamente al bus de procesador local; y un controlador de interfase de bus acoplado directamente al bus de procesador local y directamente al bus de datos de entrada/salida para proporcionar comunicaciones entre el bus de procesador loca y el bus de datos de entrada/salida. El controlador de interfase de bus proporciona arbitraje entre dispositivos acoplados directamente al bus de datos de entrada/salida para acceso al bus de datos de entrada/salida y al bus de procesador local y arbitraje entre el bus de datos de entrada /salida y el microprocesador para acceso al bus de procesador local. El controlador de interfase de bus además reconoce el recibo de una señal de reset destinada a iniciar un reset de microprocesador y difiere la emisión de una señal de reset al microprocesador hasta que el control de interfase de bus haya bloqueado el acceso al bus de procesador local y el bus de entrada/salida por cualquiera de los dispositivos que potencialmente puedan solicitar tal acceso.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US70649091A | 1991-05-28 | 1991-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UY23414A1 true UY23414A1 (es) | 1992-05-27 |
Family
ID=24837825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| UY23414A UY23414A1 (es) | 1991-05-28 | 1992-05-19 | Computadora personal con control de reset del procesador |
Country Status (18)
| Country | Link |
|---|---|
| US (1) | US5630078A (es) |
| EP (1) | EP0518502B1 (es) |
| JP (1) | JPH0752379B2 (es) |
| KR (1) | KR950005214B1 (es) |
| CN (1) | CN1030944C (es) |
| AT (1) | ATE182697T1 (es) |
| AU (1) | AU661842B2 (es) |
| BR (1) | BR9201917A (es) |
| CA (1) | CA2064163C (es) |
| DE (1) | DE69229656T2 (es) |
| EC (1) | ECSP920837A (es) |
| FI (1) | FI922349A (es) |
| MX (1) | MX9202495A (es) |
| MY (1) | MY110949A (es) |
| NO (1) | NO922090L (es) |
| SG (1) | SG43727A1 (es) |
| TW (1) | TW234178B (es) |
| UY (1) | UY23414A1 (es) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6219754B1 (en) | 1995-06-07 | 2001-04-17 | Advanced Micro Devices Inc. | Processor with decompressed video bus |
| US7562265B2 (en) * | 2004-03-23 | 2009-07-14 | International Business Machines Corporation | Method, apparatus and program storage device for providing self-quiesced logic to handle an error recovery instruction |
| KR100731208B1 (ko) | 2004-12-24 | 2007-06-20 | 한국항공우주연구원 | 로컬 버스를 이용한 통신 방법 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59168527A (ja) * | 1983-03-16 | 1984-09-22 | Sharp Corp | 電源制御方式 |
| US5007014A (en) * | 1984-01-11 | 1991-04-09 | Sharp Kabushiki Kaisha | Reset circuit for electronic apparatus |
| JPS62106524A (ja) * | 1985-11-01 | 1987-05-18 | Clarion Co Ltd | 車載用の機器のマイクロコンピユ−タリセツト回路 |
| US4787032A (en) * | 1986-09-08 | 1988-11-22 | Compaq Computer Corporation | Priority arbitration circuit for processor access |
| US5125088A (en) * | 1986-09-08 | 1992-06-23 | Compaq Computer Corporation | Computer system speed control at continuous processor speed |
| US4811200A (en) * | 1987-05-12 | 1989-03-07 | Motorola, Inc. | Multiple microprocessor watchdog system |
| JPH0289154A (ja) * | 1988-09-26 | 1990-03-29 | Toshiba Corp | 情報処理システム |
| US5170481A (en) * | 1989-06-19 | 1992-12-08 | International Business Machines Corporation | Microprocessor hold and lock circuitry |
| CA2027799A1 (en) * | 1989-11-03 | 1991-05-04 | David A. Miller | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems |
| US5148380A (en) * | 1990-08-27 | 1992-09-15 | Acer Incorporated | Method and apparatus for conserving power in a data processing system |
-
1991
- 1991-06-10 TW TW080104569A patent/TW234178B/zh active
-
1992
- 1992-03-26 CA CA002064163A patent/CA2064163C/en not_active Expired - Fee Related
- 1992-03-31 JP JP4076515A patent/JPH0752379B2/ja not_active Expired - Lifetime
- 1992-04-28 CN CN92103103A patent/CN1030944C/zh not_active Expired - Fee Related
- 1992-04-28 KR KR1019920007144A patent/KR950005214B1/ko not_active IP Right Cessation
- 1992-04-28 MY MYPI92000727A patent/MY110949A/en unknown
- 1992-04-28 AU AU15196/92A patent/AU661842B2/en not_active Ceased
- 1992-05-19 UY UY23414A patent/UY23414A1/es unknown
- 1992-05-19 SG SG1996000244A patent/SG43727A1/en unknown
- 1992-05-19 AT AT92304506T patent/ATE182697T1/de active
- 1992-05-19 DE DE69229656T patent/DE69229656T2/de not_active Expired - Fee Related
- 1992-05-19 EP EP92304506A patent/EP0518502B1/en not_active Expired - Lifetime
- 1992-05-21 BR BR929201917A patent/BR9201917A/pt not_active Application Discontinuation
- 1992-05-22 FI FI922349A patent/FI922349A/fi unknown
- 1992-05-26 NO NO92922090A patent/NO922090L/no unknown
- 1992-05-27 EC EC1992000837A patent/ECSP920837A/es unknown
- 1992-05-27 MX MX9202495A patent/MX9202495A/es not_active IP Right Cessation
-
1994
- 1994-06-20 US US08/262,397 patent/US5630078A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| BR9201917A (pt) | 1993-01-12 |
| DE69229656D1 (de) | 1999-09-02 |
| AU1519692A (en) | 1992-12-03 |
| CN1030944C (zh) | 1996-02-07 |
| FI922349A0 (fi) | 1992-05-22 |
| CA2064163A1 (en) | 1992-11-29 |
| FI922349A (fi) | 1992-11-29 |
| AU661842B2 (en) | 1995-08-10 |
| JPH05134784A (ja) | 1993-06-01 |
| CA2064163C (en) | 1998-04-14 |
| CN1067125A (zh) | 1992-12-16 |
| NO922090D0 (no) | 1992-05-26 |
| TW234178B (es) | 1994-11-11 |
| EP0518502A1 (en) | 1992-12-16 |
| JPH0752379B2 (ja) | 1995-06-05 |
| SG43727A1 (en) | 1997-11-14 |
| NO922090L (no) | 1992-11-30 |
| ECSP920837A (es) | 1993-07-29 |
| ATE182697T1 (de) | 1999-08-15 |
| MY110949A (en) | 1999-07-31 |
| US5630078A (en) | 1997-05-13 |
| KR920022077A (ko) | 1992-12-19 |
| MX9202495A (es) | 1992-11-01 |
| DE69229656T2 (de) | 2000-03-02 |
| EP0518502B1 (en) | 1999-07-28 |
| KR950005214B1 (ko) | 1995-05-22 |
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