FI20002649A - Kuvakehyksien päivittäminen muistillisessa näytössä - Google Patents

Kuvakehyksien päivittäminen muistillisessa näytössä

Info

Publication number
FI20002649A
FI20002649A FI20002649A FI20002649A FI20002649A FI 20002649 A FI20002649 A FI 20002649A FI 20002649 A FI20002649 A FI 20002649A FI 20002649 A FI20002649 A FI 20002649A FI 20002649 A FI20002649 A FI 20002649A
Authority
FI
Finland
Prior art keywords
frame
image
display
image frames
control system
Prior art date
Application number
FI20002649A
Other languages
English (en)
Swedish (sv)
Other versions
FI115802B (fi
FI20002649A0 (fi
Inventor
Mika Antila
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Publication of FI20002649A0 publication Critical patent/FI20002649A0/fi
Priority to FI20002649A priority Critical patent/FI115802B/fi
Priority to ES01000582T priority patent/ES2222942T3/es
Priority to EP01000582A priority patent/EP1217602B1/en
Priority to DE60103965T priority patent/DE60103965T2/de
Priority to AT01000582T priority patent/ATE269998T1/de
Priority to US10/005,061 priority patent/US6816163B2/en
Priority to JP2001370081A priority patent/JP4188588B2/ja
Publication of FI20002649A publication Critical patent/FI20002649A/fi
Application granted granted Critical
Publication of FI115802B publication Critical patent/FI115802B/fi
Priority to JP2008154549A priority patent/JP2008268971A/ja

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Digital Computer Display Output (AREA)
  • Processing Or Creating Images (AREA)
  • Transforming Electric Information Into Light Information (AREA)
FI20002649A 2000-12-04 2000-12-04 Kuvakehyksien päivittäminen muistillisessa näytössä FI115802B (fi)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FI20002649A FI115802B (fi) 2000-12-04 2000-12-04 Kuvakehyksien päivittäminen muistillisessa näytössä
AT01000582T ATE269998T1 (de) 2000-12-04 2001-10-31 Aktualisierung von rasterbildern in einem anzeigegerät mit einem bildspeicher
EP01000582A EP1217602B1 (en) 2000-12-04 2001-10-31 Updating image frames in a display device comprising a frame buffer
DE60103965T DE60103965T2 (de) 2000-12-04 2001-10-31 Aktualisierung von Rasterbildern in einem Anzeigegerät mit einem Bildspeicher
ES01000582T ES2222942T3 (es) 2000-12-04 2001-10-31 Actualizacion de cuadros de imagen en un dispositivo de presentacion que comprende una memoria de cuadro.
US10/005,061 US6816163B2 (en) 2000-12-04 2001-12-04 Updating image frames on a screen comprising memory
JP2001370081A JP4188588B2 (ja) 2000-12-04 2001-12-04 画面上の画像フレームを更新する方法及び表示システム
JP2008154549A JP2008268971A (ja) 2000-12-04 2008-06-12 画面上の画像フレームを更新する方法及び表示システム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20002649A FI115802B (fi) 2000-12-04 2000-12-04 Kuvakehyksien päivittäminen muistillisessa näytössä
FI20002649 2000-12-04

Publications (3)

Publication Number Publication Date
FI20002649A0 FI20002649A0 (fi) 2000-12-04
FI20002649A true FI20002649A (fi) 2002-06-05
FI115802B FI115802B (fi) 2005-07-15

Family

ID=8559633

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20002649A FI115802B (fi) 2000-12-04 2000-12-04 Kuvakehyksien päivittäminen muistillisessa näytössä

Country Status (7)

Country Link
US (1) US6816163B2 (fi)
EP (1) EP1217602B1 (fi)
JP (2) JP4188588B2 (fi)
AT (1) ATE269998T1 (fi)
DE (1) DE60103965T2 (fi)
ES (1) ES2222942T3 (fi)
FI (1) FI115802B (fi)

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ATE517500T1 (de) 2003-06-02 2011-08-15 Qualcomm Inc Erzeugung und umsetzung eines signalprotokolls und schnittstelle für höhere datenraten
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CN1902880A (zh) 2003-10-29 2007-01-24 高通股份有限公司 高数据速率接口
JP4782694B2 (ja) 2003-11-12 2011-09-28 クゥアルコム・インコーポレイテッド 改善されたリンク制御を有する高速データレートインタフェース
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EP1735986B1 (en) 2004-03-17 2013-05-22 Qualcomm, Incorporated High data rate interface apparatus and method
US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
AU2005253592B2 (en) 2004-06-04 2009-02-05 Qualcomm Incorporated High data rate interface apparatus and method
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US8667363B2 (en) 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8723705B2 (en) 2004-11-24 2014-05-13 Qualcomm Incorporated Low output skew double data rate serial encoder
EP2479920A3 (en) * 2004-11-24 2012-09-05 Qualcomm Incorporated Methods and systems for updating a buffer
US8539119B2 (en) 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
US7644309B2 (en) * 2005-05-20 2010-01-05 Nokia Corporation Recovering a hardware module from a malfunction
US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8730069B2 (en) 2005-11-23 2014-05-20 Qualcomm Incorporated Double data rate serial encoder
US8952974B2 (en) * 2006-04-20 2015-02-10 Cisco Technology, Inc. Latency reduction in a display device
US7710450B2 (en) 2006-04-20 2010-05-04 Cisco Technology, Inc. System and method for dynamic control of image capture in a video conference system
KR100777683B1 (ko) 2006-11-15 2007-11-21 (주)토마토엘에스아이 디스플레이 왜곡 방지를 위한 ｓｒａｍ을 내장한 액정 구동드라이버의 인터페이스 장치 및 그 방법
US8248387B1 (en) * 2008-02-12 2012-08-21 Microsoft Corporation Efficient buffering of data frames for multiple clients
US8947420B2 (en) 2011-05-27 2015-02-03 Nokia Corporation Processing image content for content motion or touch input
US9317892B2 (en) * 2011-12-28 2016-04-19 Intel Corporation Method and device to augment volatile memory in a graphics subsystem with non-volatile memory
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Also Published As

Publication number Publication date
ATE269998T1 (de) 2004-07-15
ES2222942T3 (es) 2005-02-16
FI115802B (fi) 2005-07-15
EP1217602A2 (en) 2002-06-26
DE60103965D1 (de) 2004-07-29
JP2002236480A (ja) 2002-08-23
EP1217602A3 (en) 2002-10-30
FI20002649A0 (fi) 2000-12-04
EP1217602B1 (en) 2004-06-23
JP2008268971A (ja) 2008-11-06
JP4188588B2 (ja) 2008-11-26
DE60103965T2 (de) 2005-07-07
US6816163B2 (en) 2004-11-09
US20020080134A1 (en) 2002-06-27

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