FI116867B - Förbindnings- och monteringsteknik för flerchipsmoduler - Google Patents

Förbindnings- och monteringsteknik för flerchipsmoduler Download PDF

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Publication number
FI116867B
FI116867B FI953174A FI953174A FI116867B FI 116867 B FI116867 B FI 116867B FI 953174 A FI953174 A FI 953174A FI 953174 A FI953174 A FI 953174A FI 116867 B FI116867 B FI 116867B
Authority
FI
Finland
Prior art keywords
layer
insulating material
dielectric
copper
patterns
Prior art date
Application number
FI953174A
Other languages
English (en)
Finnish (fi)
Other versions
FI953174A (sv
FI953174A0 (sv
Inventor
Siegfried Birkle
Tobias Noll
Hellmut Ahne
Rainer Leuschner
Albert Hammerschmidt
Recai Sezi
Ann Dumoulin
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI953174A0 publication Critical patent/FI953174A0/sv
Publication of FI953174A publication Critical patent/FI953174A/sv
Application granted granted Critical
Publication of FI116867B publication Critical patent/FI116867B/sv

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

Claims (8)

1. Förfarande för framställning av flerchjpsmoduler, sorr ovanpä varandra beiägna skikt av ett isoleringsmaterial samt i dess deledare, kännetecknat avatt 5. som isoleringsmaterial används en temperaturstabil, alk polymer med en dielektricitetskoefficient som är ^ 3 och som anbrii bottenplatta som inte leder elektricitet, varvid den fungerar som < gränsare i en strömlös, autokatalytisk framställningsprocess av led a), 10. isoleringsmaterialet är belagt med ett skikt bestaende a rial som löser sig i ett organiskt lösningsmedel (avlägsningsskikt) (fig - isoleringsmaterialet och avlägsningsskiktet mönsterpräj ma exponeringstekniska steg, varvid mönsterpräglingen kan ske indirekt, och i isoleringsmaterialet uppstär fördjupningar, vilkas form 15 (figure), - pä isoleringsmaterialets eller avlägsningsskiktets yta an metalliskt kämskikt genom avdunstning pä ett riktat sätt (figur f), - avlägsningsskiktet avlägsnas med hjälp av ett organise medet (figur g), 20. i fördjupningama ästadkoms ledarmönster med hjälp a ... metallavskiljning (figur h).
2. Förfarande enligt patentkrav l.kännetecknat a : *' ringsmateriaiet och avlägsningsskiktet är ljuskänsliga, och att en di ] : terprägling utförs (figure). : V 25 3. Förfarande enligt patentkrav l.kännetecknat a' • * : rialet i avlägsningsskiktet är ett kiselhaltigt eller silicifierbart Ijuskänsl 'V': ringslack, och mönsterpräglingen utförs indirekt med hjälp av et sker i syreplasma (figur c). : 4. Förfarande enligt nägot av patentkraven 1-3, k ä n n e t .***. 30 av att isoleringsmaterialet är polybensoxazol eller polyimid. ··· 18
7. Förfarande enligt ett eller flera av patentkraven 1-6, tecknat avatt metelien i fördjupningama avskiljs frän en utspl saltlösning, i synnerhet frän en kopparsaltlösning (figur h).
8. Förfarande enligt ett eller flera av patentkraven 1-7, 5 t e c k n a t av att som bottenplatta används en kiselskiva som är b ett tunt metallskikt och ett tunt skikt isoleringsmaterial.
9. Förfarande enligt ett eller flera av patentkraven 1-8, tecknat av att pä motsvarande sätt ästadkoms genomkopplingar i-n). ·· · • M» »» • * * «· • * ·· · • I « • « • · • · • · · • · ♦ ·♦· • · · • · · • ♦ • · · • ♦ · Φ ··» • · » · ··· Λ
FI953174A 1994-06-27 1995-06-27 Förbindnings- och monteringsteknik för flerchipsmoduler FI116867B (sv)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4422345 1994-06-27
DE4422345 1994-06-27

Publications (3)

Publication Number Publication Date
FI953174A0 FI953174A0 (sv) 1995-06-27
FI953174A FI953174A (sv) 1995-12-28
FI116867B true FI116867B (sv) 2006-03-15

Family

ID=6521543

Family Applications (1)

Application Number Title Priority Date Filing Date
FI953174A FI116867B (sv) 1994-06-27 1995-06-27 Förbindnings- och monteringsteknik för flerchipsmoduler

Country Status (5)

Country Link
US (1) US5556812A (sv)
EP (1) EP0690494B1 (sv)
JP (1) JP3630777B2 (sv)
DE (1) DE59510873D1 (sv)
FI (1) FI116867B (sv)

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EP0784913A2 (en) * 1995-08-09 1997-07-23 Koninklijke Philips Electronics N.V. Method of manufacturing devices comprising a base with a conductor pattern of electrical conductors
US6037248A (en) * 1997-06-13 2000-03-14 Micron Technology, Inc. Method of fabricating integrated circuit wiring with low RC time delay
WO1999017366A1 (de) * 1997-09-29 1999-04-08 Siemens Aktiengesellschaft Halbleiterbauelement und verfahren zu seiner herstellung
US6727170B2 (en) * 1998-02-16 2004-04-27 Renesas Technology Corp. Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
JPH11340321A (ja) * 1998-05-27 1999-12-10 Sony Corp 半導体装置およびその製造方法
US6277203B1 (en) * 1998-09-29 2001-08-21 Lam Research Corporation Method and apparatus for cleaning low K dielectric and metal wafer surfaces
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US6678952B2 (en) * 2000-08-03 2004-01-20 Tessera, Inc. Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof
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Also Published As

Publication number Publication date
FI953174A (sv) 1995-12-28
FI953174A0 (sv) 1995-06-27
EP0690494A3 (de) 1998-03-18
EP0690494B1 (de) 2004-03-17
EP0690494A2 (de) 1996-01-03
JPH0818227A (ja) 1996-01-19
DE59510873D1 (de) 2004-04-22
US5556812A (en) 1996-09-17
JP3630777B2 (ja) 2005-03-23

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