FI953174A0 - Förbindnings- och monteringsteknik för flerchopmoduler - Google Patents
Förbindnings- och monteringsteknik för flerchopmodulerInfo
- Publication number
- FI953174A0 FI953174A0 FI953174A FI953174A FI953174A0 FI 953174 A0 FI953174 A0 FI 953174A0 FI 953174 A FI953174 A FI 953174A FI 953174 A FI953174 A FI 953174A FI 953174 A0 FI953174 A0 FI 953174A0
- Authority
- FI
- Finland
- Prior art keywords
- connection
- chip modules
- installation technology
- installation
- technology
- Prior art date
Links
- 238000009434 installation Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Physical Vapour Deposition (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4422345 | 1994-06-27 | ||
DE4422345 | 1994-06-27 |
Publications (3)
Publication Number | Publication Date |
---|---|
FI953174A0 true FI953174A0 (sv) | 1995-06-27 |
FI953174A FI953174A (sv) | 1995-12-28 |
FI116867B FI116867B (sv) | 2006-03-15 |
Family
ID=6521543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI953174A FI116867B (sv) | 1994-06-27 | 1995-06-27 | Förbindnings- och monteringsteknik för flerchipsmoduler |
Country Status (5)
Country | Link |
---|---|
US (1) | US5556812A (sv) |
EP (1) | EP0690494B1 (sv) |
JP (1) | JP3630777B2 (sv) |
DE (1) | DE59510873D1 (sv) |
FI (1) | FI116867B (sv) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5550405A (en) * | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
WO1997006656A2 (en) * | 1995-08-09 | 1997-02-20 | Philips Electronics N.V. | Method of manufacturing devices comprising a base with a conductor pattern of electrical conductors |
US6037248A (en) * | 1997-06-13 | 2000-03-14 | Micron Technology, Inc. | Method of fabricating integrated circuit wiring with low RC time delay |
WO1999017366A1 (de) * | 1997-09-29 | 1999-04-08 | Siemens Aktiengesellschaft | Halbleiterbauelement und verfahren zu seiner herstellung |
US6727170B2 (en) * | 1998-02-16 | 2004-04-27 | Renesas Technology Corp. | Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof |
JPH11340321A (ja) * | 1998-05-27 | 1999-12-10 | Sony Corp | 半導体装置およびその製造方法 |
US6277203B1 (en) | 1998-09-29 | 2001-08-21 | Lam Research Corporation | Method and apparatus for cleaning low K dielectric and metal wafer surfaces |
DE19929179A1 (de) * | 1999-06-25 | 2001-01-11 | Siemens Ag | Flexible Leiterplatte mit beidseitigem Zugriff |
WO2001003173A1 (en) * | 1999-07-01 | 2001-01-11 | Lam Research Corporation | Method for patterning a layer of a low dielectric constant material |
EP1138804A3 (de) * | 2000-03-27 | 2003-06-25 | Infineon Technologies AG | Bauelement mit zumindest zwei aneinander grenzenden Isolierschichten und Herstellungsverfahren dazu |
US6678952B2 (en) * | 2000-08-03 | 2004-01-20 | Tessera, Inc. | Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof |
US6605519B2 (en) * | 2001-05-02 | 2003-08-12 | Unaxis Usa, Inc. | Method for thin film lift-off processes using lateral extended etching masks and device |
JP3834589B2 (ja) * | 2001-06-27 | 2006-10-18 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
DE10250538B4 (de) * | 2002-10-29 | 2008-02-21 | Infineon Technologies Ag | Elektronisches Bauteil als Multichipmodul und Verfahren zu dessen Herstellung |
TWI248138B (en) * | 2002-12-20 | 2006-01-21 | Shipley Co Llc | Electronic device manufacture |
US20040187297A1 (en) * | 2003-03-27 | 2004-09-30 | E Touch Corporation | Method of fabricating a polymer resistor in an interconnection via |
US20040192039A1 (en) * | 2003-03-27 | 2004-09-30 | E Touch Corporation | Method of fabricating a multi-layer circuit structure having embedded polymer resistors |
KR20040092550A (ko) * | 2003-04-24 | 2004-11-04 | 클라리언트 인터내셔널 리미티드 | 레지스트 조성물 및 레지스트 제거용 유기용제 |
US7150820B2 (en) * | 2003-09-22 | 2006-12-19 | Semitool, Inc. | Thiourea- and cyanide-free bath and process for electrolytic etching of gold |
US20050092616A1 (en) * | 2003-11-03 | 2005-05-05 | Semitool, Inc. | Baths, methods, and tools for superconformal deposition of conductive materials other than copper |
DE10355586B4 (de) * | 2003-11-28 | 2007-09-27 | Infineon Technologies Ag | Chip-on-Chip-Struktur und Verfahren zu deren Herstellung |
KR100847985B1 (ko) * | 2007-06-25 | 2008-07-22 | 삼성전자주식회사 | 금속 배선 형성방법 |
KR100916647B1 (ko) * | 2007-11-26 | 2009-09-08 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
CN102449748B (zh) * | 2009-05-13 | 2015-06-17 | 宾夕法尼亚大学理事会 | 与碳纳米结构的光蚀刻划定的接触 |
WO2013057949A2 (en) * | 2011-10-19 | 2013-04-25 | Panasonic Corporation | Manufacturing method for semiconductor package, semiconductor package, and semiconductor device |
US20190098703A1 (en) * | 2017-09-26 | 2019-03-28 | E I Du Pont De Nemours And Company | Heating elements and heating devices |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4705606A (en) | 1985-01-31 | 1987-11-10 | Gould Inc. | Thin-film electrical connections for integrated circuits |
US5270253A (en) * | 1986-01-27 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Method of producing semiconductor device |
WO1988005252A1 (en) | 1987-01-12 | 1988-07-14 | Allied Corporation | Method for the manufacture of multilayer printed circuit boards |
US4770897A (en) | 1987-05-05 | 1988-09-13 | Digital Equipment Corporation | Multilayer interconnection system for multichip high performance semiconductor packaging |
US5286713A (en) * | 1987-05-08 | 1994-02-15 | Fujitsu Limited | Method for manufacturing an oxide superconducting circuit board by printing |
DE3853316T2 (de) * | 1987-05-08 | 1995-08-03 | Fujitsu Ltd | Supraleitende Schaltungskarte und Verfahren zu ihrer Herstellung. |
EP0291779B1 (de) | 1987-05-18 | 1994-07-27 | Siemens Aktiengesellschaft | Wärmebeständige Positivresists und Verfahren zur Herstellung wärmebeständiger Reliefstrukturen |
DE3888390D1 (de) | 1987-05-18 | 1994-04-21 | Siemens Ag | Verfahren zur Herstellung hochwärmebeständiger Dielektrika. |
US4956313A (en) * | 1987-08-17 | 1990-09-11 | International Business Machines Corporation | Via-filling and planarization technique |
DD272755A1 (de) * | 1988-05-20 | 1989-10-18 | Robotron Elektronik | Verfahren zur herstellung eines mehrebenensubstrates |
US5108785A (en) * | 1989-09-15 | 1992-04-28 | Microlithics Corporation | Via formation method for multilayer interconnect board |
JP3469251B2 (ja) * | 1990-02-14 | 2003-11-25 | 株式会社東芝 | 半導体装置の製造方法 |
JPH03297103A (ja) * | 1990-04-17 | 1991-12-27 | Cmk Corp | プリント配線板におけるカーボン抵抗体の形成方法 |
US5153023A (en) * | 1990-12-03 | 1992-10-06 | Xerox Corporation | Process for catalysis of electroless metal plating on plastic |
US5171712A (en) * | 1991-12-20 | 1992-12-15 | Vlsi Technology, Inc. | Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate |
JP3219909B2 (ja) * | 1993-07-09 | 2001-10-15 | 株式会社東芝 | 半導体装置の製造方法 |
DE4331185C1 (de) * | 1993-09-14 | 1994-12-15 | Siemens Ag | Verfahren zur Kontaktlochauffüllung in einem Halbleiterschichtaufbau |
-
1995
- 1995-06-14 EP EP95109271A patent/EP0690494B1/de not_active Expired - Lifetime
- 1995-06-14 DE DE59510873T patent/DE59510873D1/de not_active Expired - Lifetime
- 1995-06-21 JP JP17688195A patent/JP3630777B2/ja not_active Expired - Lifetime
- 1995-06-27 FI FI953174A patent/FI116867B/sv not_active IP Right Cessation
- 1995-06-27 US US08/495,246 patent/US5556812A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5556812A (en) | 1996-09-17 |
EP0690494A2 (de) | 1996-01-03 |
FI953174A (sv) | 1995-12-28 |
EP0690494A3 (de) | 1998-03-18 |
JPH0818227A (ja) | 1996-01-19 |
DE59510873D1 (de) | 2004-04-22 |
EP0690494B1 (de) | 2004-03-17 |
JP3630777B2 (ja) | 2005-03-23 |
FI116867B (sv) | 2006-03-15 |
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Legal Events
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FG | Patent granted |
Ref document number: 116867 Country of ref document: FI |
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MA | Patent expired |