ES8405200A1 - Un metodo para producir una estructura de vidrio-ceramica de multiples capas. - Google Patents

Un metodo para producir una estructura de vidrio-ceramica de multiples capas.

Info

Publication number
ES8405200A1
ES8405200A1 ES523275A ES523275A ES8405200A1 ES 8405200 A1 ES8405200 A1 ES 8405200A1 ES 523275 A ES523275 A ES 523275A ES 523275 A ES523275 A ES 523275A ES 8405200 A1 ES8405200 A1 ES 8405200A1
Authority
ES
Spain
Prior art keywords
copper
glass
temperature
ceramic
ceramic structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES523275A
Other languages
English (en)
Other versions
ES523275A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8405200A1 publication Critical patent/ES8405200A1/es
Publication of ES523275A0 publication Critical patent/ES523275A0/es
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • H05K3/1291—Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/088—Using a vapour or mist, e.g. cleaning using water vapor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)

Abstract

METODO PARA PRODUCIR UNA ESTRUCTURA DE VIDRIO-MATERIAL CERAMICO DE MULTIPLES CAPAS.CONSISTE EN CALCINAR UNA ESTRUCTURA DE CAPAS MULTIPLES DE COBRE Y DE VIDRIO-MATERIAL CERAMICO, EN UNA ATMOSFERA INERTE CON VAPOR DE AGUA A UNA TEMPERATURA QUE SE DESPOLIMERIZA Y ELIMINA UNA RESINA AGLOMERANTE CONTENIDA EN LAS HOJAS DE VIDRIO-MATERIAL CERAMICO, Y FINALMENTE, ELEVA LA TEMPERATURA DE CALCINACION.
ES523275A 1982-06-16 1983-06-15 Un metodo para producir una estructura de vidrio-ceramica de multiples capas. Granted ES523275A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57101990A JPS59995A (ja) 1982-06-16 1982-06-16 銅導体多層構造体の製造方法

Publications (2)

Publication Number Publication Date
ES8405200A1 true ES8405200A1 (es) 1984-05-16
ES523275A0 ES523275A0 (es) 1984-05-16

Family

ID=14315269

Family Applications (1)

Application Number Title Priority Date Filing Date
ES523275A Granted ES523275A0 (es) 1982-06-16 1983-06-15 Un metodo para producir una estructura de vidrio-ceramica de multiples capas.

Country Status (8)

Country Link
US (1) US4504339A (es)
EP (1) EP0098067B1 (es)
JP (1) JPS59995A (es)
KR (1) KR880000367B1 (es)
AU (1) AU546794B2 (es)
CA (1) CA1194314A (es)
DE (1) DE3378668D1 (es)
ES (1) ES523275A0 (es)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60221358A (ja) * 1984-04-13 1985-11-06 日本碍子株式会社 電気絶縁体用セラミック組成物
JPS60254697A (ja) * 1984-05-31 1985-12-16 富士通株式会社 多層セラミック回路基板および製法
US4657778A (en) * 1984-08-01 1987-04-14 Moran Peter L Multilayer systems and their method of production
FR2571545B1 (fr) * 1984-10-05 1987-11-27 Thomson Csf Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede
US4645552A (en) * 1984-11-19 1987-02-24 Hughes Aircraft Company Process for fabricating dimensionally stable interconnect boards
JPS61155243A (ja) * 1984-12-28 1986-07-14 富士通株式会社 グリ−ンシ−ト組成物
CA1253628A (en) * 1985-03-04 1989-05-02 Charles J. Leedecke Hybrid and multi-layer circuitry
EP0196865B1 (en) * 1985-03-27 1990-09-12 Ibiden Co, Ltd. Electronic circuit substrates
JPS61270897A (ja) * 1985-05-25 1986-12-01 株式会社住友金属セラミックス 多層回路基板
US4627160A (en) * 1985-08-02 1986-12-09 International Business Machines Corporation Method for removal of carbonaceous residues from ceramic structures having internal metallurgy
JPS6247196A (ja) * 1985-08-26 1987-02-28 松下電器産業株式会社 セラミツク多層基板
US4678683A (en) * 1985-12-13 1987-07-07 General Electric Company Process for cofiring structure comprised of ceramic substrate and refractory metal metallization
US4795512A (en) * 1986-02-26 1989-01-03 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a multilayer ceramic body
US4885038A (en) * 1986-05-01 1989-12-05 International Business Machines Corporation Method of making multilayered ceramic structures having an internal distribution of copper-based conductors
JPS63128791A (ja) * 1986-11-12 1988-06-01 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション 金属導体を有する高密度多層ガラス・セラミツク構造体の製造方法
CA1273853A (en) * 1986-12-17 1990-09-11 Hitoshi Suzuki Method for production of ceramic circuit board
CA1329952C (en) * 1987-04-27 1994-05-31 Yoshihiko Imanaka Multi-layer superconducting circuit substrate and process for manufacturing same
US4788046A (en) * 1987-08-13 1988-11-29 Ceramics Process Systems Corporation Method for producing materials for co-sintering
US4799984A (en) * 1987-09-18 1989-01-24 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US5147484A (en) * 1987-10-19 1992-09-15 International Business Machines Corporation Method for producing multi-layer ceramic substrates with oxidation resistant metalization
JPH0650792B2 (ja) * 1987-10-19 1994-06-29 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 耐酸化金属導体を含むセラミック構造体及びその製造方法
US4931323A (en) * 1987-12-10 1990-06-05 Texas Instruments Incorporated Thick film copper conductor patterning by laser
JPH0772092B2 (ja) * 1988-02-10 1995-08-02 日本特殊陶業株式会社 低温焼成基板
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
JPH0728128B2 (ja) * 1988-03-11 1995-03-29 松下電器産業株式会社 セラミック多層配線基板とその製造方法
US5053361A (en) * 1988-07-18 1991-10-01 International Business Machines Corporation Setter tile for use in sintering of ceramic substrate laminates
US4971738A (en) * 1988-07-18 1990-11-20 International Business Machines Corporation Enhanced removal of carbon from ceramic substrate laminates
CA2007199C (en) * 1989-02-03 1993-05-18 Satish S. Tamhankar Single atmosphere for firing copper compatible thick film materials
US5194294A (en) * 1989-02-20 1993-03-16 L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Process for preparing electrical connection means, in particular interconnection substances of hybrid circuits
FR2643535B1 (fr) * 1989-02-20 1991-04-26 Air Liquide Procede d'elaboration de moyens de connexion electrique, en particulier de substrats d'interconnexion de circuits hybrides
US5041695A (en) * 1989-06-01 1991-08-20 Westinghouse Electric Corp. Co-fired ceramic package for a power circuit
US5089070A (en) * 1989-12-07 1992-02-18 Pac Polymers Inc. Poly(propylene carbonate)-containing ceramic tape formulations and the green tapes resulting therefrom
KR920002589B1 (ko) * 1990-03-30 1992-03-30 삼성코닝 주식회사 금속 인쇄된 세라믹 팩키지의 제조방법
DE4025715C1 (es) * 1990-08-14 1992-04-02 Robert Bosch Gmbh, 7000 Stuttgart, De
US5073180A (en) * 1991-03-20 1991-12-17 International Business Machines Corporation Method for forming sealed co-fired glass ceramic structures
US5215610A (en) * 1991-04-04 1993-06-01 International Business Machines Corporation Method for fabricating superconductor packages
US5682018A (en) * 1991-10-18 1997-10-28 International Business Machines Corporation Interface regions between metal and ceramic in a metal/ceramic substrate
US5925444A (en) * 1992-12-09 1999-07-20 Hitachi, Ltd. Organic binder for shaping ceramic, its production method and product employing the same
US5728470A (en) * 1994-05-13 1998-03-17 Nec Corporation Multi-layer wiring substrate, and process for producing the same
DE4443365A1 (de) * 1994-12-06 1996-06-13 Philips Patentverwaltung Brenn- und Sinterverfahren für ein keramisches elektronisches Bauteil
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JPS51111666A (en) * 1975-03-26 1976-10-02 Hitachi Ltd Method of manufacturing multilayered wiring ceramic structure
JPS51127112A (en) * 1975-04-30 1976-11-05 Fujitsu Ltd Method of producing multiilayered glass substrate
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JPS58223678A (ja) * 1982-06-16 1983-12-26 株式会社日立製作所 金属化層を有するＳｉＣ焼結体とその製法

Also Published As

Publication number Publication date
CA1194314A (en) 1985-10-01
KR840005302A (ko) 1984-11-05
ES523275A0 (es) 1984-05-16
EP0098067B1 (en) 1988-12-07
EP0098067A3 (en) 1985-06-12
DE3378668D1 (en) 1989-01-12
JPH039636B2 (es) 1991-02-08
EP0098067A2 (en) 1984-01-11
AU546794B2 (en) 1985-09-19
US4504339A (en) 1985-03-12
KR880000367B1 (ko) 1988-03-20
AU1530983A (en) 1984-12-20
JPS59995A (ja) 1984-01-06

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20040916