FR2571545B1 - Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede - Google Patents

Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede

Info

Publication number
FR2571545B1
FR2571545B1 FR8415325A FR8415325A FR2571545B1 FR 2571545 B1 FR2571545 B1 FR 2571545B1 FR 8415325 A FR8415325 A FR 8415325A FR 8415325 A FR8415325 A FR 8415325A FR 2571545 B1 FR2571545 B1 FR 2571545B1
Authority
FR
France
Prior art keywords
hybrid
circuit
planar
substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8415325A
Other languages
English (en)
Other versions
FR2571545A1 (fr
Inventor
Daniel Mestdagh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR8415325A priority Critical patent/FR2571545B1/fr
Publication of FR2571545A1 publication Critical patent/FR2571545A1/fr
Application granted granted Critical
Publication of FR2571545B1 publication Critical patent/FR2571545B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302—Bending a rigid substrate; Breaking rigid substrates by bending
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
FR8415325A 1984-10-05 1984-10-05 Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede Expired FR2571545B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8415325A FR2571545B1 (fr) 1984-10-05 1984-10-05 Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8415325A FR2571545B1 (fr) 1984-10-05 1984-10-05 Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede

Publications (2)

Publication Number Publication Date
FR2571545A1 FR2571545A1 (fr) 1986-04-11
FR2571545B1 true FR2571545B1 (fr) 1987-11-27

Family

ID=9308385

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8415325A Expired FR2571545B1 (fr) 1984-10-05 1984-10-05 Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede

Country Status (1)

Country Link
FR (1) FR2571545B1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766027A (en) * 1987-01-13 1988-08-23 E. I. Du Pont De Nemours And Company Method for making a ceramic multilayer structure having internal copper conductors
US4799984A (en) * 1987-09-18 1989-01-24 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US5028473A (en) * 1989-10-02 1991-07-02 Hughes Aircraft Company Three dimensional microcircuit structure and process for fabricating the same from ceramic tape
US5006182A (en) * 1989-11-17 1991-04-09 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
EP0477981A3 (en) * 1990-09-27 1992-05-06 Toshiba Lighting & Technology Corporation Multi-layer circuit substrate having a non-planar shape, and a method for the manufacture thereof
JP2002517909A (ja) 1998-06-05 2002-06-18 ディーエスエム エヌ．ブイ． 曲げられたセラミックス製成形部品
US6370767B1 (en) 1999-10-04 2002-04-16 Artesyn Technologies, Inc. Method for fabricating an electrical apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3374110A (en) * 1964-05-27 1968-03-19 Ibm Conductive element, composition and method
FR2238688A1 (en) * 1973-07-27 1975-02-21 Hitachi Ltd Sintered laminated integrated circuit unit - mfd. from ceramic, and printed conducting assemblies on a ceramic substrate
US4109377A (en) * 1976-02-03 1978-08-29 International Business Machines Corporation Method for preparing a multilayer ceramic
US4445274A (en) * 1977-12-23 1984-05-01 Ngk Insulators, Ltd. Method of manufacturing a ceramic structural body
US4413061A (en) * 1978-02-06 1983-11-01 International Business Machines Corporation Glass-ceramic structures and sintered multilayer substrates thereof with circuit patterns of gold, silver or copper
JPS59995A (ja) * 1982-06-16 1984-01-06 富士通株式会社 銅導体多層構造体の製造方法

Also Published As

Publication number Publication date
FR2571545A1 (fr) 1986-04-11

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Legal Events

Date Code Title Description
ST Notification of lapse