ES2186890T3 - Disposicion de circuito con un numero de componentes electronicos de circuito. - Google Patents
Disposicion de circuito con un numero de componentes electronicos de circuito.Info
- Publication number
- ES2186890T3 ES2186890T3 ES97920549T ES97920549T ES2186890T3 ES 2186890 T3 ES2186890 T3 ES 2186890T3 ES 97920549 T ES97920549 T ES 97920549T ES 97920549 T ES97920549 T ES 97920549T ES 2186890 T3 ES2186890 T3 ES 2186890T3
- Authority
- ES
- Spain
- Prior art keywords
- circuit
- opening
- circuit components
- opening stage
- components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Abstract
LA INVENCION SE REFIERE A UN CONJUNTO DE CIRCUITOS CON VARIOS COMPONENTES DE CIRCUITO ELECTRONICOS (2, 3, 4, 5), CUYO ESTADO OPERATIVO PUEDE CONMUTARSE, MEDIANTE UNA SEÑAL DE MANDO (6, 7, 8, 9) DEFINIDA, APLICADA AL CORRESPONDIENTE COMPONENTES DEL CIRCUITO (2, 3, 4, 5), A UN ESTADO DE REINICIO Y BORRADO EN EL QUE EL CONTENIDO DE DATOS DEL COMPONENTE (2, 3, 4, 5) ADOPTA COMO VALOR EL CERO LOGICO. SE HA PREVISTO UN CIRCUITO DE CONTROL (25), ACTIVABLE PARA EL REINICIO SUCESIVO DE LOS CONTENIDOS DE DATOS DE LOS DIFERENTES COMPONENTES DEL CIRCUITO (2, 3, 4, 5) AL CERO LOGICO, CON UN NUMERO DE ETAPAS DE APERTURA (26, 27, 28, 29), CONECTADAS SUCESIVAMENTE EN SERIE, CORRESPONDIENTE AL NUMERO DE COMPONENTES DE CIRCUITO (2, 3, 4, 5). CADA COMPONENTE (2, 3, 4, 5) TIENE ASIGNADA UNA ETAPA DE APERTURA (26, 27, 28, 29) DEL CIRCUITO DE CONTROL (25). CADA ETAPA DE APERTURA (26, 27, 28, 29), SALVO LA PRIMERA, ES ACTIVADA O EXCITADA POR UNA SEÑAL DE APERTURA (42, 43, 44, 45), GENERADA POR LA ETAPA DE APERTURA INMEDIATAMENTE ANTERIOR (26, 27, 28, 29), PARA ENVIAR UNA SEÑAL DE MANDO AL COMPONENTE DE CIRCUITO ASIGNADO. UNA VEZ REINICIADO EL COMPONENTE DE CIRCUITO ASIGNADO (2, 3, 4, 5), LA ETAPA DE APERTURA (26, 27, 28, 29) CORRESPONDIENTE EMITE UNA SEÑAL DE APERTURA (42, 43, 44, 45) PARA EL CONTROL Y LA ACTIVACION DE LA ETAPA DE APERTURA INMEDIATAMENTE SIGUIENTE (26, 72, 28, 29).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19612440A DE19612440C1 (de) | 1996-03-28 | 1996-03-28 | Schaltungsanordnung mit einer Anzahl von elektronischen Schaltungskomponenten |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2186890T3 true ES2186890T3 (es) | 2003-05-16 |
Family
ID=7789783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES97920549T Expired - Lifetime ES2186890T3 (es) | 1996-03-28 | 1997-03-26 | Disposicion de circuito con un numero de componentes electronicos de circuito. |
Country Status (13)
Country | Link |
---|---|
US (1) | US5991207A (es) |
EP (1) | EP0890173B1 (es) |
JP (1) | JP3174066B2 (es) |
KR (1) | KR100400532B1 (es) |
CN (1) | CN1163906C (es) |
AT (1) | ATE227467T1 (es) |
BR (1) | BR9708367A (es) |
DE (2) | DE19612440C1 (es) |
ES (1) | ES2186890T3 (es) |
IN (1) | IN191217B (es) |
RU (1) | RU2189082C2 (es) |
UA (1) | UA54418C2 (es) |
WO (1) | WO1997037353A1 (es) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100386949B1 (ko) * | 2001-03-14 | 2003-06-09 | 삼성전자주식회사 | 디지털 데이터 처리 시스템 |
JP4443067B2 (ja) * | 2001-04-26 | 2010-03-31 | 富士通マイクロエレクトロニクス株式会社 | プロセッサおよびそのリセット制御方法 |
DE10152034B4 (de) * | 2001-10-23 | 2004-08-26 | Infineon Technologies Ag | Speicheranordnung |
US6990011B2 (en) * | 2003-05-09 | 2006-01-24 | Stmicroelectronics, Inc. | Memory circuit and method for corrupting stored data |
US7224600B2 (en) * | 2004-01-08 | 2007-05-29 | Stmicroelectronics, Inc. | Tamper memory cell |
US8548420B2 (en) * | 2007-10-05 | 2013-10-01 | Hand Held Products, Inc. | Panic button for data collection device |
DE102010035374A1 (de) * | 2010-08-25 | 2012-03-01 | Airbus Operations Gmbh | System und Verfahren zum Sammeln von Defektdaten von Bauteilen in einer Passagierkabine eines Fahrzeugs |
CN103077137A (zh) * | 2011-10-25 | 2013-05-01 | 北京大豪科技股份有限公司 | 中断控制方法及中断控制单元 |
KR101565536B1 (ko) | 2015-08-31 | 2015-11-03 | 박기선 | 종이 판지용 정밀교정 적층장치 |
CN108664435B (zh) * | 2018-07-30 | 2024-02-23 | 合肥联宝信息技术有限公司 | 一种数据清除电路及电子设备 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE425705B (sv) * | 1980-12-23 | 1982-10-25 | Ericsson Telefon Ab L M | Anordning for att i en databasanleggning automatiskt forstora informationsinnehallet i dataminnen och programminnen |
DE3318101A1 (de) * | 1983-05-18 | 1984-11-22 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordung mit einem speicher und einer zugriffskontrolleinheit |
US5054000A (en) * | 1988-02-19 | 1991-10-01 | Sony Corporation | Static random access memory device having a high speed read-out and flash-clear functions |
US4928266A (en) * | 1988-05-26 | 1990-05-22 | Visic, Inc. | Static ram with high speed, low power reset |
DE3886529T2 (de) * | 1988-08-27 | 1994-06-30 | Ibm | Einrichtung in einem Datenverarbeitungssystem zur System-Initialisierung und -Rückstellung. |
US5381366A (en) * | 1989-04-11 | 1995-01-10 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory device with timer controlled re-write inhibit means |
DE4135767C2 (de) * | 1991-10-30 | 2003-04-30 | Adp Gauselmann Gmbh | Verfahren zum Sichern von in datenspeichernden elektronischen Bauelementen gespeicherten Daten gegen einen unbefugten Zugriff und/oder Manipulation und Vorrichtung zur Durchführung des Verfahrens |
US5724289A (en) * | 1993-09-08 | 1998-03-03 | Fujitsu Limited | Nonvolatile semiconductor memory capable of selectively performing a pre-conditioning of threshold voltage before an erase self-test of memory cells and a method related therewith |
-
1996
- 1996-03-28 DE DE19612440A patent/DE19612440C1/de not_active Expired - Fee Related
-
1997
- 1997-03-18 IN IN480CA1997 patent/IN191217B/en unknown
- 1997-03-26 CN CNB971934339A patent/CN1163906C/zh not_active Expired - Lifetime
- 1997-03-26 EP EP97920549A patent/EP0890173B1/de not_active Expired - Lifetime
- 1997-03-26 KR KR10-1998-0707682A patent/KR100400532B1/ko not_active IP Right Cessation
- 1997-03-26 WO PCT/DE1997/000622 patent/WO1997037353A1/de active IP Right Grant
- 1997-03-26 BR BR9708367A patent/BR9708367A/pt not_active Application Discontinuation
- 1997-03-26 DE DE59708669T patent/DE59708669D1/de not_active Expired - Lifetime
- 1997-03-26 RU RU98119737/09A patent/RU2189082C2/ru active
- 1997-03-26 UA UA98095073A patent/UA54418C2/uk unknown
- 1997-03-26 JP JP53480697A patent/JP3174066B2/ja not_active Expired - Lifetime
- 1997-03-26 ES ES97920549T patent/ES2186890T3/es not_active Expired - Lifetime
- 1997-03-26 AT AT97920549T patent/ATE227467T1/de not_active IP Right Cessation
-
1998
- 1998-09-28 US US09/163,627 patent/US5991207A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
UA54418C2 (uk) | 2003-03-17 |
ATE227467T1 (de) | 2002-11-15 |
CN1163906C (zh) | 2004-08-25 |
EP0890173B1 (de) | 2002-11-06 |
JP3174066B2 (ja) | 2001-06-11 |
US5991207A (en) | 1999-11-23 |
JPH11507165A (ja) | 1999-06-22 |
CN1214792A (zh) | 1999-04-21 |
WO1997037353A1 (de) | 1997-10-09 |
DE59708669D1 (de) | 2002-12-12 |
DE19612440C1 (de) | 1997-05-07 |
BR9708367A (pt) | 1999-08-03 |
KR100400532B1 (ko) | 2003-11-15 |
KR20000005055A (ko) | 2000-01-25 |
EP0890173A1 (de) | 1999-01-13 |
RU2189082C2 (ru) | 2002-09-10 |
IN191217B (es) | 2003-10-11 |
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