ES2163043T3 - Matriz de rejilla de resaltes de polimero. - Google Patents

Matriz de rejilla de resaltes de polimero.

Info

Publication number
ES2163043T3
ES2163043T3 ES96934620T ES96934620T ES2163043T3 ES 2163043 T3 ES2163043 T3 ES 2163043T3 ES 96934620 T ES96934620 T ES 96934620T ES 96934620 T ES96934620 T ES 96934620T ES 2163043 T3 ES2163043 T3 ES 2163043T3
Authority
ES
Spain
Prior art keywords
polymer
pct
substrate
connections
date apr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES96934620T
Other languages
English (en)
Inventor
Ann Dumoulin
Marcel Heerman
Jean Roggen
Eric Beyne
Hoof Rita Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INTERUNIVERSITAIRE MICROELEKTR
Siemens NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
INTERUNIVERSITAIRE MICROELEKTR
Siemens NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INTERUNIVERSITAIRE MICROELEKTR, Siemens NV SA, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical INTERUNIVERSITAIRE MICROELEKTR
Application granted granted Critical
Publication of ES2163043T3 publication Critical patent/ES2163043T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Surface Heating Bodies (AREA)
  • Pens And Brushes (AREA)
  • Vehicle Interior And Exterior Ornaments, Soundproofing, And Insulation (AREA)

Abstract

SE PROPONE UN DISPOSITIVO EN REJILLA DE TACOS POLIMERICOS PARA MEJORAR LA EVACUACION DEL CALOR DE PERDIDA, CON UN SUSTRATO TRIDIMENSIONAL (S) DE FUNDICION INYECTADA A PARTIR DE UN POLIMERO ELECTRICAMENTE AISLANTE; TACOS POLIMERICOS (PS) DISPUESTOS SUPERFICIALMENTE SOBRE LA CARA INFERIOR DEL SUSTRATO (S) Y MOLDEADOS TAMBIEN DURANTE LA FUNDICION INYECTADA; CONEXIONES EXTERIORES FORMADAS SOBRE LOS TACOS POLIMERICOS (PS) MEDIANTE UNA SUPERFICIE EXTREMA SOLDABLE; APAREJOS ELECTRICOS CONFORMADOS AL MENOS SOBRE LA CARA INFERIOR DEL SUSTRATO (S), QUE UNEN LAS CONEXIONES EXTERIORES A LAS CONEXIONES INTERIORES; AL MENOS UN CUERPO TERMICAMENTE CONDUCTOR (WL) INYECTADO PARCIALMENTE DURANTE LA FUNDICION INYECTADA DEL SUSTRATO (S); Y CON AL MENOS UN CHIP O ELEMENTO DE CABLEADO (VE) DISPUESTO SOBRE EL CUERPO TERMICAMENTE CONDUCTOR (WL), CUYAS CONEXIONES ESTAN UNIDAS DE FORMA ELECTRICAMENTE CONDUCTORA A LAS CONEXIONES INTERIORES. LA NUEVA FORMA CONSTRUCTIVA ES ESPECIALMENTE APROPIADA PARA ELEMENTOS CONSTRUCTIVOS DE POTENCIA O GRUPOS CONSTRUCTIVOS DE POTENCIA EN EL DISPOSITIVO EN REJILLA DE TACOS POLIMERICOS.
ES96934620T 1995-10-16 1996-10-10 Matriz de rejilla de resaltes de polimero. Expired - Lifetime ES2163043T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19538464 1995-10-16

Publications (1)

Publication Number Publication Date
ES2163043T3 true ES2163043T3 (es) 2002-01-16

Family

ID=7774969

Family Applications (1)

Application Number Title Priority Date Filing Date
ES96934620T Expired - Lifetime ES2163043T3 (es) 1995-10-16 1996-10-10 Matriz de rejilla de resaltes de polimero.

Country Status (8)

Country Link
US (1) US6122172A (es)
EP (1) EP0856199B1 (es)
JP (1) JP3037440B2 (es)
KR (1) KR100430325B1 (es)
AT (1) ATE204678T1 (es)
DE (1) DE59607546D1 (es)
ES (1) ES2163043T3 (es)
WO (1) WO1997015078A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6705388B1 (en) * 1997-11-10 2004-03-16 Parker-Hannifin Corporation Non-electrically conductive thermal dissipator for electronic components
DE10030289B4 (de) * 1999-06-29 2012-10-04 Marquardt Gmbh Träger für Bauteile und Herstellungsverfahren
US6444489B1 (en) 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate
US6486549B1 (en) 2001-11-10 2002-11-26 Bridge Semiconductor Corporation Semiconductor module with encapsulant base
US6638082B2 (en) 2001-11-20 2003-10-28 Fci Americas Technology, Inc. Pin-grid-array electrical connector
US6666693B2 (en) 2001-11-20 2003-12-23 Fci Americas Technology, Inc. Surface-mounted right-angle electrical connector
US7052763B2 (en) * 2003-08-05 2006-05-30 Xerox Corporation Multi-element connector
US20050031840A1 (en) * 2003-08-05 2005-02-10 Xerox Corporation RF connector
DE102004032371A1 (de) 2004-06-30 2006-01-26 Robert Bosch Gmbh Elektronische Schaltungseinheit
US20090323295A1 (en) * 2008-06-30 2009-12-31 Houle Sabina J Injection molded metal stiffener and integrated carrier for packaging applications
US10128593B1 (en) 2017-09-28 2018-11-13 International Business Machines Corporation Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271507A (en) * 1965-11-02 1966-09-06 Alloys Unltd Inc Flat package for semiconductors
AU2073088A (en) * 1987-07-01 1989-01-30 Western Digital Corporation Plated plastic castellated interconnect for electrical components
WO1989000339A1 (en) * 1987-07-03 1989-01-12 Doduco Gmbh + Co. Dr. Eugen Dürrwächter Flat bodies, in particular for use as heat sinks for electronic power components
DE3732249A1 (de) * 1987-09-24 1989-04-13 Siemens Ag Verfahren zur herstellung von dreidimensionalen leiterplatten
US5152057A (en) * 1987-11-17 1992-10-06 Mold-Pac Corporation Molded integrated circuit package
US5438481A (en) * 1987-11-17 1995-08-01 Advanced Interconnections Corporation Molded-in lead frames
US5072283A (en) * 1988-04-12 1991-12-10 Bolger Justin C Pre-formed chip carrier cavity package
US4868349A (en) * 1988-05-09 1989-09-19 National Semiconductor Corporation Plastic molded pin-grid-array power package
US5081520A (en) * 1989-05-16 1992-01-14 Minolta Camera Kabushiki Kaisha Chip mounting substrate having an integral molded projection and conductive pattern
EP1020914B1 (en) * 1989-10-09 2004-04-28 Mitsubishi Materials Corporation Ceramic substrate used for fabricating electric or electronic circuit
US5012386A (en) * 1989-10-27 1991-04-30 Motorola, Inc. High performance overmolded electronic package
JPH03188654A (ja) * 1989-12-18 1991-08-16 Nippon Steel Corp 樹脂モールド型半導体用放熱体
WO1992002040A1 (en) * 1990-07-25 1992-02-06 Dsm N.V. Package for incorporating an integrated circuit and a process for the production of the package
JPH04322452A (ja) * 1991-04-23 1992-11-12 Mitsubishi Electric Corp 半導体装置、半導体素子収納容器および半導体装置の製造方法
JP2931741B2 (ja) * 1993-09-24 1999-08-09 株式会社東芝 半導体装置
EP0645953B1 (de) * 1993-09-29 1997-08-06 Siemens NV Verfahren zur Herstellung einer zwei- oder mehrlagigen Verdrahtung und danach hergestellte zwei- oder mehrlagige Verdrahtung
PT782765E (pt) * 1994-09-23 2000-12-29 Imec Inter Uni Micro Electr Embalagem matricial com saliencias de polimero
US5609889A (en) * 1995-05-26 1997-03-11 Hestia Technologies, Inc. Apparatus for encapsulating electronic packages

Also Published As

Publication number Publication date
JP3037440B2 (ja) 2000-04-24
ATE204678T1 (de) 2001-09-15
EP0856199B1 (de) 2001-08-22
KR100430325B1 (ko) 2004-09-18
US6122172A (en) 2000-09-19
WO1997015078A1 (de) 1997-04-24
EP0856199A1 (de) 1998-08-05
DE59607546D1 (de) 2001-09-27
KR19990064244A (ko) 1999-07-26
JPH11502064A (ja) 1999-02-16

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