ES2104871T3 - Procedimiento y dispositivo de control de modo de funcionamiento de un bucle de enclavamiento de fase numerica. - Google Patents
Procedimiento y dispositivo de control de modo de funcionamiento de un bucle de enclavamiento de fase numerica.Info
- Publication number
- ES2104871T3 ES2104871T3 ES92402653T ES92402653T ES2104871T3 ES 2104871 T3 ES2104871 T3 ES 2104871T3 ES 92402653 T ES92402653 T ES 92402653T ES 92402653 T ES92402653 T ES 92402653T ES 2104871 T3 ES2104871 T3 ES 2104871T3
- Authority
- ES
- Spain
- Prior art keywords
- loop
- input signal
- appearance
- counter
- procedure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title abstract 3
- 238000001514 detection method Methods 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
ESTE PROCESO DE CONTROL DE MODO DE FUNCIONAMIENTO DE UN BUCLE DE BLOQUEO DE FASE DIGITAL QUE COMPRENDE UN CONTADOR DE CONTROL DE INCREMENTO O DECREMENTO DE LA FRECUENCIA DE UNA SEÑAL DE RELOJ DIGITAL INTERNA DE ESTE BUCLE, ES TAL QUE, LA SEÑAL DE ENTRADA DE DICHO BUCLE QUE ESTA PRESENTE INTERMITENTEMENTE, COMPRENDE EN ORDEN, LAS SIGUIENTES ETAPAS: NICIO DE PRESENCIA DE DICHA SEÑAL DE ENTRADA, NA ZONA DE RECUENTO DE DICHO CONTADOR QUE TIENE UN VALOR RELATIVAMENTE PEQUEÑO PARA PERMITIR UN ENGANCHE RELATIVAMENTE RAPIDO DE DICHO BUCLE, ECCION DE UNA ZONA DE RECUENTO DE DICHO CONTADOR QUE TIENE UN VALOR RELATIVAMENTE FUERTE, PARA FILTRAR RELATIVAMENTE FUERTEMENTE LAS EVENTUALES VARIACIONES DE FASE DE DICHA SEÑAL DE ENTRADA QUE SE PRODUCEN DURANTE DICHA PRESENCIA, CONSERVANDOSE ESTE ULTIMO AJUSTE HASTA LA PROXIMA DETECCION DE UN INICIO DE PRESENCIA DE LA SEÑAL DE ENTRADA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9112265A FR2682236B1 (fr) | 1991-10-04 | 1991-10-04 | Procede et dispositif de commande de mode de fonctionnement d'une boucle a verrouillage de phase numerique |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2104871T3 true ES2104871T3 (es) | 1997-10-16 |
Family
ID=9417617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES92402653T Expired - Lifetime ES2104871T3 (es) | 1991-10-04 | 1992-09-28 | Procedimiento y dispositivo de control de modo de funcionamiento de un bucle de enclavamiento de fase numerica. |
Country Status (8)
Country | Link |
---|---|
US (1) | US5268653A (es) |
EP (1) | EP0541408B1 (es) |
JP (1) | JP2710901B2 (es) |
AT (1) | ATE157491T1 (es) |
CA (1) | CA2079762C (es) |
DE (1) | DE69221818T2 (es) |
ES (1) | ES2104871T3 (es) |
FR (1) | FR2682236B1 (es) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3241079B2 (ja) * | 1992-02-24 | 2001-12-25 | 株式会社日立製作所 | ディジタル位相同期回路 |
JP2964912B2 (ja) * | 1995-04-28 | 1999-10-18 | 日本電気株式会社 | デジタルpll |
US6570947B1 (en) | 1999-09-24 | 2003-05-27 | Motorola, Inc. | Phase lock loop having a robust bandwidth and a calibration method thereof |
US6181168B1 (en) | 1999-09-24 | 2001-01-30 | Motorola, Inc. | High speed phase detector and a method for detecting phase difference |
US6208211B1 (en) | 1999-09-24 | 2001-03-27 | Motorola Inc. | Low jitter phase locked loop having a sigma delta modulator and a method thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3989931A (en) * | 1975-05-19 | 1976-11-02 | Rockwell International Corporation | Pulse count generator for wide range digital phase detector |
US4316152A (en) * | 1979-09-24 | 1982-02-16 | Hewlett-Packard Company | Data tracking phase locked loop |
US4587496A (en) * | 1984-09-12 | 1986-05-06 | General Signal Corporation | Fast acquisition phase-lock loop |
IT1184024B (it) * | 1985-12-17 | 1987-10-22 | Cselt Centro Studi Lab Telecom | Perfezionamenti ai circuiti ad aggancio di fase numerici |
JPS62232219A (ja) * | 1986-04-01 | 1987-10-12 | Sanyo Electric Co Ltd | デジタル位相同期回路 |
JPS6468127A (en) * | 1987-09-09 | 1989-03-14 | Nec Corp | Oscillation circuit |
JPH0338673A (ja) * | 1989-07-06 | 1991-02-19 | Dai Ichi Kasei Kk | マグネットローラの製造方法 |
-
1991
- 1991-10-04 FR FR9112265A patent/FR2682236B1/fr not_active Expired - Fee Related
-
1992
- 1992-09-28 EP EP92402653A patent/EP0541408B1/fr not_active Expired - Lifetime
- 1992-09-28 AT AT92402653T patent/ATE157491T1/de not_active IP Right Cessation
- 1992-09-28 ES ES92402653T patent/ES2104871T3/es not_active Expired - Lifetime
- 1992-09-28 DE DE69221818T patent/DE69221818T2/de not_active Expired - Fee Related
- 1992-10-01 US US07/955,261 patent/US5268653A/en not_active Expired - Fee Related
- 1992-10-02 CA CA002079762A patent/CA2079762C/fr not_active Expired - Fee Related
- 1992-10-05 JP JP4266316A patent/JP2710901B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0541408A1 (fr) | 1993-05-12 |
FR2682236A1 (fr) | 1993-04-09 |
DE69221818T2 (de) | 1998-01-02 |
US5268653A (en) | 1993-12-07 |
DE69221818D1 (de) | 1997-10-02 |
JPH05243981A (ja) | 1993-09-21 |
CA2079762A1 (fr) | 1993-04-05 |
JP2710901B2 (ja) | 1998-02-10 |
FR2682236B1 (fr) | 1997-01-03 |
ATE157491T1 (de) | 1997-09-15 |
CA2079762C (fr) | 1999-08-03 |
EP0541408B1 (fr) | 1997-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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