ES2046209T3 - Estructura de contacto a tope de area reducida. - Google Patents
Estructura de contacto a tope de area reducida.Info
- Publication number
- ES2046209T3 ES2046209T3 ES87310857T ES87310857T ES2046209T3 ES 2046209 T3 ES2046209 T3 ES 2046209T3 ES 87310857 T ES87310857 T ES 87310857T ES 87310857 T ES87310857 T ES 87310857T ES 2046209 T3 ES2046209 T3 ES 2046209T3
- Authority
- ES
- Spain
- Prior art keywords
- polysilicon
- layers
- doped silicon
- silicon region
- etch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Air Bags (AREA)
- Installation Of Indoor Wiring (AREA)
- Multi-Conductor Connections (AREA)
- Connector Housings Or Holding Contact Members (AREA)
Abstract
ESTRUCTURA DE CONTACTO A TOPE DE AREA REDUCIDA (10'') QUE SE PROVEE, LA CUAL ES ESPECIALMENTE ADECUADA PARA CELULAS RAM ESTATICAS DE CUATRO TRANSISTORES. SE FORMA UNA ESTRUCTURA LA CUAL INCLUYE UNA REGION DOPADA DE SILICONA Y UNA O MAS CAPAS DE POLISILICONA Y OXIDO COLOCADAS ALLI ENCIMA, PUDIENDO SER UNA DE LAS CAPAS DE POLISILICONA UNA POLISILICONA DE PUERTA. ENTONCES SE REALIZA UN GRABADO POR ATAQUE QUIMICO ANISOTROPICO A TRAVES DE TODAS LAS CAPAS SUPERIORES INCLUYENDO ALGUNA CAPA SUPERIOR DE POLISILICONA LA CUAL PUEDE PRESENTARSE, PERO PARANDO EN LA REGION DOPADA DE SILICONA Y SE PRESENTA ALGUNA CAPA DE POLISILICONA DE LAS PUERTAS, PARA FORMAR UN ORIFICIO DE CONTACTO (26''). EL ORIFICIO DE CONTACTO SE LLENA CON UNA TOMA CONDUCTIVA (32) DE UN MATERIAL TAL COMO TUNGSTENO O POLISILICONA Y QUE ESTA ATACADO POR DETRAS. EN OTRO CASO, SE HACE EL CONTACTO CON TODAS LAS CAPAS DE POLISILICONA PRESENTES Y LA REGION DE SILICONA DOPADA. EN EL PROCESO DE ATAQUE ANISOTROPICO, SE EMPLEA UN ATAQUE EN DOS ETAPAS. EL PRIMER ATAQUE NO ES ESPECIFICO COMO DE UN MATERIAL, ATACANDO TODOS LOS MATERIALES (POLISILICONA Y OXIDO) EN LA MISMA TASA SUBSTANCIALMENTE Y ES CONTINUADO A TRAVES DE ALGUNA CAPA SUPERIOR DE POLISILICONA, PERO SE TERMINA ANTES DE ATACAR LA REGION DE SILICONA DOPADA O ALGUNA DE LAS CAPAS DE POLISILICONA DE LAS PUERTAS (22). EL SEGUNDO ATAQUE ES ESPECIFICO COMO DE UN MATERIAL, ATACANDO EL DIOXIDO DE SILICONA MAS RAPIDO QUE A LA POLISILICONA O A LA SILICONA, Y ASI PARA EN LA CAPA DE POLISILICONA DE LAS PUERTAS Y EN LA REGION DE SILICONA DOPADA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US94415086A | 1986-12-17 | 1986-12-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2046209T3 true ES2046209T3 (es) | 1995-04-01 |
Family
ID=25480890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES87310857T Expired - Lifetime ES2046209T3 (es) | 1986-12-17 | 1987-12-10 | Estructura de contacto a tope de area reducida. |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0272051B1 (es) |
JP (1) | JPH0752751B2 (es) |
AT (1) | ATE80750T1 (es) |
DE (1) | DE3781778T2 (es) |
ES (1) | ES2046209T3 (es) |
GR (1) | GR3005727T3 (es) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02202054A (ja) * | 1989-01-31 | 1990-08-10 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
NL9100094A (nl) * | 1991-01-21 | 1992-08-17 | Koninkl Philips Electronics Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
GB9219268D0 (en) * | 1992-09-11 | 1992-10-28 | Inmos Ltd | Semiconductor device incorporating a contact and manufacture thereof |
WO2003023847A2 (en) * | 2001-09-13 | 2003-03-20 | Koninklijke Philips Electronics N.V. | Integrated circuit, portable device and method for manufacturing an integrated circuit |
DE102008045037B4 (de) * | 2008-08-29 | 2010-12-30 | Advanced Micro Devices, Inc., Sunnyvale | Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5842257A (ja) * | 1981-09-07 | 1983-03-11 | Toshiba Corp | 半導体装置 |
JPS59171140A (ja) * | 1983-03-17 | 1984-09-27 | Nec Corp | 半導体装置 |
US4663831A (en) * | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
-
1987
- 1987-12-10 DE DE8787310857T patent/DE3781778T2/de not_active Expired - Lifetime
- 1987-12-10 AT AT87310857T patent/ATE80750T1/de not_active IP Right Cessation
- 1987-12-10 ES ES87310857T patent/ES2046209T3/es not_active Expired - Lifetime
- 1987-12-10 EP EP87310857A patent/EP0272051B1/en not_active Expired - Lifetime
- 1987-12-16 JP JP62320042A patent/JPH0752751B2/ja not_active Expired - Lifetime
-
1992
- 1992-09-17 GR GR920402050T patent/GR3005727T3/el unknown
Also Published As
Publication number | Publication date |
---|---|
EP0272051A3 (en) | 1989-02-01 |
ATE80750T1 (de) | 1992-10-15 |
EP0272051B1 (en) | 1992-09-16 |
DE3781778D1 (de) | 1992-10-22 |
JPH0752751B2 (ja) | 1995-06-05 |
GR3005727T3 (es) | 1993-06-07 |
EP0272051A2 (en) | 1988-06-22 |
DE3781778T2 (de) | 1993-01-28 |
JPS63164359A (ja) | 1988-07-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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