GR3005727T3 - - Google Patents

Info

Publication number
GR3005727T3
GR3005727T3 GR920402050T GR920402050T GR3005727T3 GR 3005727 T3 GR3005727 T3 GR 3005727T3 GR 920402050 T GR920402050 T GR 920402050T GR 920402050 T GR920402050 T GR 920402050T GR 3005727 T3 GR3005727 T3 GR 3005727T3
Authority
GR
Greece
Prior art keywords
polysilicon
layers
doped silicon
silicon region
etch
Prior art date
Application number
GR920402050T
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GR3005727T3 publication Critical patent/GR3005727T3/el

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Air Bags (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Installation Of Indoor Wiring (AREA)
  • Multi-Conductor Connections (AREA)
  • Connector Housings Or Holding Contact Members (AREA)
GR920402050T 1986-12-17 1992-09-17 GR3005727T3 (el)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US94415086A 1986-12-17 1986-12-17

Publications (1)

Publication Number Publication Date
GR3005727T3 true GR3005727T3 (el) 1993-06-07

Family

ID=25480890

Family Applications (1)

Application Number Title Priority Date Filing Date
GR920402050T GR3005727T3 (el) 1986-12-17 1992-09-17

Country Status (6)

Country Link
EP (1) EP0272051B1 (el)
JP (1) JPH0752751B2 (el)
AT (1) ATE80750T1 (el)
DE (1) DE3781778T2 (el)
ES (1) ES2046209T3 (el)
GR (1) GR3005727T3 (el)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202054A (ja) * 1989-01-31 1990-08-10 Texas Instr Japan Ltd 半導体装置及びその製造方法
NL9100094A (nl) * 1991-01-21 1992-08-17 Koninkl Philips Electronics Nv Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting.
GB9219268D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Semiconductor device incorporating a contact and manufacture thereof
WO2003023847A2 (en) * 2001-09-13 2003-03-20 Koninklijke Philips Electronics N.V. Integrated circuit, portable device and method for manufacturing an integrated circuit
DE102008045037B4 (de) * 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842257A (ja) * 1981-09-07 1983-03-11 Toshiba Corp 半導体装置
JPS59171140A (ja) * 1983-03-17 1984-09-27 Nec Corp 半導体装置
US4663831A (en) * 1985-10-08 1987-05-12 Motorola, Inc. Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers

Also Published As

Publication number Publication date
JPH0752751B2 (ja) 1995-06-05
ES2046209T3 (es) 1995-04-01
EP0272051B1 (en) 1992-09-16
EP0272051A3 (en) 1989-02-01
ATE80750T1 (de) 1992-10-15
DE3781778D1 (de) 1992-10-22
DE3781778T2 (de) 1993-01-28
EP0272051A2 (en) 1988-06-22
JPS63164359A (ja) 1988-07-07

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