JPS6419770A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6419770A
JPS6419770A JP62176109A JP17610987A JPS6419770A JP S6419770 A JPS6419770 A JP S6419770A JP 62176109 A JP62176109 A JP 62176109A JP 17610987 A JP17610987 A JP 17610987A JP S6419770 A JPS6419770 A JP S6419770A
Authority
JP
Japan
Prior art keywords
formation
accomplished
active layer
diffusion layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62176109A
Other languages
Japanese (ja)
Inventor
Masumitsu Ino
Taketo Osada
Masumi Shimada
Masaki Hiroi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP62176109A priority Critical patent/JPS6419770A/en
Publication of JPS6419770A publication Critical patent/JPS6419770A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent a 'penetration phenomenon' attributable to the silification of an active layer and to reduce parasitic resistance by a method wherein no direct contact is allowed to be present between a metal such as Al constituting a source or drain electrode and diffusion layers and a conductive non-metal layer is provided between them. CONSTITUTION:An active layer 2 is formed of polycrystalline Si or singlecrystal Si on a transparent insulating substrate 1, which is followed by patterning. Thermal oxidation is accomplished on the active layer 2 for the formation of a gate oxide film 4, whereon a gate electrode region is built of a polycrystalline Si layer, to be patterned into a gate electrode. An ion implanter is next used for the formation of diffusion layers 3, 3', and 3''. Activation is then accomplished in an N2 atmosphere. Spattering is next used for the formation of MoSi layers 9 and 9'. The ion implanter is employed again for the formation of richly doped n<+> diffusion layers 10 and 10'. Activation therefor is accomplished in an O2 atmosphere. An SiO2 interlayer insulating film 6 is formed, and a contact hole is provided by using the conventional technique. Finally, a source electrode 7 and a drain electrode 8 are formed of Al.
JP62176109A 1987-07-14 1987-07-14 Semiconductor device Pending JPS6419770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176109A JPS6419770A (en) 1987-07-14 1987-07-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176109A JPS6419770A (en) 1987-07-14 1987-07-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6419770A true JPS6419770A (en) 1989-01-23

Family

ID=16007848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176109A Pending JPS6419770A (en) 1987-07-14 1987-07-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6419770A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999690A (en) * 1989-12-19 1991-03-12 Texas Instruments Incorporated Transistor
US5231296A (en) * 1989-12-19 1993-07-27 Texas Instruments Incorporated Thin film transistor structure with insulating mask
US11014845B2 (en) 2014-12-04 2021-05-25 Corning Incorporated Method of laser cutting glass using non-diffracting laser beams

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999690A (en) * 1989-12-19 1991-03-12 Texas Instruments Incorporated Transistor
US5231296A (en) * 1989-12-19 1993-07-27 Texas Instruments Incorporated Thin film transistor structure with insulating mask
US11014845B2 (en) 2014-12-04 2021-05-25 Corning Incorporated Method of laser cutting glass using non-diffracting laser beams

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