ES2004607A6 - Procedimiento para la produccion de dispositivos transistores en areas seleccioadas de una lamina semiconductora - Google Patents

Procedimiento para la produccion de dispositivos transistores en areas seleccioadas de una lamina semiconductora

Info

Publication number
ES2004607A6
ES2004607A6 ES8701169A ES8701169A ES2004607A6 ES 2004607 A6 ES2004607 A6 ES 2004607A6 ES 8701169 A ES8701169 A ES 8701169A ES 8701169 A ES8701169 A ES 8701169A ES 2004607 A6 ES2004607 A6 ES 2004607A6
Authority
ES
Spain
Prior art keywords
stacks
layer
over
elements
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8701169A
Other languages
English (en)
Inventor
Tzu-Yin Chiu
Gen Man Chin
Ronald Curtis Hanson
Maureen Ylau
Kwing Fai Lee
Mark D Morris
Alexander Micha Voshchenkov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of ES2004607A6 publication Critical patent/ES2004607A6/es
Expired legal-status Critical Current

Links

Classifications

    • H01L21/82—
    • H01L29/41783—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H01L21/8249—
    • H01L27/0623—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

UN PROCEDIMIENTO PARA FABRICAR TRANSISTORES BIPOLARES Y CMOS SOBRE UN SUSTRATO DE SILICIO DEL TIPO P-. EL SUSTRATO DE SILICIO TIENE LOS POZOS ENTERRADOS N+ HABITUALES Y REGIONES DE OXIDO DE CAMPO PARA AISLAR LOS DISPOSITIVOS TRANSISTORES INDIVIDUALES. DE ACUERDO CON EL PROCEDIMIENTO, SE CREAN PILAS DE MATERIAL SOBRE LOS ELEMENTOS DE PUERTA DE LOS DISPOSITIVOS CMOS Y SOBRE LOS ELEMENTOS EMISORES DE LOS TRANSISTORES BIPOLARES. LAS PILAS DE MATERIAL SOBRE LOS ELEMENTOS DE PUERTA TIENEN UNA CAPA DE PUERTA DE DIOXIDO DE SILICIO EN CONTACTO CON LA CAPA EPITAXIAL DEL SUSTRATO Y LAS PILAS DE MATERIAL, SOBRE LOS ELEMENTOS EMISORES, TIENEN UNA CAPA DE SILICIO POLICRISTALINO EN CONTACTO CON LA CAPA EPITAXIAL. SE CREAN PAREDES DE DIOXIDO DE SILICIO ALREDEDOR DE LAS PILAS CON EL FIN DE AISLAR EL MATERIAL DENTRO DE LAS PILAS DEL MATERIAL DEPOSITADO FUERA DE LAS PAREDES. FUERA DE LAS PAREDES QUE RODEAN A LAS PILAS, SE DEPOSITA SILICIO POLICRISTALINO EN CONTACTO CON LA CAPA EPITAXIAL. TODAS LAS CAPAS DE SILICIO POLICRISTALINO EN CONTACTO CON LA CAPA EPITAXIAL SON INJERTADAS CON DOPANTES ADECUADOS, DE MANERA QUE ESTAS CAPAS SIRVAN COMO DEPOSITOS DE DOPANTE CON EL FIN DE CREAR SIMULTANEAMENTE LOS ELEMENTOS DE FUENTE Y DRENAJE DE LOS DISPOSITIVOS CMOS Y LOS ELEMENTOS EMISORES DE LOS DISPOSITIVOS BIPOLARES DURANTE UNA FASE DE CALENTAMIENTO DEL PROCESO. SE DEPOSITA UNA CAPA DE TUNGSTENO SOBRE LA CAPA POLICRISTALINA CON EL FIN DE PROPORCIONAR UN ACOPLAMIENTO CONDUCTOR A ELECTRODOS DE ALUMINIO.
ES8701169A 1986-04-23 1987-04-22 Procedimiento para la produccion de dispositivos transistores en areas seleccioadas de una lamina semiconductora Expired ES2004607A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US85488586A 1986-04-23 1986-04-23

Publications (1)

Publication Number Publication Date
ES2004607A6 true ES2004607A6 (es) 1989-01-16

Family

ID=25319783

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8701169A Expired ES2004607A6 (es) 1986-04-23 1987-04-22 Procedimiento para la produccion de dispositivos transistores en areas seleccioadas de una lamina semiconductora

Country Status (8)

Country Link
US (2) US4784971A (es)
EP (1) EP0265489B1 (es)
JP (1) JP2537936B2 (es)
KR (1) KR910002831B1 (es)
CA (2) CA1271566A1 (es)
DE (1) DE3767431D1 (es)
ES (1) ES2004607A6 (es)
WO (1) WO1987006764A1 (es)

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Also Published As

Publication number Publication date
KR910002831B1 (ko) 1991-05-06
KR880701461A (ko) 1988-07-27
CA1271566A1 (en) 1990-07-10
US4784971A (en) 1988-11-15
WO1987006764A1 (en) 1987-11-05
JP2537936B2 (ja) 1996-09-25
US4824796A (en) 1989-04-25
DE3767431D1 (de) 1991-02-21
CA1273128C (es) 1990-08-21
CA1273128A (en) 1990-08-21
JPS63503185A (ja) 1988-11-17
EP0265489B1 (en) 1991-01-16
EP0265489A1 (en) 1988-05-04

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Effective date: 20041102