ES2000270A6 - Perfeccionamientos introducidos en un aparato de n etapas para desarrollar el complemento aritmetico de valores binarios de n bits. - Google Patents
Perfeccionamientos introducidos en un aparato de n etapas para desarrollar el complemento aritmetico de valores binarios de n bits.Info
- Publication number
- ES2000270A6 ES2000270A6 ES8600198A ES8600198A ES2000270A6 ES 2000270 A6 ES2000270 A6 ES 2000270A6 ES 8600198 A ES8600198 A ES 8600198A ES 8600198 A ES8600198 A ES 8600198A ES 2000270 A6 ES2000270 A6 ES 2000270A6
- Authority
- ES
- Spain
- Prior art keywords
- circuitry
- stage
- input
- bit
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3832—Less usual number representations
- G06F2207/3836—One's complement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4816—Pass transistors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Logic Circuits (AREA)
- Electrophonic Musical Instruments (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Details Of Television Scanning (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
- Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
- Developing Agents For Electrophotography (AREA)
- Amplifiers (AREA)
- Mobile Radio Communication Systems (AREA)
- Radar Systems Or Details Thereof (AREA)
- Manipulation Of Pulses (AREA)
Abstract
SE DESCRIBE UN APARATO QUE COMPRENDE UNA DISPOSICION DE CIRCUITO PARA FORMAR EL COMPLEMENTO A DOSES O EL COMPLEMENTO A UNOS DE NUMEROS BINARIOS DE N BITIOS. LA DISPOSICION DE CIRCUITO INCLUYE N ETAPAS, CADA UNA DE LAS CUALES CONTIENE UNA PUERTA NOR (NO-O) EXCLUSIVA. UN PRIMER TERMINAL DE ENTRADA DE LA PUERTA NOR EXCLUSIVA ESTA ACOPLADO PARA RECIBIR UN BITIO DEL VALOR DE ENTRADA Y UN SEGUNDO TERMINAL DE ENTRADA ESTA ACOPLADO PARA RECIBIR LA SEÑAL DE SALIDA PORTADORA DE LA ETAPA ANTERIOR. SE APLICA EN UNO LOGICO O UN CERO LOGICO AL SEGUNDO TERMINAL DE ENTRADA DE LA ETAPA QUE PROCESA EL BITIO MENOS SIGNIFICATIVO DE LA PALABRA BINARIA SI LA DISPOSICION DE CIRCUITO ES PARA PROPORCIONAR UN VALOR DE COMPLEMENTO A DOSES O DE COMPLEMENTO A UNOS, RESPECTIVAMENTE. TAMBIEN SE DESCRIBE LA APLICACION DE LA DISPOSICION DE CIRCUITO EN UN CIRCUITO DE VALORES ABSOLUTOS, COMPLEMENTANDOSE SOLO LOS VALORES NEGATIVOS Y QUEDANDO SIN MODIFICAR LOS VALORES POSITIVOS.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/755,011 US4709226A (en) | 1985-07-15 | 1985-07-15 | Circuitry for complementing binary numbers |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2000270A6 true ES2000270A6 (es) | 1988-02-01 |
Family
ID=25037332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES8600198A Expired ES2000270A6 (es) | 1985-07-15 | 1986-07-09 | Perfeccionamientos introducidos en un aparato de n etapas para desarrollar el complemento aritmetico de valores binarios de n bits. |
Country Status (10)
Country | Link |
---|---|
US (1) | US4709226A (es) |
EP (1) | EP0209308B1 (es) |
JP (1) | JPH0785221B2 (es) |
KR (1) | KR940008612B1 (es) |
AT (1) | ATE68275T1 (es) |
AU (1) | AU589982B2 (es) |
CA (1) | CA1246234A (es) |
DE (1) | DE3681840D1 (es) |
ES (1) | ES2000270A6 (es) |
FI (1) | FI862883A (es) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6478029A (en) * | 1987-09-18 | 1989-03-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
JP2558739B2 (ja) * | 1987-09-28 | 1996-11-27 | 株式会社東芝 | 絶対値回路 |
US5307474A (en) * | 1987-09-30 | 1994-04-26 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for processing literal operand computer instructions |
JPH0774989B2 (ja) * | 1988-01-18 | 1995-08-09 | 株式会社東芝 | 符号変換回路 |
US5018094A (en) * | 1988-08-30 | 1991-05-21 | Siemens Aktiengesellschaft | Dual incrementer |
US5237513A (en) * | 1989-11-20 | 1993-08-17 | Massachusetts Institute Of Technology | Optimal integrated circuit generation |
US5162796A (en) * | 1990-07-31 | 1992-11-10 | Inmos Limited | Digital signal inversion employing cross-over switch |
US5268858A (en) * | 1991-08-30 | 1993-12-07 | Cyrix Corporation | Method and apparatus for negating an operand |
JPH0580982A (ja) * | 1991-09-19 | 1993-04-02 | Nec Corp | 絶対値回路 |
US5548542A (en) * | 1992-08-14 | 1996-08-20 | Harris Corporation | Half-band filter and method |
KR950009682B1 (ko) * | 1993-04-30 | 1995-08-26 | 현대전자산업주식회사 | 병렬 증분기를 이용한 2의 보수기 |
US5563813A (en) * | 1994-06-01 | 1996-10-08 | Industrial Technology Research Institute | Area/time-efficient motion estimation micro core |
US5856936A (en) * | 1996-09-24 | 1999-01-05 | Samsung Semiconductor, Inc. | Calculating A - sign(A) in a single instruction cycle |
US5835394A (en) * | 1996-09-24 | 1998-11-10 | Samsung Electronics Co., Ltd. | Calculating selected sign 3 expression in a single instruction cycle |
US5831886A (en) * | 1996-09-24 | 1998-11-03 | Samsung Electronics Co., Ltd. | Calculating a + sign(A) in a single instruction cycle |
US5831887A (en) * | 1996-09-24 | 1998-11-03 | Samsung Electronics Co., Ltd. | Calculating 2A-sign(A) in a single instruction cycle |
US5850347A (en) * | 1996-09-24 | 1998-12-15 | Samsung Semiconductor, Inc. | Calculating 2A+ sign(A) in a single instruction cycle |
KR100345413B1 (ko) * | 1999-11-05 | 2002-07-26 | 한국타이어 주식회사 | 고무압연장치 |
US6826588B2 (en) | 1999-12-23 | 2004-11-30 | Intel Corporation | Method and apparatus for a fast comparison in redundant form arithmetic |
US6813628B2 (en) | 1999-12-23 | 2004-11-02 | Intel Corporation | Method and apparatus for performing equality comparison in redundant form arithmetic |
DE10085322B4 (de) | 1999-12-23 | 2006-10-26 | Intel Corporation, Santa Clara | Schaltungsanordnung, Verfahren und Datenverarbeitungs-Einrichtung zum Durchführen einer Ein-Zyklus-Addition oder -Subtraktion und eines Vergleichs bei einer Arithmetik redundanter Form |
US20040015534A1 (en) * | 2002-07-17 | 2004-01-22 | Sun Microsystems, Inc. | Method for adding one to a binary number |
CN103929430A (zh) * | 2014-05-03 | 2014-07-16 | 郑卫兵 | 基于移动终端多媒体信息发送后的反馈方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3949299A (en) * | 1974-11-05 | 1976-04-06 | North Electric Company | Signal coding for telephone communication system |
JPS5320833A (en) * | 1976-08-11 | 1978-02-25 | Seiko Epson Corp | Absolute value arithmetic circuit |
US4357675A (en) * | 1980-08-04 | 1982-11-02 | Bell Telephone Laboratories, Incorporated | Ripple-carry generating circuit with carry regeneration |
US4369500A (en) * | 1980-10-20 | 1983-01-18 | Motorola Inc. | High speed NXM bit digital, repeated addition type multiplying circuit |
DE3069310D1 (en) * | 1980-11-03 | 1984-10-31 | Itt Ind Gmbh Deutsche | Binary mos ripple carry parallel adder/subtractor and appropriate adding/subtracting stage |
US4422143A (en) * | 1980-11-24 | 1983-12-20 | Texas Instruments Incorporated | Microprocessor ALU with absolute value function |
US4417315A (en) * | 1981-07-14 | 1983-11-22 | Rockwell International Corporation | Method and apparatus for incrementing a digital word |
US4486851A (en) * | 1982-07-01 | 1984-12-04 | Rca Corporation | Incrementing/decrementing circuit as for a FIR filter |
US4520347A (en) * | 1982-11-22 | 1985-05-28 | Motorola, Inc. | Code conversion circuit |
-
1985
- 1985-07-15 US US06/755,011 patent/US4709226A/en not_active Expired - Fee Related
-
1986
- 1986-06-25 CA CA000512390A patent/CA1246234A/en not_active Expired
- 1986-07-08 AU AU59831/86A patent/AU589982B2/en not_active Ceased
- 1986-07-08 FI FI862883A patent/FI862883A/fi not_active Application Discontinuation
- 1986-07-08 DE DE8686305249T patent/DE3681840D1/de not_active Expired - Fee Related
- 1986-07-08 EP EP86305249A patent/EP0209308B1/en not_active Expired - Lifetime
- 1986-07-08 AT AT86305249T patent/ATE68275T1/de active
- 1986-07-09 ES ES8600198A patent/ES2000270A6/es not_active Expired
- 1986-07-14 KR KR1019860005678A patent/KR940008612B1/ko not_active IP Right Cessation
- 1986-07-14 JP JP61163934A patent/JPH0785221B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE3681840D1 (de) | 1991-11-14 |
AU5983186A (en) | 1987-01-22 |
US4709226A (en) | 1987-11-24 |
FI862883A (fi) | 1987-01-16 |
ATE68275T1 (de) | 1991-10-15 |
EP0209308A2 (en) | 1987-01-21 |
EP0209308A3 (en) | 1988-07-13 |
KR870001516A (ko) | 1987-03-14 |
JPH0785221B2 (ja) | 1995-09-13 |
FI862883A0 (fi) | 1986-07-08 |
JPS6220028A (ja) | 1987-01-28 |
EP0209308B1 (en) | 1991-10-09 |
AU589982B2 (en) | 1989-10-26 |
KR940008612B1 (ko) | 1994-09-24 |
CA1246234A (en) | 1988-12-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19980504 |