EP4154306A1 - Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequences - Google Patents
Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequencesInfo
- Publication number
- EP4154306A1 EP4154306A1 EP21732481.3A EP21732481A EP4154306A1 EP 4154306 A1 EP4154306 A1 EP 4154306A1 EP 21732481 A EP21732481 A EP 21732481A EP 4154306 A1 EP4154306 A1 EP 4154306A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- layer
- semiconductor layer
- epitaxial
- electrically insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
Definitions
- the present invention relates to a method of manufacturing a semiconductor-on-insulator substrate for radiofrequency applications.
- Radio frequency electronic components formed in or on semiconductor substrates are particularly sensitive to attenuation phenomena caused by the properties of said substrates.
- semiconductor substrates in particular solid silicon, having a high electrical resistivity, that is to say greater than 500 Q.cm.
- semiconductor-on-insulator substrates of the FDSOI type (acronym of the English term “Fully Depleted Semiconductor On Insulator”, that is to say semiconductor on totally depleted insulator) appear as interesting alternatives to substrates.
- the FDSOI substrates successively comprise a support substrate, an electrically insulating layer and a thin semiconductor layer in or on which electronic components can be manufactured.
- the semiconductor layer has a sufficiently thin thickness to allow complete depletion of the conduction channel of a transistor formed in said layer.
- Such a layer typically has a thickness of a few tens of nanometers.
- the electrically insulating layer which generally consists of an oxide, is also frequently called BOX (acronym for the English term “Buried OXide” or buried oxide).
- BOX acronym for the English term "Buried OXide” or buried oxide.
- the manufacturing process for FDSOI substrates aims to ensure high precision of the thickness of the semiconductor layer and of the electrically insulating layer as well as high uniformity of these thicknesses, both within a substrate and a substrate. substrate to another within the same production batch.
- FIGS. 1 A to 1 C The process for manufacturing an FDSOI substrate is shown schematically in FIGS. 1 A to 1 C.
- This process implements a layer transfer from a donor substrate to a support substrate, also known under the name of the Smart Cut TM process.
- a donor substrate for example of silicon
- an electrically insulating layer for example of silicon oxide (S1O2).
- Said weakening zone 11 defines a thin layer 12 to be transferred.
- the donor substrate 1 thus implanted is glued on a support substrate 2 via the electrically insulating layer which then fulfills the function of a bonding layer.
- the support substrate 2 can advantageously be a semiconductor substrate, for example of silicon, with high electrical resistivity.
- the donor substrate 1 is detached along the weakening zone 11, which leads to the transfer of the thin layer 12 onto the support substrate 2.
- a finishing treatment is then carried out on the transferred layer, so as to cure the defects associated with the implantation and to smooth the free surface of said layer.
- a semiconductor-on-insulator substrate is thus obtained.
- the target thickness for the transferred semiconductor layer is between 4 nm and 100 nm, with a maximum variation of ⁇ 5 ⁇ from the target value, within each substrate and between the different substrates produced by the process.
- Such uniformity and a very low roughness of the transferred layer can be obtained by a so-called “batch anneal” finishing process, which is a long smoothing process, at high temperature, advantageously carried out in an oven making it possible to treat a plurality of substrates. the same time.
- Such a “batch anneal” is typically carried out at a temperature of between 1150 and 1200 ° C., for a period of several minutes, generally greater than 15 minutes. This smoothing makes it possible to bring the transferred semiconductor layer to a level of surface roughness compatible with the subsequent manufacture of transistors.
- this method is penalizing for radiofrequency applications, in particular for extremely high frequency applications, that is to say in a frequency band between 30 and 300 GHz.
- This frequency band is also called "mmWave”.
- the support substrate has high electrical resistivity and therefore lightly doped.
- the support substrate is generally substantially less doped (for example doped with boron) than the donor substrate, in other words, less doped than the transferred thin film.
- the boron atoms diffuse through the electrically insulating layer in the support substrate, leading to a reduction in the electrical resistivity in a surface portion extending from the electrically insulating layer.
- An aim of the invention is to define a method for manufacturing a semiconductor-on-insulator substrate of the FDSOI type suitable for radiofrequency applications, making it possible to maintain a high resistivity of the support substrate even in the vicinity of the electrically insulating layer.
- the invention provides a method of manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications, comprising the following steps:
- the dopants of the seed substrate are kept sufficiently far from the bonding interface by the epitaxial layer and the electrically insulating layer (which do not contain such dopants), so that they cannot diffuse into the support substrate.
- the electrical resistivity of the support substrate is not affected, even in its portion adjacent to the bonding interface.
- the undoped epitaxial semiconductor layer has a thickness between 10 and 1000 nm.
- the seed substrate is doped with boron.
- forming the electrically insulating layer includes thermal oxidation of the material of the undoped epitaxial semiconductor layer.
- the formation of the donor substrate comprises forming, between the seed substrate and the undoped epitaxial semiconductor layer, an intermediate layer of a material different from the material of the epitaxial semiconductor layer, chosen for allow selective etching of the undoped epitaxial layer relative to the intermediate layer.
- the material of the undoped epitaxial layer is silicon and the material of the intermediate layer is silicon-germanium with a germanium content less than or equal to 30%.
- the method comprises, after detachment, a selective etching of the remainder of the non-doped epitaxial semiconductor layer relative to the intermediate layer followed by selective etching of the intermediate layer relative to the seed substrate, and the formation of a new donor substrate by successive formation, on said seed substrate, of a new intermediate layer and of a new undoped epitaxial layer.
- the electrically insulating layer has a thickness between 10 and 150 nm.
- the transferred semiconductor layer has a thickness between 4 and 300 nm.
- FIG. 1A is a schematic sectional view of the implantation of atomic species through an electrically insulating layer arranged on a donor substrate;
- Figure 1B is a schematic sectional view of the bonding of the donor substrate having undergone the implantation of Figure 1A on a support substrate;
- Figure 1 C is a schematic sectional view of the transfer of a thin layer of the donor substrate on the support substrate of Figure 1 B;
- FIG. 2 is a schematic sectional view of the formation of a donor substrate by growing an undoped epitaxial layer on a doped seed substrate;
- FIG. 3 is a schematic sectional view of the formation of an electrically insulating layer on the epitaxial layer of Figure 2;
- FIG. 4 is a schematic sectional view of an alternative to Figures 2 and 3, comprising the growth of an intermediate layer between the seed substrate and the undoped layer;
- FIG. 5 is a schematic sectional view of the implantation of ionic species in the donor substrate of Figure 4 through the electrically insulating layer;
- FIG. 6 is a schematic sectional view of the bonding of the donor substrate of Figure 5 and a support substrate with high electrical resistivity;
- FIG. 7 is a schematic sectional view of the transfer of a thin layer from the donor substrate to the support substrate;
- Figure 8 is a schematic sectional view of a first recycling step of the remainder of the donor substrate resulting from the transfer of Figure 7;
- FIG. 9 is a schematic sectional view of a second step for recycling the remainder of the donor substrate
- FIG. 10 is a schematic sectional view of the growth of a new intermediate layer on the seed substrate resulting from recycling
- Figure 11 is a schematic sectional view of the growth by epitaxy of a new undoped semiconductor layer on the intermediate layer of Figure 10.
- the manufacturing process avoids the diffusion of dopants from the donor substrate into the support substrate by forming, on a P-doped seed substrate, conventionally used in the Smart Cut TM process, an undoped semiconductor epitaxial layer, the entire seed substrate. and the epitaxial layer forming the donor substrate, which is intended to receive an implantation of ionic species and to be bonded to the support substrate.
- the thickness of said epitaxial layer is greater than the thickness of the semiconductor layer to be transferred.
- the seed substrate which contains the dopants is separated from the support substrate by the epitaxial layer and by the electrically insulating layer which ensures the bonding between the donor substrate and the support substrate, which do not contain no such doping agents.
- Figure 2 illustrates the formation of donor substrate 1.
- Said donor substrate 1 comprises a seed substrate 100, made of a monocrystalline semiconductor material, such as silicon.
- Said seed substrate 100 has a concentration of P-type dopants, for example boron, of the order of 10 E 15 at / cm 3 .
- P-type dopants for example boron
- a monocrystalline semiconductor epitaxial layer 101 is grown by epitaxy on the seed substrate 100.
- the epitaxy conditions are chosen to avoid or at least minimize the presence of dopants in the layer 101.
- the dopant concentration of the layer 101 is less than the dopant content of the seed substrate 100.
- the dopant concentration of the layer 101 is less than 1 E 14 at / cm 3 and if possible of the order of 1 E 13 at / cm 3 .
- the material of said layer advantageously has a lattice parameter close to that of the seed substrate 100, the seed substrate serving as the seed for the growth of the monocrystalline layer 101.
- the epitaxial layer is formed from the same material (free of dopants) as the seed substrate.
- the undoped epitaxial semiconductor layer has a thickness between 10 and 1000 nm, greater than the thickness of the layer to be transferred by the Smart Cut TM process.
- Such a composite donor substrate makes it possible to limit the presence of dopants in the layer to be transferred from the donor substrate to the support substrate, at a cost lower than that of an undoped bulk substrate. Indeed, insofar as it is the epitaxy which imposes the crystalline quality of the layer to be transferred, it is possible to use a seed substrate of lower quality than that of the donor substrates traditionally used.
- an electrically insulating layer 10 is formed on the non-doped epitaxial semiconductor layer 101.
- Said layer 10 makes it possible in particular to minimize direct trajectories of the atomic species during implantation (a phenomenon known by the English term -saxon of "channeling").
- the layer 10 fulfills the function of a bonding layer between the donor substrate and the support substrate.
- the layer 10 is an oxide layer, so as to ensure good quality bonding with the semiconductor material of the support substrate.
- Layer 10 can in particular be formed by thermal oxidation of undoped epitaxial layer 101. As a result, layer 10 is substantially free of dopants.
- the undoped epitaxial layer 101 is not formed directly on the seed substrate 100, but on an intermediate layer 102 previously formed on the seed substrate 100.
- the intermediate layer 102 is a monocrystalline semiconductor layer made of a material different from that of the epitaxial layer. Said material is advantageously chosen to allow selective etching of the non-doped epitaxial layer 101 with respect to the intermediate layer 102, while having a lattice parameter sufficiently close to that of the layer 101 to allow the growth of the layer 101 with a good crystalline quality.
- the material of the undoped epitaxial layer 101 is silicon
- the material of the intermediate layer 102 is advantageously silicon-germanium with a germanium content of less than or equal to 30%.
- the intermediate layer 102 can be formed by epitaxy on the seed substrate 100.
- the material of the intermediate layer also has a lattice parameter sufficiently close to that of the seed substrate 100 to allow the growth of the intermediate layer 102 with good growth. crystalline quality.
- the thickness of the intermediate layer 102 can be between 10 and 100 nm.
- the electrically insulating layer 10 previously described with reference to FIG. 3 is formed on the non-doped epitaxial semiconductor layer 101.
- the donor substrate including the intermediate layer 102 which is shown, but it goes without saying that the description also applies to the embodiment where the donor substrate comprises the epitaxial layer formed directly. on the seed substrate, as shown in Figure 3.
- an implantation of ionic species (shown diagrammatically by the arrows) in the donor substrate is carried out through the electrically insulating layer 10.
- the implanted species typically include hydrogen and / or helium.
- the dose and energy of the implanted species are chosen to form an area of weakness 11 located in the undoped epitaxial layer 101.
- Said weakening zone 11 defines, in layer 101, a thin layer to be transferred 12.
- the thickness of said layer to be transferred 12 may be between 4 and 100 nm.
- the donor substrate 1 is bonded to a support substrate 2 through the electrically insulating layer 10.
- the support substrate 2 is a semiconductor substrate, for example of silicon, having a high electrical resistivity, for example greater than 500 Q.cm, preferably greater than or equal to 1000 Q.cm.
- the support substrate is a silicon substrate having a high content of interstitial oxygen, that is to say a content greater than 20 old ppma (for the definition of the old ppma unit, reference may be made to to the memoir of Robert Kurt Graupner, “A Study of Oxygen Precipitation in Heavily Doped Silicon” (1989), Dissertations and Theses, Paper 1218).
- Such a substrate is generally designated by the abbreviation "HiOi”.
- the interstitial oxygen atoms are liable to precipitate under the effect of a heat treatment so as to form a large quantity of defects, called “Bulk Micro Defects” (BMD), formed by the oxygen precipitates, which block the particles. dislocations generated during heat treatments at high temperature, which is advantageous for preserving the crystalline quality of the support substrate.
- the method comprises, prior to bonding, a step of heat treatment of the support substrate at a temperature sufficient to precipitate interstitial oxygen and form said BMDs.
- heat treatment can typically be achieved by a thermal cycle reaching a temperature of the order of 1000 ° C for 12 hours.
- a HiOi substrate generally comprises a large quantity of crystal defects called COPs (acronym for the English term “crystal originated particles”), which are undesirable in an FDSOI substrate.
- the manufacturing process therefore comprises a heat treatment of the "depletion" type, aimed at diffusing the oxygen out of the support substrate.
- this treatment can be carried out simultaneously with the heat treatment for precipitation of the interstitial oxygen, provided that the surface of the support substrate is free, that is to say not oxidized, to allow the oxygen to diffuse out. of the substrate.
- this precipitation / diffusion heat treatment must be carried out prior to the formation of the electrically insulating layer on the support substrate.
- the support substrate a silicon substrate having a low or medium content of interstitial oxygen, that is to say a content of less than 10 old ppma, respectively between 10 and 20. old ppma.
- a silicon substrate having a low or medium content of interstitial oxygen, that is to say a content of less than 10 old ppma, respectively between 10 and 20. old ppma.
- Such a substrate is generally designated by the abbreviation "LowOi”, respectively "MidOi”.
- the aforementioned precipitation and / or diffusion heat treatments are not necessary.
- the bonding can optionally be reinforced by a method of preparing the electrically insulating surface, for example by an oxygen plasma.
- the donor substrate 1 is detached along the weakening zone 11.
- said detachment can be caused by the application of a mechanical stress in the vicinity of the zone of weakening. embrittlement, by heat treatment or by any other suitable means.
- the thin layer 12 has been transferred from the donor substrate to the support substrate and an FDSOI structure is obtained comprising the support substrate 2, the electrically insulating bonding layer 10 and the transferred layer 12.
- This finishing treatment includes in particular thermal smoothing of the transferred layer (“batch anneal”) as mentioned in the introduction.
- this smoothing process consists in placing a batch of FDSOI structures in an oven, in carrying out a slow rise in temperature from room temperature (20 ° C) to a temperature of the order of 1500 to 1200 ° C, then maintaining the structures at this temperature for a period of several minutes, preferably greater than 15 minutes.
- the thermal budget of this smoothing process is high enough to allow diffusion of the dopants present in the structure, the dopants of the seed substrate have been kept sufficiently far from the bonding interface by the epitaxial layer
- the electrically insulating layer 10 (which do not contain such dopants) so as not to diffuse in the support substrate 2. Consequently, the electrical resistivity of the support substrate is not affected, even in its portion adjacent to the interface. lift-off.
- the FDSOI structure thus formed is therefore fully functional for radiofrequency applications, in particular in the mmWave band.
- the remainder 1 'of the donor substrate can be recycled in order to allow the formation of a new donor substrate which can be used for a new layer transfer.
- the remainder 1 'of the donor substrate comprises the seed substrate 100, the intermediate layer
- a first recycling step comprises a selective etching of the non-transferred portion 120 of the epitaxial layer 101 with respect to the intermediate layer 102.
- a wet etching can be implemented by means of a suitable engraving solution.
- a second recycling step comprises a selective etching of the intermediate layer 102 with respect to the seed substrate 100.
- a wet etching can be implemented by means of a suitable etching solution.
- a new donor substrate can be formed by successively forming, on said seed substrate 100, a new intermediate layer 102 ’(see figure 10) and a new epitaxial layer 101’ undoped (see figure 11).
- This recycling process is advantageous over the recycling of a donor substrate comprising the epitaxial layer directly on the seed substrate.
- the donor substrate comprises the intermediate layer, which fulfills the function of etching stopper layer, between the seed substrate and the epitaxial layer
- the recycling process can be simply based on etching steps, which do not consume not the material of the substrate germinates.
- the seed substrate can thus be reused indefinitely, which reduces the cost of obtaining the donor substrate.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2004971A FR3110283B1 (fr) | 2020-05-18 | 2020-05-18 | Procédé de fabrication d’un substrat semi-conducteur sur isolant pour applications radiofréquences |
PCT/FR2021/050870 WO2021234277A1 (fr) | 2020-05-18 | 2021-05-18 | Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequences |
Publications (1)
Publication Number | Publication Date |
---|---|
EP4154306A1 true EP4154306A1 (fr) | 2023-03-29 |
Family
ID=72178709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP21732481.3A Pending EP4154306A1 (fr) | 2020-05-18 | 2021-05-18 | Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequences |
Country Status (8)
Country | Link |
---|---|
US (1) | US20230207382A1 (ko) |
EP (1) | EP4154306A1 (ko) |
JP (1) | JP2023526902A (ko) |
KR (1) | KR20230011297A (ko) |
CN (1) | CN115552592A (ko) |
FR (1) | FR3110283B1 (ko) |
TW (1) | TW202147400A (ko) |
WO (1) | WO2021234277A1 (ko) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8101500B2 (en) * | 2007-09-27 | 2012-01-24 | Fairchild Semiconductor Corporation | Semiconductor device with (110)-oriented silicon |
FR2928775B1 (fr) * | 2008-03-11 | 2011-12-09 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semiconducteur sur isolant |
JP6447439B2 (ja) * | 2015-09-28 | 2019-01-09 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
-
2020
- 2020-05-18 FR FR2004971A patent/FR3110283B1/fr active Active
-
2021
- 2021-05-13 TW TW110117327A patent/TW202147400A/zh unknown
- 2021-05-18 US US17/998,833 patent/US20230207382A1/en active Pending
- 2021-05-18 JP JP2022565780A patent/JP2023526902A/ja active Pending
- 2021-05-18 WO PCT/FR2021/050870 patent/WO2021234277A1/fr unknown
- 2021-05-18 EP EP21732481.3A patent/EP4154306A1/fr active Pending
- 2021-05-18 KR KR1020227039462A patent/KR20230011297A/ko active Search and Examination
- 2021-05-18 CN CN202180034312.2A patent/CN115552592A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230207382A1 (en) | 2023-06-29 |
JP2023526902A (ja) | 2023-06-26 |
WO2021234277A1 (fr) | 2021-11-25 |
TW202147400A (zh) | 2021-12-16 |
FR3110283A1 (fr) | 2021-11-19 |
KR20230011297A (ko) | 2023-01-20 |
CN115552592A (zh) | 2022-12-30 |
FR3110283B1 (fr) | 2022-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1922752B1 (fr) | Procede de report d'une couche mince sur un support | |
EP3997728B1 (fr) | Procede de fabrication d'une structure comprenant une couche mince reportee sur un support muni d'une couche de piegeage de charges | |
FR2973159A1 (fr) | Procede de fabrication d'un substrat de base pour un substrat de type semi-conducteur sur isolant | |
FR3049763A1 (ko) | ||
EP3847693B1 (fr) | Procede de fabrication d'un dispositif cfet | |
FR2978603A1 (fr) | Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support | |
FR2880988A1 (fr) | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE | |
EP1938362A1 (fr) | Procede de fabrication d'un element en couches minces | |
FR3062238A1 (fr) | Support pour une structure semi-conductrice | |
FR3051596A1 (fr) | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant | |
EP1523771B1 (fr) | Procede de transfert d'une couche mince electriquement active. | |
EP3818561A1 (fr) | Substrat pour un dispositif integre radioafrequence et son procede de fabrication | |
WO2020128354A1 (fr) | Substrat de type semi-conducteur sur isolant pour des applications radiofréquences | |
FR3037438A1 (fr) | Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges | |
FR3051595A1 (fr) | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant | |
FR3116940A1 (fr) | Procédé basse température de fabrication d’un substrat semiconducteur sur isolant | |
EP4030467B1 (fr) | Procédé de collage direct hydrophile de substrats | |
EP4154306A1 (fr) | Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequences | |
EP4088312B1 (fr) | Procédé de fabrication d'une structure de type semi-conducteur sur isolant pour applications radiofréquences | |
FR3068506A1 (fr) | Procede pour preparer un support pour une structure semi-conductrice | |
EP4154307A1 (fr) | Procede de fabrication d'un substrat semi-conducteur sur isolant pour applications radiofrequences | |
FR3027451A1 (fr) | Substrat et procede de fabrication d'un substrat | |
FR2933235A1 (fr) | Substrat bon marche et procede de fabrication associe | |
WO2024156465A1 (fr) | Structure comprenant une couche superficielle reportee sur un support muni d'une couche de piegeage de charges a contamination limitee et procede de fabrication | |
EP4315396A1 (fr) | Procede de fabrication d'une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20221207 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) |