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  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
  • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
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  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
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  • H10W72/00—Interconnections or connectors in packages
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  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
  • H10W70/654—Top-view layouts
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  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/66—Conductive materials thereof
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  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
  • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01251—Changing the shapes of bumps
  • H10W72/01255—Changing the shapes of bumps by using masks
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01251—Changing the shapes of bumps
  • H10W72/01257—Changing the shapes of bumps by reflowing
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
  • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
  • H10W72/225—Bumps having a filler embedded in a matrix
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/231—Shapes
  • H10W72/234—Cross-sectional shape, i.e. in side view
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
• • H—ELECTRICITY
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/281—Auxiliary members
  • H10W72/287—Flow barriers
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
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  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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  • H10W90/00—Package configurations
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  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• SMT Surface Mounted Technology
• solderable bumps are used for electrical interconnection and mechanical connection between a carrier, e.g. B. a circuit board, and an electrical component, for. B. discrete components or modules used.
• the material of the bumps is in one step, z.
• solder paste may contain flux that attack the surface of the carrier when heated. Furthermore, there is a risk that solder paste gets to solderable surfaces that should remain free of solder, z. B. to avoid electrical short circuits.
• a protective layer eg. B. a solder stop layer, are covered.
• solder stop layer The problem with the use of a solder stop layer is the increased complexity in the manufacture of the components, since the solder stop layer must be structured so that in an optimal case, all sensitive areas, but not actually to be provided with Lot areas are covered by the protective layer. It also holds that electrical Components should have ever smaller dimensions. Conventional solder-stop layers are already so thick compared to current dimensions of bump connections that further problems can occur in further steps to encapsulate the devices. Many components are encapsulated and mechanically stabilized by pouring a mold over the top and then hardening the mass. The problem now is that the mold mass no longer sufficiently filled gaps between the component and the carrier when the gap is too low due to the thickness of the solder stop layer.
• a protective layer should there ⁇ at a good adhesion on the surface of the carrier aufwei ⁇ sen, high temperatures, eg. B. greater than 250 ° C in a reflow process, without enduring degradation, be mechanically stable, chemically neutral and passive and do not conduct the electric current.
• the protective layer should be as thin as possible.
• the electrical component comprises a carrier having an upper side, a metallized contact surface on the upper side and a solder stop layer covering a part of the upper side, but not the contact surface.
• the solder stop layer has a thickness of 200 nm or less.
• solder-stop layer has a thickness which Kgs ⁇ NEN even at the currently small dimensions of bump connections, thus gaps are still reliably filled small distances between the carrier and electrical component.
• the carrier can be a printed circuit board or a chip.
• the metallized contact surface is preferably a solderable metallized surface which is intended to be over a
• the metallized Kon ⁇ clock face may in particular be a so-called under- bump metallization, and in turn have a multilayer structure.
• solder-stop layer has a thickness Zvi ⁇ rule 30 nm and 80 nm.
• the device has a bump ball on the metallized contact surface.
• the bump ball on the metallized contact surface may then consist of a solder material that has been applied to the area of the metallized contact area by a stencil printing method. In a subsequent heating, the material melts and forms due to the Oberflä ⁇ chenschreib to form a relatively small surface, a ball.
• the metallized contact surface can with a further metallization on the top of the carrier, z. B. a signal line in the form of a stripline connected.
• a further metallization can be arranged on the upper side of the carrier.
• the two further metallizations next to the contact surface on the upper side of the carrier are covered by the solder stop layer.
• the solder stop layer may have poor solder wettability. Then, when heated, solder material automatically centers away from the region of poor wettability toward the metallized contact surface which is free of the material of the solder stop layer.
• the solder material and / or flux thereby engage emp ⁇ -sensitive areas on the upper side of the support not. Even if electrically conductive solder material remains on a Be ⁇ rich next to the contact surface, the solder stop layer acts as an electrical insulator and signal lines are not short-circuited.
• the component additionally comprises an electrical component.
• the electrical component may have a contact surface at the bottom.
• the Bauele ⁇ ment then further comprises a bump connection that connects the two contact surfaces.
• the carrier may have a plurality of further metallized contact surfaces on its surface.
• the device may also have a variety of different electrical components, which are connected and interconnected via bump connections with the metallized contact surfaces of the carrier, wherein each of the electrical compo ⁇ nents in turn have metallized contact surfaces on their lower sides.
• the electrical component or the electrical plurality ⁇ shear components may also each have a solder-stop layer on their undersides.
• the solder-stop layers of the electrical components can be conventional protective layers. They may also be solder stop layers of the type of protective layer present.
• the component when two protective layers are arranged between a component and the carrier, the advantage of the small thicknesses of the present protective layers comes into play, since the effect on the height of the free gap doubles. Accordingly, it is possible for the component to comprise a molding compound which covers at least parts of the top side of the carrier and at least one electrical component.
• the mold mass also fills the intermediate space between the electrical component and the carrier or between all electrical components and the carrier.
• a hermetically sealed volume between the component and the carrier remains free of the material of the mold mass.
• an additional frame structure can be arranged between the component and the carrier, which surrounds the cavity since ⁇ Lich. The cavity is then formed by the surfaces of the carrier and the component and by the frame.
• the component prefferably has a first signal line connected to the contact surface on the upper side of the contact surface
• Carrier comprises.
• the device further has a second Sig ⁇ naltechnisch at the top of the carrier.
• Both signal lines are at least partially be ⁇ covered by the solder-stop layer.
• the electrical resistance between the two signal lines is 100 ⁇ or more.
• the lateral distance between the signal lines can be of the order of 180 ym.
• the solder-stop layer has a thickness, which - is selected such that a minimum resistance of 100 ⁇ réellege ⁇ represents is - depending on the material of the layer.
• solder stop layer is silicon as
• Main component comprises or consists entirely of silicon.
• solder-stop layers of silicon or other material with similar electrical isolation properties can be made surprisingly easily using the method described below.
• all materials for the solder stop layer can be used that sufficiently provides a reasonable ⁇ accordingly low wettability by solder and a have low electrical conductivity. Is preferred that the materials with the usual Swisssme ⁇ methods such. As the semiconductor industry, can be deposited and adhere well to the top of the carrier.
• the solder stop layer can also include germanium as a main ingredient ⁇ part or consist of germanium.
• the solder stop layer can in principle consist of all dielectric materials. However, preference is given to those which can be deposited relatively easily as a correspondingly thin layer. These include in particular the materials that can be applied to surfaces in reactive or non-reactive PVD processes, for. For example, oxides and nitrides of silicon, titanium, aluminum or chromium.
• the component may have component structures on the upper side of the carrier or on the underside of at least one electrical component.
• the device structures may have a height of 40 ym or more.
• the component structures may be SAW component structures, BAW component structures, MEMS (micro-electro-mechanical system) device structures or GBAW devices.
• similar component ⁇ structures be.
• the carrier has on its upper side or the electrical component on its underside a com ⁇ plex topology, which are poor or not covered by conventional solder stop layers.
• the other solderable metal surfaces to be protected by the solder stop layer may be nickel, copper, Alloys of these two elements or alloys with these two elements, gold, silver, palladium, rhodium, tin, and / or zinc have.
• the number of contact surfaces, the electrical components and the contact surfaces of the electrical components is not limited in principle, especially in electrical components with integrated circuits, the electrical component and the carrier can be interconnected and connected over many hundreds of bump connections.
• the carrier is not limited to printed circuit boards.
• the carrier itself can an electrical component, which is arranged on ei ⁇ nem further carrier or a further electrical component, etc., and connected to be.
• a method for producing such an electrical component comprises the steps of: providing a carrier with an upper side and a metallized contact surface on the upper side,
• the lacquer layer may comprise a conventional material for photolithography processes and z. B. be applied by spin coating. After application of the material of the solder stop layer on the remaining portions of the structured varnish layer and on the vacant surfaces of the carrier, the material of the photoresist can be removed by stripping ⁇ ent. As a result, the structured solder stop layer in the form of the desired solder stop mask is produced without additional structuring of the material of the solder stop layer. This method reduces the complexity of the overall ⁇ process and the cost of manufacturing the device when compared with conventional methods.
• solder stop layer It is possible for the solder stop layer to have a thickness that is 200 nm or less.
• solder stop layer it is possible for the solder stop layer to have a thickness which is between 20 nm and 80 nm. It is possible that the formed during the process
• Lot stop layer comprises silicon or germanium as the main constituent ⁇ part or is completely made of silicon or germanium be ⁇ .
• Other materials with similar electrical properties and similar wettability are also possible.
• the electrical component has another solderable metal surface on the upper side and the solder stop layer is deposited directly onto the further solderable metal surface.
• the more solderable metal surface can be a metal surface ⁇ a signal line or a realized at the top of the carrier capacitive, inductive or re- sistiven element.
• the method comprises the steps
• Arranging solder paste at least on the contact surface, arranging an electrical component with a contact surface on its underside on the upper side of the carrier, reflowing the component and connecting the two contact surfaces by means of a bump connection,
• the method comprises the step of enveloping the electrical component with a mold mass.
• the mold mass also fills the area between the component and the carrier.
• the lacquer which is patterned prior to the application of the material of the solder-stop layer to form the solder-stop mask to preserver ⁇ th may ⁇ a thickness between 0.5 and 10 ⁇ , z. B. between ⁇ 2 ym and 4 ym, and have a standard paint semiconductor manufacturing be.
• the paint can be sprayed next to the spin on the top of the carrier who ⁇ .
• Fig. 1 a cross section through an electrical compo ⁇ ment
• Fig. 2 a cross section through a device with further
• FIG. 3 shows a cross section through a component with a
• Fig. 7 a fourth intermediate step
• Fig. 8 a first intermediate result in the production of egg ⁇ nes complex electrical component
• FIG. 9 shows a further intermediate step
• FIG. 10 shows a further intermediate step after heating
• FIG. 11 shows a cross section through a simple execution ⁇ form of the device
• Fig. 12 shows a cross section through an alternative exporting ⁇ approximate shape
• Fig. 13 shows a cross section through a component with a thin
• Lot stop layer and a mold mass that fills the gaps between the electrical component and the carrier are listed.
• FIG. 1 shows a cross section through a simple Ausure ⁇ tion form of the electrical component EB.
• the electrical component EB has a carrier TR, on which a metallized contact surface MK is structured.
• the metallized contact surface ⁇ MK is intended to be connected via a bump connection to an electrical component.
• a solder stop layer LSS is arranged on ⁇ which covers those areas of the top of the carrier TR, which should not come into direct contact with solder material.
• the metallized contact surface may be a so-called under-bump metallization UBM and have a good wettable surface.
• Figure 2 shows a cross section through a shape of a
• solder stop layer LSS reliably protects sensitive areas on the top side of the carrier TR against wetting with solder, if the top side of the carrier TR is sufficiently flat. If the component is to be encapsulated by a mold mass MM, provides a thick solder-stop layer LSS of all ⁇ recently an obstacle, that the filling of the gap Z between the bottom of the electrical component EK, the via bump connections BU connected to the carrier TR and is connected, and the carrier TR fills.
• Figure 3 shows a cross section through an electric element construction, in which a bump ball BU has already formed on the con tact surface ⁇ MK. Due to the surface tension of the solder, a ball-like structure at the pres ⁇ fen a reflow process formed. Compared with the height of the bump ball or the subsequent bump connection to an electrical component, the thickness of the solder stop layer LSS is very small.
• solderable surface LO On the surface of the support is a material with solderable surface LO, z. B. a signal line SL, which may include nickel, Kup ⁇ fer, gold or silver arranged.
• solder stop layer LSS there is a risk that the material of the bump ball BU does not collect on the contact surface MK, but attacks the signal conductor and optionally short-circuits the Sig ⁇ nalleiter and another circuit element at the top of the carrier.
• Figure 4 shows a cross section through a first stinkpro ⁇ domestic product in the production of the electrical component.
• the contact surface MK and the signal conductor SL are arranged as an example of elements to be protected on the upper side of the carrier TR.
• FIG. 5 shows a cross section through a further intermediate step, in which the entire surface, including the regions to be protected and the regions to be wetted later by the solder, are covered by a photoresist FL.
• FIG. 6 shows a cross section through a further intermediate step, in which the photoresist FL has been structured in such a way that that only the areas of MK, which should remain the material of the solder-stop layer later released, remain covered by the material of the photo ⁇ lacks FL. For this it is possible to selectively expose and develop the photoresist.
• FIG. 7 shows the result of a further intermediate step, in which the entire upper side of the previous electrical component is covered by the material of the later solder stop layer LSS.
• the sensitive areas are directly covered by the material of the solder stop layer LSS.
• solder is to be arranged later, is the ver ⁇ remaining residue of the photoresist FL between the material of the solder-stop layer LSS and the contact surface.
• Figure 8 shows the result of a further Ver ⁇ drive step in which the remaining radicals of the photo ⁇ lacks FL were removed along with the deposited thereon segments of the material of the solder-stop layer LSS so that the surface to be wetted without coverage by the Lot - Stop layer exposed.
• FIG. 9 shows the result of a further step, namely of applying a solder paste on LP regions corresponding in Wesent ⁇ union areas of the contact surfaces MK. Due to the precisely definable edges of the solder stop layer LSS, the lateral positioning accuracy when applying the solder paste LP need not be too high as long as a substantial area of the contact surface MK is covered by the solder paste LP.
• FIG. 10 shows the result of a further intermediate step in the production of the electrical component, in which the material of the solder paste LP after heating has concentrated to form a sphere at the location of the contact surface MK.
• Figure 11 shows a cross section through an electrical construction ⁇ element, in which the contact surface MK on the underside of the electrical component EK and the contact surface MK at the top of the carrier TR via a bump connection, which emerged from the bump ball of Figure 10 is connected.
• Figure 12 shows a cross section through a further exemplary embodiment in which the electrical component and the EK Trä ⁇ ger TR are connected via a plurality of bump connections BU and connected.
• a solder stop layer LSS which is preferably also thin, may be arranged on the underside of the electrical component EK.
• FIG. 13 shows a cross section through an encapsulated electrical component in which a molding compound MM envelopes the electrical component EK at the top side of the carrier TR and fills the gaps Z between the electrical component EK and the carrier TR.

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• Wire Bonding (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Geometry (AREA)
• Ceramic Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

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• 2015
  • 2015-11-27 DE DE102015120647.1A patent/DE102015120647B4/de active Active
• 2016
  • 2016-09-06 BR BR112018010666A patent/BR112018010666A8/pt not_active Application Discontinuation
  • 2016-09-06 KR KR1020187011776A patent/KR20180088798A/ko not_active Ceased
  • 2016-09-06 JP JP2018527165A patent/JP2018536994A/ja not_active Ceased
  • 2016-09-06 CN CN201680062169.7A patent/CN108369935A/zh active Pending
  • 2016-09-06 US US15/776,019 patent/US20180331062A1/en not_active Abandoned
  • 2016-09-06 EP EP16762778.5A patent/EP3381052A1/de not_active Withdrawn
  • 2016-09-06 WO PCT/EP2016/070973 patent/WO2017088998A1/de not_active Ceased

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