EP2887176B1 - Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action - Google Patents

Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action Download PDF

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Publication number
EP2887176B1
EP2887176B1 EP13198965.9A EP13198965A EP2887176B1 EP 2887176 B1 EP2887176 B1 EP 2887176B1 EP 13198965 A EP13198965 A EP 13198965A EP 2887176 B1 EP2887176 B1 EP 2887176B1
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EP
European Patent Office
Prior art keywords
current
ptat
nmos transistor
transistor
resistor
Prior art date
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Active
Application number
EP13198965.9A
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German (de)
English (en)
French (fr)
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EP2887176A1 (fr
Inventor
Arnaud Casagrande
Jean-Luc Arend
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Swatch Group Research and Development SA
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Swatch Group Research and Development SA
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Publication date
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Priority to EP13198965.9A priority Critical patent/EP2887176B1/fr
Priority to US14/558,839 priority patent/US9442509B2/en
Priority to TW103142196A priority patent/TWI675275B/zh
Priority to JP2014253730A priority patent/JP5918344B2/ja
Priority to CN201410784806.4A priority patent/CN104731148B/zh
Priority to KR1020140184793A priority patent/KR101749794B1/ko
Publication of EP2887176A1 publication Critical patent/EP2887176A1/fr
Priority to HK15112380.6A priority patent/HK1211715A1/xx
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Publication of EP2887176B1 publication Critical patent/EP2887176B1/fr
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type.
  • the invention also relates to the method for calibrating a current source of the PTAT type of the electronic circuit.
  • a PTAT type current is a current proportional to the absolute temperature.
  • Current sources of the PTAT type are used in electronic circuits for supplying at least one temperature-dependent current. They can also be used in electronic circuits with temperature sensor or in function management circuits in conjunction with a time base.
  • a conventional resistor is used in a current generation branch.
  • the precision of such a resistor can vary by ⁇ 30% with respect to an estimated value according to the manufacturing method, for example of the MOS type. Provision must often be made to calibrate such a resistor at the end of the manufacturing process in order to be able to ensure sufficient precision of a current reference of the PTAT type, which is a drawback.
  • the Master matching circuit is a phase-locked loop (PLL) circuit, which comprises a switched capacitor (SC) resistor in a first branch, and a replica MOS resistor in parallel in a second branch, and in connection with an integrator for supplying a control voltage to the variable resistor and the replica resistor.
  • PLL phase-locked loop
  • SC switched capacitor
  • MOS complementary metal-oxide-semiconductor
  • the object of the invention is therefore to provide an electronic circuit provided with a current reference of the self-calibrated PTAT type in order to improve the current reference precision independently of any variation in the manufacturing process of the electronic circuit and overcoming the aforementioned drawbacks of the state of the art.
  • the invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type, which comprises the characteristics mentioned in independent claim 1.
  • An advantage of the electronic circuit resides in the fact that it is possible to digitally adjust a resistor network for the generation of a PTAT current reference, by comparing an output current of a PTAT current generating unit with a reference current.
  • the reference current is generated in a reference current generator based on a switched capacitor equivalent resistance.
  • a calibration of the current reference PTAT of the electronic circuit can be carried out automatically as soon as the electronic circuit is put into operation. Calibration is performed by several successive comparisons of the PTAT output current with the reference current by dichotomy. The comparison can be performed in a comparator. An adaptation of the resistive value of the network of resistors or the value of the output current by paralleling transistors of a current mirror is controlled via a processing unit receiving the information from the comparator.
  • the reference unit which provides the reference current for comparison with the PTAT output current, can be disconnected.
  • Switched capacitor resistor switch timing signals which originate from a time base, are suppressed to reduce power consumption and avoid spectral pollution.
  • this PTAT current can be at least 2 to 3 times more accurate than such a current obtained with a standard built-in state-of-the-art resistor, while taking into account the errors of pairing of the current mirrors and the current comparator.
  • the invention also relates to a method for calibrating a current source of the PTAT type of the electronic circuit, which comprises the characteristics defined in independent claim 7.
  • the electronic circuit 1 comprises a so-called master unit for supplying a calibration reference current I ref , and a so-called slave unit 3 for supplying a current reference PTAT at output I OUT .
  • the master unit 2 is a calibration reference current generator I ref dependent on a switched capacitor resistor 12.
  • the PTAT slave unit 3 is a current generator for supplying a PTAT current reference at output I OUT .
  • the current reference PTAT supplied by the generator PTAT is dependent on a resistor 8, the resistive value of which R can be adjusted digitally as explained below. However, it is also possible to digitally adapt a dimensional ratio of transistors of a current mirror in the generator of the current PTAT for the supply of the adapted current PTAT.
  • a comparison in a comparator 6 is performed between the calibration reference current I ref of the master unit 2 and the output current PTAT I OUT of the slave unit 3.
  • the PTAT output current I OUT is identical to the reference current I ref .
  • the electronic circuit with resistor 8 is integrated into a semiconductor substrate, such as a silicon substrate, the resistive value of resistor 8 at the output of the MOS-type manufacturing process is not precise. Consequently, the output current PTAT I OUT is not identical to the current I ref .
  • the programmable resistor 8 is digitally matched. Programmable resistor 8 can be adapted to become equivalent to switched capacitor resistor 12. Depending on the comparison between the two currents, information at the output of the comparator 6 is supplied to a processing unit 7 so as to control a digital adaptation of the programmable resistor 8.
  • This programmable resistor 8 can be composed of a network of resistors and programmable switches.
  • the resistor network comprises several unit value resistors in series and/or also partly in parallel.
  • switches can be provided by being connected in parallel to each unit resistor or groups of unit resistors, which is well known. The switches are controlled by digital signals or a binary command word coming from the processing unit 7 so as to short-circuit a certain number of unit resistors to adapt the resistive value of the programmable resistor 8.
  • the processing unit 7 therefore provides a binary word to control the switches and adapt the programmable resistor.
  • a command binary word for example on 16 bits, can be provided so as to adjust said programmable resistor 8. This makes it possible to guarantee an accuracy of at least the order of ⁇ 5% with respect to the estimated resistance, whereas without calibration , the error of the programmable resistor can be close to ⁇ 30% as mentioned above. However, account must be taken in the precision of the pairing errors of the current mirrors and of the current comparator 6, which can reduce the precision somewhat.
  • a dichotomy algorithm is preferably used in the processing unit 7. This makes it possible to converge quickly towards a final value of the programmable resistor. This adaptation is performed for a certain number of cycles according to the dichotomy algorithm.
  • the master unit or reference current generator 2 firstly comprises a first current mirror composed of transistors N1, N2 of a first type of conductivity, for example NMOS type transistors.
  • the master unit 2 further comprises a second current mirror composed of transistors P1, P2, P3 of a second type of conductivity, for example PMOS type transistors.
  • the first and second current mirrors are connected in series between two terminals of a supply voltage source V DD .
  • the first current mirror is preferably connected to a first terminal of the voltage source, which is in this case a ground terminal, while the second current mirror is preferably connected to a second terminal of the voltage source, which is the high potential terminal V DD .
  • the first current mirror comprises a first NMOS transistor N1, the source of which is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N2, the gate of which is connected to the gate of the first transistor NMOS N1 and the source is connected to the switched capacitor resistor 12, as well as a filter capacitor Cf.
  • the switched capacitor resistor 12 and the filter capacitor C f are also connected to the ground terminal in this form of 'execution.
  • the drain and the gate of the first NMOS transistor N1 are connected to the drain of a first PMOS transistor P1 of the second current mirror.
  • the drain of the second NMOS transistor N2 is connected to the gate and to the drain of a second PMOS transistor P2 of the second current mirror.
  • the gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2.
  • the second current mirror further comprises a third PMOS transistor P3 mounted in parallel with the first and second PMOS transistors P1, P2.
  • the gate of the third PMOS transistor P3 is connected to the gates of the first and second PMOS transistors P1, P2.
  • the sources of the first, second and third PMOS transistors P1, P2, P3 are connected to the high potential terminal V DD of the voltage source.
  • the drain of the third PMOS transistor P3 supplies the reference current I ref of the reference current generator 2.
  • this NMOS transistor N2 is N times larger than the first NMOS transistor N1, which is considered as a unit transistor.
  • the switched capacitor resistor 12 therefore comprises a capacitor C, a first electrode of which is connected to a first switch 4 and to a second switch 5.
  • a second electrode of the capacitor C is connected to the ground terminal.
  • this capacitor C can be a capacitor of the CMOS accumulation type or a capacitor with a thin oxide metal electrode. This makes it possible to have a switched capacitor resistor 12 with an accuracy of the order of ⁇ 5%, whereas a standard integrated resistor 8 is produced with an accuracy of the order of ⁇ 30%.
  • the first switch 4 is arranged between the first electrode of capacitor C and the ground terminal, while the second switch 5 is arranged between the first electrode of capacitor C and the source of the second NMOS transistor N2.
  • the first switch 4 is controlled by a first control signal ⁇ 1, while the second switch 5 is controlled alternately by a second control signal ⁇ 2.
  • the first switch 4 is closed, when the second switch 5 is open, in a first phase, and the first switch 4 is open, when the second switch 5 is closed, in a second phase.
  • Each switch can advantageously be made by means of an MOS transistor, for example an NMOS transistor, which is controlled on its gate by the corresponding control signal.
  • the picture 2 represents in a simplified way the two control signals ⁇ 1 and ⁇ 2, which are preferably not overlapping. These control signals can be obtained via a time base with a quartz oscillator. This quartz oscillator time base can also clock the operations of the processing unit 7.
  • Each control signal comprises one rectangular control pulse per time period T.
  • the rectangular pulse of the first control signal ⁇ 1 is d 'a duration t1, which can be equal to T/4, whereas the rectangular pulse of the second control signal ⁇ 2 has a duration t2, which can also be equal to T/4.
  • a time space of T/4 between the rectangular pulses of the first and second control signals ⁇ 1 and ⁇ 2 can also be considered.
  • the rectangular pulse at state "1" of the first control signal ⁇ 1 controls the closing of the first switch 4, while the rectangular pulse at state "1" of the second control signal ⁇ 2 controls the closing of the second switch 5.
  • the equivalent resistance obtained by controlling the first and second switches 4 and 5 with the first and second control signals ⁇ 1 and ⁇ 2, is equal to T/C.
  • T is the period of each control signal and C defines the capacitance of the capacitor.
  • the resistive value of the equivalent resistance can be changed.
  • This equivalent resistance of the master unit 2 can be established with an accuracy of ⁇ 5% according to the manufacturing method of the electronic circuit integrated in a traditional silicon substrate.
  • This equivalent resistor 12 may be identical to the programmable resistor 8 digitally adapted in the slave unit 3 after the calibration of the PTAT current.
  • the reference current generator 2 and the time base for supplying the control signals ⁇ 1 and ⁇ 2 can be disconnected. Only the calibrated PTAT current generator remains functional with an accuracy of the output current PTAT I OUT guaranteed with an accuracy, which can be at least ⁇ 5% of the expected value.
  • the PTAT slave unit 3 or the PTAT current generator 3 comprises a first current mirror composed of transistors N11, N12 of a first type of conductivity, for example NMOS type transistors .
  • the PTAT slave unit 3 further comprises a second current mirror composed of transistors P11, P12, P13 of a second type of conductivity, for example PMOS type transistors.
  • the first and second current mirrors are connected in series between two terminals of a supply voltage source V DD .
  • the first current mirror is preferably connected to the first terminal of the voltage source, which in this case is the ground terminal, while the second current mirror is preferably connected to the second terminal of the voltage source, which is the high potential terminal V DD .
  • the first current mirror comprises a first NMOS transistor N11, whose source is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N12, whose gate is connected to the gate of the first transistor NMOS N11 and the source is connected to the programmable resistor 8, which is also connected to the ground terminal.
  • the drain and the gate of the first NMOS transistor N11 are connected to the drain of a first PMOS transistor P11 of the second current mirror.
  • the drain of the second NMOS transistor N12 is connected to the gate and to the drain of a second PMOS transistor P12 of the second current mirror.
  • the gate of the first PMOS transistor P11 is connected to the gate of the second PMOS transistor P12.
  • the second current mirror of the PTAT slave unit 3 further comprises a third PMOS transistor P13 connected in parallel with the first and second PMOS transistors P11, P12.
  • the gate of the third PMOS transistor P13 is connected to the gates of the first and second PMOS transistors P11, P12.
  • the sources of the first, second and third PMOS transistors P11, P12, P13 are connected to the high potential terminal V DD of the voltage source.
  • the drain of the third PMOS transistor P13 supplies the output current PTAT I OUT of the current generator PTAT 3.
  • this NMOS transistor N2 is N′ times larger than the first NMOS transistor N11, which is considered as a single transistor.
  • the third PMOS transistor P13 can also be provided M times larger than the first PMOS transistor P11 and the second PMOS transistor P12 of the second current mirror of the slave unit PTAT 3.
  • M is an integer plus large or equal to 1.
  • the programmable resistor 8, which has been adapted can be equivalent to the switched capacitor resistor 12 of the master unit 2.
  • the electronic circuit 1 can be used instead of the third PMOS transistor P13, a set of unitary transistors combined with digitally controlled switches.
  • the programmable resistor 8 it can be envisaged to have a resistor 8 of defined value, and to digitally adapt a dimensional ratio of PMOS transistors of the second current mirror, which provide the output current PTAT I OUT .
  • An adaptation binary word is supplied at the end of the calibration cycles by the dichotomy algorithm. This binary word for configuring the set of transistors is stored in the processing unit 7.
  • resistors with switched capacitor arranged in parallel and each controlled by two control signals specific to each resistor with switched capacitor.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
EP13198965.9A 2013-12-20 2013-12-20 Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action Active EP2887176B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP13198965.9A EP2887176B1 (fr) 2013-12-20 2013-12-20 Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action
US14/558,839 US9442509B2 (en) 2013-12-20 2014-12-03 Electronic circuit with self-calibrated PTAT current reference and method for actuating the same
TW103142196A TWI675275B (zh) 2013-12-20 2014-12-04 具有自校準ｐｔａｔ電流參考的電子電路及對其致動的方法
JP2014253730A JP5918344B2 (ja) 2013-12-20 2014-12-16 自己較正されるｐｔａｔ電流基準を備えた電子回路及びこれを作動させる方法
CN201410784806.4A CN104731148B (zh) 2013-12-20 2014-12-17 具有ptat电流基准的电子电路及致动该电路的方法
KR1020140184793A KR101749794B1 (ko) 2013-12-20 2014-12-19 자기-교정된 ptat 전류 기준을 갖는 전자 회로 및 그것을 구동하는 방법
HK15112380.6A HK1211715A1 (en) 2013-12-20 2015-12-16 Electronic circuit with self-calibrated ptat current reference and method for actuating the same ptat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP13198965.9A EP2887176B1 (fr) 2013-12-20 2013-12-20 Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action

Publications (2)

Publication Number Publication Date
EP2887176A1 EP2887176A1 (fr) 2015-06-24
EP2887176B1 true EP2887176B1 (fr) 2022-09-14

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EP13198965.9A Active EP2887176B1 (fr) 2013-12-20 2013-12-20 Circuit électronique à référence de courant PTAT auto-calibrée, et procédé pour sa mise en action

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US (1) US9442509B2 (ko)
EP (1) EP2887176B1 (ko)
JP (1) JP5918344B2 (ko)
KR (1) KR101749794B1 (ko)
CN (1) CN104731148B (ko)
HK (1) HK1211715A1 (ko)
TW (1) TWI675275B (ko)

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US10078016B2 (en) 2016-02-10 2018-09-18 Nxp Usa, Inc. On-die temperature sensor for integrated circuit
CN106055009A (zh) * 2016-06-17 2016-10-26 中国科学院微电子研究所 一种高精度带隙基准电路
CN108566173A (zh) * 2018-06-11 2018-09-21 杨俊杰 一种采用cmos工艺芯片内部的rc时间常数校正电路
CN109341890B (zh) * 2018-10-22 2021-05-14 安徽鸿创新能源动力有限公司 一种基于ntc温度传感器的bms温度采集系统及测量方法
US10747254B1 (en) * 2019-09-03 2020-08-18 Globalfoundries Inc. Circuit structure for adjusting PTAT current to compensate for process variations in device transistor
CN113253787A (zh) * 2021-06-17 2021-08-13 苏州裕太微电子有限公司 一种芯片内电阻校正电路
US11962311B2 (en) * 2021-10-20 2024-04-16 Samsung Electronics Co., Ltd. Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same
CN116795165B (zh) * 2023-07-25 2024-04-05 南京米乐为微电子科技股份有限公司 一种ptat电流源的输出调节电路

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Also Published As

Publication number Publication date
KR20150073122A (ko) 2015-06-30
US9442509B2 (en) 2016-09-13
US20150177772A1 (en) 2015-06-25
JP5918344B2 (ja) 2016-05-18
TWI675275B (zh) 2019-10-21
KR101749794B1 (ko) 2017-06-21
CN104731148B (zh) 2016-08-31
JP2015122494A (ja) 2015-07-02
EP2887176A1 (fr) 2015-06-24
HK1211715A1 (en) 2016-05-27
TW201541219A (zh) 2015-11-01
CN104731148A (zh) 2015-06-24

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