EP2887176B1 - Electronic circuit with self-calibrated PTAT current reference, and method for operating same - Google Patents

Electronic circuit with self-calibrated PTAT current reference, and method for operating same Download PDF

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Publication number
EP2887176B1
EP2887176B1 EP13198965.9A EP13198965A EP2887176B1 EP 2887176 B1 EP2887176 B1 EP 2887176B1 EP 13198965 A EP13198965 A EP 13198965A EP 2887176 B1 EP2887176 B1 EP 2887176B1
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EP
European Patent Office
Prior art keywords
current
ptat
nmos transistor
transistor
resistor
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EP13198965.9A
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German (de)
French (fr)
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EP2887176A1 (en
Inventor
Arnaud Casagrande
Jean-Luc Arend
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Swatch Group Research and Development SA
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Swatch Group Research and Development SA
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Priority to EP13198965.9A priority Critical patent/EP2887176B1/en
Priority to US14/558,839 priority patent/US9442509B2/en
Priority to TW103142196A priority patent/TWI675275B/en
Priority to JP2014253730A priority patent/JP5918344B2/en
Priority to CN201410784806.4A priority patent/CN104731148B/en
Priority to KR1020140184793A priority patent/KR101749794B1/en
Publication of EP2887176A1 publication Critical patent/EP2887176A1/en
Priority to HK15112380.6A priority patent/HK1211715A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type.
  • the invention also relates to the method for calibrating a current source of the PTAT type of the electronic circuit.
  • a PTAT type current is a current proportional to the absolute temperature.
  • Current sources of the PTAT type are used in electronic circuits for supplying at least one temperature-dependent current. They can also be used in electronic circuits with temperature sensor or in function management circuits in conjunction with a time base.
  • a conventional resistor is used in a current generation branch.
  • the precision of such a resistor can vary by ⁇ 30% with respect to an estimated value according to the manufacturing method, for example of the MOS type. Provision must often be made to calibrate such a resistor at the end of the manufacturing process in order to be able to ensure sufficient precision of a current reference of the PTAT type, which is a drawback.
  • the Master matching circuit is a phase-locked loop (PLL) circuit, which comprises a switched capacitor (SC) resistor in a first branch, and a replica MOS resistor in parallel in a second branch, and in connection with an integrator for supplying a control voltage to the variable resistor and the replica resistor.
  • PLL phase-locked loop
  • SC switched capacitor
  • MOS complementary metal-oxide-semiconductor
  • the object of the invention is therefore to provide an electronic circuit provided with a current reference of the self-calibrated PTAT type in order to improve the current reference precision independently of any variation in the manufacturing process of the electronic circuit and overcoming the aforementioned drawbacks of the state of the art.
  • the invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type, which comprises the characteristics mentioned in independent claim 1.
  • An advantage of the electronic circuit resides in the fact that it is possible to digitally adjust a resistor network for the generation of a PTAT current reference, by comparing an output current of a PTAT current generating unit with a reference current.
  • the reference current is generated in a reference current generator based on a switched capacitor equivalent resistance.
  • a calibration of the current reference PTAT of the electronic circuit can be carried out automatically as soon as the electronic circuit is put into operation. Calibration is performed by several successive comparisons of the PTAT output current with the reference current by dichotomy. The comparison can be performed in a comparator. An adaptation of the resistive value of the network of resistors or the value of the output current by paralleling transistors of a current mirror is controlled via a processing unit receiving the information from the comparator.
  • the reference unit which provides the reference current for comparison with the PTAT output current, can be disconnected.
  • Switched capacitor resistor switch timing signals which originate from a time base, are suppressed to reduce power consumption and avoid spectral pollution.
  • this PTAT current can be at least 2 to 3 times more accurate than such a current obtained with a standard built-in state-of-the-art resistor, while taking into account the errors of pairing of the current mirrors and the current comparator.
  • the invention also relates to a method for calibrating a current source of the PTAT type of the electronic circuit, which comprises the characteristics defined in independent claim 7.
  • the electronic circuit 1 comprises a so-called master unit for supplying a calibration reference current I ref , and a so-called slave unit 3 for supplying a current reference PTAT at output I OUT .
  • the master unit 2 is a calibration reference current generator I ref dependent on a switched capacitor resistor 12.
  • the PTAT slave unit 3 is a current generator for supplying a PTAT current reference at output I OUT .
  • the current reference PTAT supplied by the generator PTAT is dependent on a resistor 8, the resistive value of which R can be adjusted digitally as explained below. However, it is also possible to digitally adapt a dimensional ratio of transistors of a current mirror in the generator of the current PTAT for the supply of the adapted current PTAT.
  • a comparison in a comparator 6 is performed between the calibration reference current I ref of the master unit 2 and the output current PTAT I OUT of the slave unit 3.
  • the PTAT output current I OUT is identical to the reference current I ref .
  • the electronic circuit with resistor 8 is integrated into a semiconductor substrate, such as a silicon substrate, the resistive value of resistor 8 at the output of the MOS-type manufacturing process is not precise. Consequently, the output current PTAT I OUT is not identical to the current I ref .
  • the programmable resistor 8 is digitally matched. Programmable resistor 8 can be adapted to become equivalent to switched capacitor resistor 12. Depending on the comparison between the two currents, information at the output of the comparator 6 is supplied to a processing unit 7 so as to control a digital adaptation of the programmable resistor 8.
  • This programmable resistor 8 can be composed of a network of resistors and programmable switches.
  • the resistor network comprises several unit value resistors in series and/or also partly in parallel.
  • switches can be provided by being connected in parallel to each unit resistor or groups of unit resistors, which is well known. The switches are controlled by digital signals or a binary command word coming from the processing unit 7 so as to short-circuit a certain number of unit resistors to adapt the resistive value of the programmable resistor 8.
  • the processing unit 7 therefore provides a binary word to control the switches and adapt the programmable resistor.
  • a command binary word for example on 16 bits, can be provided so as to adjust said programmable resistor 8. This makes it possible to guarantee an accuracy of at least the order of ⁇ 5% with respect to the estimated resistance, whereas without calibration , the error of the programmable resistor can be close to ⁇ 30% as mentioned above. However, account must be taken in the precision of the pairing errors of the current mirrors and of the current comparator 6, which can reduce the precision somewhat.
  • a dichotomy algorithm is preferably used in the processing unit 7. This makes it possible to converge quickly towards a final value of the programmable resistor. This adaptation is performed for a certain number of cycles according to the dichotomy algorithm.
  • the master unit or reference current generator 2 firstly comprises a first current mirror composed of transistors N1, N2 of a first type of conductivity, for example NMOS type transistors.
  • the master unit 2 further comprises a second current mirror composed of transistors P1, P2, P3 of a second type of conductivity, for example PMOS type transistors.
  • the first and second current mirrors are connected in series between two terminals of a supply voltage source V DD .
  • the first current mirror is preferably connected to a first terminal of the voltage source, which is in this case a ground terminal, while the second current mirror is preferably connected to a second terminal of the voltage source, which is the high potential terminal V DD .
  • the first current mirror comprises a first NMOS transistor N1, the source of which is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N2, the gate of which is connected to the gate of the first transistor NMOS N1 and the source is connected to the switched capacitor resistor 12, as well as a filter capacitor Cf.
  • the switched capacitor resistor 12 and the filter capacitor C f are also connected to the ground terminal in this form of 'execution.
  • the drain and the gate of the first NMOS transistor N1 are connected to the drain of a first PMOS transistor P1 of the second current mirror.
  • the drain of the second NMOS transistor N2 is connected to the gate and to the drain of a second PMOS transistor P2 of the second current mirror.
  • the gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2.
  • the second current mirror further comprises a third PMOS transistor P3 mounted in parallel with the first and second PMOS transistors P1, P2.
  • the gate of the third PMOS transistor P3 is connected to the gates of the first and second PMOS transistors P1, P2.
  • the sources of the first, second and third PMOS transistors P1, P2, P3 are connected to the high potential terminal V DD of the voltage source.
  • the drain of the third PMOS transistor P3 supplies the reference current I ref of the reference current generator 2.
  • this NMOS transistor N2 is N times larger than the first NMOS transistor N1, which is considered as a unit transistor.
  • the switched capacitor resistor 12 therefore comprises a capacitor C, a first electrode of which is connected to a first switch 4 and to a second switch 5.
  • a second electrode of the capacitor C is connected to the ground terminal.
  • this capacitor C can be a capacitor of the CMOS accumulation type or a capacitor with a thin oxide metal electrode. This makes it possible to have a switched capacitor resistor 12 with an accuracy of the order of ⁇ 5%, whereas a standard integrated resistor 8 is produced with an accuracy of the order of ⁇ 30%.
  • the first switch 4 is arranged between the first electrode of capacitor C and the ground terminal, while the second switch 5 is arranged between the first electrode of capacitor C and the source of the second NMOS transistor N2.
  • the first switch 4 is controlled by a first control signal ⁇ 1, while the second switch 5 is controlled alternately by a second control signal ⁇ 2.
  • the first switch 4 is closed, when the second switch 5 is open, in a first phase, and the first switch 4 is open, when the second switch 5 is closed, in a second phase.
  • Each switch can advantageously be made by means of an MOS transistor, for example an NMOS transistor, which is controlled on its gate by the corresponding control signal.
  • the picture 2 represents in a simplified way the two control signals ⁇ 1 and ⁇ 2, which are preferably not overlapping. These control signals can be obtained via a time base with a quartz oscillator. This quartz oscillator time base can also clock the operations of the processing unit 7.
  • Each control signal comprises one rectangular control pulse per time period T.
  • the rectangular pulse of the first control signal ⁇ 1 is d 'a duration t1, which can be equal to T/4, whereas the rectangular pulse of the second control signal ⁇ 2 has a duration t2, which can also be equal to T/4.
  • a time space of T/4 between the rectangular pulses of the first and second control signals ⁇ 1 and ⁇ 2 can also be considered.
  • the rectangular pulse at state "1" of the first control signal ⁇ 1 controls the closing of the first switch 4, while the rectangular pulse at state "1" of the second control signal ⁇ 2 controls the closing of the second switch 5.
  • the equivalent resistance obtained by controlling the first and second switches 4 and 5 with the first and second control signals ⁇ 1 and ⁇ 2, is equal to T/C.
  • T is the period of each control signal and C defines the capacitance of the capacitor.
  • the resistive value of the equivalent resistance can be changed.
  • This equivalent resistance of the master unit 2 can be established with an accuracy of ⁇ 5% according to the manufacturing method of the electronic circuit integrated in a traditional silicon substrate.
  • This equivalent resistor 12 may be identical to the programmable resistor 8 digitally adapted in the slave unit 3 after the calibration of the PTAT current.
  • the reference current generator 2 and the time base for supplying the control signals ⁇ 1 and ⁇ 2 can be disconnected. Only the calibrated PTAT current generator remains functional with an accuracy of the output current PTAT I OUT guaranteed with an accuracy, which can be at least ⁇ 5% of the expected value.
  • the PTAT slave unit 3 or the PTAT current generator 3 comprises a first current mirror composed of transistors N11, N12 of a first type of conductivity, for example NMOS type transistors .
  • the PTAT slave unit 3 further comprises a second current mirror composed of transistors P11, P12, P13 of a second type of conductivity, for example PMOS type transistors.
  • the first and second current mirrors are connected in series between two terminals of a supply voltage source V DD .
  • the first current mirror is preferably connected to the first terminal of the voltage source, which in this case is the ground terminal, while the second current mirror is preferably connected to the second terminal of the voltage source, which is the high potential terminal V DD .
  • the first current mirror comprises a first NMOS transistor N11, whose source is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N12, whose gate is connected to the gate of the first transistor NMOS N11 and the source is connected to the programmable resistor 8, which is also connected to the ground terminal.
  • the drain and the gate of the first NMOS transistor N11 are connected to the drain of a first PMOS transistor P11 of the second current mirror.
  • the drain of the second NMOS transistor N12 is connected to the gate and to the drain of a second PMOS transistor P12 of the second current mirror.
  • the gate of the first PMOS transistor P11 is connected to the gate of the second PMOS transistor P12.
  • the second current mirror of the PTAT slave unit 3 further comprises a third PMOS transistor P13 connected in parallel with the first and second PMOS transistors P11, P12.
  • the gate of the third PMOS transistor P13 is connected to the gates of the first and second PMOS transistors P11, P12.
  • the sources of the first, second and third PMOS transistors P11, P12, P13 are connected to the high potential terminal V DD of the voltage source.
  • the drain of the third PMOS transistor P13 supplies the output current PTAT I OUT of the current generator PTAT 3.
  • this NMOS transistor N2 is N′ times larger than the first NMOS transistor N11, which is considered as a single transistor.
  • the third PMOS transistor P13 can also be provided M times larger than the first PMOS transistor P11 and the second PMOS transistor P12 of the second current mirror of the slave unit PTAT 3.
  • M is an integer plus large or equal to 1.
  • the programmable resistor 8, which has been adapted can be equivalent to the switched capacitor resistor 12 of the master unit 2.
  • the electronic circuit 1 can be used instead of the third PMOS transistor P13, a set of unitary transistors combined with digitally controlled switches.
  • the programmable resistor 8 it can be envisaged to have a resistor 8 of defined value, and to digitally adapt a dimensional ratio of PMOS transistors of the second current mirror, which provide the output current PTAT I OUT .
  • An adaptation binary word is supplied at the end of the calibration cycles by the dichotomy algorithm. This binary word for configuring the set of transistors is stored in the processing unit 7.
  • resistors with switched capacitor arranged in parallel and each controlled by two control signals specific to each resistor with switched capacitor.

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Description

L'invention concerne un circuit électronique muni d'une référence de courant du type PTAT auto-calibrée.The invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type.

L'invention concerne également le procédé de calibration d'une source de courant du type PTAT du circuit électronique.The invention also relates to the method for calibrating a current source of the PTAT type of the electronic circuit.

Un courant de type PTAT est un courant proportionnel à la température absolue. Des sources de courant de type PTAT sont utilisées dans des circuits électroniques pour la fourniture d'au moins un courant dépendant de la température. Elles peuvent servir également dans des circuits électroniques à capteur de température ou dans des circuits de gestion de fonctions en liaison avec une base de temps.A PTAT type current is a current proportional to the absolute temperature. Current sources of the PTAT type are used in electronic circuits for supplying at least one temperature-dependent current. They can also be used in electronic circuits with temperature sensor or in function management circuits in conjunction with a time base.

Généralement pour la génération d'une référence de courant du type PTAT dans un circuit électronique intégré dans un substrat en silicium, il est utilisé dans une branche de génération de courant une résistance classique. La précision d'une telle résistance peut varier de ±30% par rapport à une valeur estimée selon le procédé de fabrication par exemple de type MOS. Il doit souvent être prévu de calibrer une telle résistance au terme du procédé de fabrication pour pouvoir assurer une précision suffisante d'une référence de courant du type PTAT, ce qui est un inconvénient.Generally for the generation of a current reference of the PTAT type in an electronic circuit integrated in a silicon substrate, a conventional resistor is used in a current generation branch. The precision of such a resistor can vary by ±30% with respect to an estimated value according to the manufacturing method, for example of the MOS type. Provision must often be made to calibrate such a resistor at the end of the manufacturing process in order to be able to ensure sufficient precision of a current reference of the PTAT type, which is a drawback.

Pour calibrer la référence de courant du type PTAT, il peut être utilisé un réseau de résistances et de commutateurs programmables liés aux résistances pour la génération de ce courant. Cela nécessite au terme de tout procédé de fabrication de mesurer la valeur de ce courant et de commander la connexion de plusieurs résistances pour obtenir la référence désirée de ce courant PTAT. Cela complique les opérations d'adaptation de cette référence de courant, ce qui constitue un inconvénient.To calibrate the current reference of the PTAT type, a network of resistors and programmable switches linked to the resistors for the generation of this current can be used. This requires at the end of any manufacturing process to measure the value of this current and to control the connection of several resistors to obtain the desired reference of this PTAT current. This complicates the operations for adapting this current reference, which constitutes a drawback.

Il est cité l'article de Talebbeydokhti et AI "Constant transconductance bias circuit with an on-chip resistor", 2006 IEEE International Sympositum on Circuits and systems, pages 2857-2860 du 21 mai 2006 . Il est décrit un circuit de polarisation à transconductance constante avec une résistance variable sur le circuit. La résistance est en série avec deux miroirs de courants NMOS et PMOS entre des bornes d'une source de tension d'alimentation. La valeur résistive de la résistance MOS peut être adaptée précisément par un circuit d'adaptation selon le principe Maître-Esclave relié à ladite résistance variable. Le circuit d'adaptation Maître est un circuit à boucle à verrouillage de phase (PLL), qui comprend une résistance à condensateur commuté (SC) dans une première branche, et une résistance réplique MOS en parallèle dans une seconde branche, et en liaison avec un intégrateur pour fournir une tension de commande à la résistance variable et à la résistance réplique. Un tel circuit d'adaptation est de conception relativement compliquée et ne permet pas de facilement adapter un courant d'un circuit électronique par un courant de référence au terme d'un procédé de fabrication, ce qui constitue un inconvénient.It is quoted the article of Talebbeydokhti and AI "Constant transconductance bias circuit with an on-chip resistor", 2006 IEEE International Sympositum on Circuits and systems, pages 2857-2860 of May 21, 2006 . A constant transconductance bias circuit is described with a variable resistor on the circuit. The resistor is in series with two NMOS and PMOS current mirrors between terminals of a supply voltage source. The resistive value of the MOS resistor can be adapted precisely by an adaptation circuit according to the Master-Slave principle connected to said variable resistor. The Master matching circuit is a phase-locked loop (PLL) circuit, which comprises a switched capacitor (SC) resistor in a first branch, and a replica MOS resistor in parallel in a second branch, and in connection with an integrator for supplying a control voltage to the variable resistor and the replica resistor. Such an adaptation circuit is of relatively complicated design and does not make it possible to easily adapt a current of an electronic circuit by a reference current at the end of a manufacturing process, which constitutes a drawback.

Dans les brevets US 7,076,384 B1 , US 6,844,711 B1 et dans la demande de brevet US 2006/0276986 A1 , il est décrit des systèmes de calibration d'un courant ou d'une tension de référence, mais sans mentionner une calibration au moyen d'un circuit d'adaptation de référence au moyen d'une résistance à condensateur commuté.in patents US 7,076,384 B1 , US 6,844,711 B1 and in the patent application US 2006/0276986 A1 , systems for calibrating a reference current or voltage are described, but without mentioning a calibration by means of a reference matching circuit by means of a switched capacitor resistor.

L'invention a donc pour but de fournir un circuit électronique muni d'une référence de courant du type PTAT auto-calibrée pour améliorer la précision de référence de courant indépendamment de toute variation du procédé de fabrication du circuit électronique et palliant les inconvénients susmentionnés de l'état de la technique.The object of the invention is therefore to provide an electronic circuit provided with a current reference of the self-calibrated PTAT type in order to improve the current reference precision independently of any variation in the manufacturing process of the electronic circuit and overcoming the aforementioned drawbacks of the state of the art.

A cet effet, l'invention concerne un circuit électronique muni d'une référence de courant du type PTAT auto-calibrée, qui comprend les caractéristiques mentionnées dans la revendication indépendante 1.To this end, the invention relates to an electronic circuit provided with a current reference of the self-calibrated PTAT type, which comprises the characteristics mentioned in independent claim 1.

Des formes d'exécution particulières du circuit électronique sont définies dans les revendications dépendantes 2 à 6.Particular embodiments of the electronic circuit are defined in dependent claims 2 to 6.

Un avantage du circuit électronique réside dans le fait qu'il est possible d'ajuster numériquement un réseau de résistances pour la génération d'une référence de courant PTAT, en comparant un courant de sortie d'une unité de génération du courant PTAT à un courant de référence. Le courant de référence est généré dans un générateur de courant de référence sur la base d'une résistance équivalente à condensateur commuté.An advantage of the electronic circuit resides in the fact that it is possible to digitally adjust a resistor network for the generation of a PTAT current reference, by comparing an output current of a PTAT current generating unit with a reference current. The reference current is generated in a reference current generator based on a switched capacitor equivalent resistance.

Avantageusement, il est également possible d'adapter numériquement un rapport dimensionnel de transistors d'un miroir de courant de l'unité de génération du courant PTAT par la comparaison entre le courant de sortie PTAT et le courant de référence. Plusieurs transistors sont donc connectables en parallèle dans un miroir de courant de l'unité de génération pour la fourniture du courant PTAT.Advantageously, it is also possible to digitally adapt a dimensional ratio of transistors of a current mirror of the current generation unit PTAT by comparing the output current PTAT and the reference current. Several transistors can therefore be connected in parallel in a current mirror of the generation unit for supplying the current PTAT.

Avantageusement, une calibration de la référence de courant PTAT du circuit électronique peut être effectuée automatiquement dès la mise en fonction du circuit électronique. La calibration s'effectue par plusieurs comparaisons successives du courant de sortie PTAT avec le courant de référence par dichotomie. La comparaison peut être effectuée dans un comparateur. Une adaptation de la valeur résistive du réseau de résistances ou de la valeur du courant de sortie par la mise en parallèle de transistors d'un miroir de courant est commandée par l'intermédiaire d'une unité de traitement recevant l'information du comparateur.Advantageously, a calibration of the current reference PTAT of the electronic circuit can be carried out automatically as soon as the electronic circuit is put into operation. Calibration is performed by several successive comparisons of the PTAT output current with the reference current by dichotomy. The comparison can be performed in a comparator. An adaptation of the resistive value of the network of resistors or the value of the output current by paralleling transistors of a current mirror is controlled via a processing unit receiving the information from the comparator.

Avantageusement après la calibration de la référence de courant PTAT dans une première phase, l'unité de référence, qui fournit le courant de référence pour la comparaison avec le courant de sortie PTAT, peut être déconnectée. Les signaux de cadencement des commutateurs de la résistance à condensateur commuté, qui proviennent d'une base de temps, sont supprimés pour réduire la consommation et éviter toute pollution spectrale. Avec cette calibration automatique du courant de sortie PTAT, ce courant PTAT peut être au moins de 2 à 3 fois plus précis qu'un tel courant obtenu avec une résistance standard intégrée de l'état de la technique, tout en tenant compte des erreurs d'appariement des miroirs de courant et du comparateur de courants.Advantageously, after calibration of the PTAT current reference in a first phase, the reference unit, which provides the reference current for comparison with the PTAT output current, can be disconnected. Switched capacitor resistor switch timing signals, which originate from a time base, are suppressed to reduce power consumption and avoid spectral pollution. With this automatic calibration of the PTAT output current, this PTAT current can be at least 2 to 3 times more accurate than such a current obtained with a standard built-in state-of-the-art resistor, while taking into account the errors of pairing of the current mirrors and the current comparator.

A cet effet, l'invention concerne également un procédé de calibration d'une source de courant du type PTAT du circuit électronique, qui comprend les caractéristiques définies dans la revendication indépendante 7.To this end, the invention also relates to a method for calibrating a current source of the PTAT type of the electronic circuit, which comprises the characteristics defined in independent claim 7.

Des étapes particulières du procédé sont définies dans les revendications dépendantes 8 à 10.Particular process steps are defined in dependent claims 8 to 10.

Les buts, avantages et caractéristiques du circuit électronique à référence de courant PTAT auto-calibrée, ainsi que le procédé de calibration d'une source de courant de type PTAT, apparaîtront mieux dans la description suivante sur la base d'au moins une forme d'exécution non limitative et illustrée par les dessins sur lesquels :

  • la figure 1 représente de manière simplifiée les différents composants du circuit électronique à référence de courant PTAT auto-calibrée selon l'invention, et
  • la figure 2 représente un graphique des signaux de cadencement des commutateurs en liaison à au moins un condensateur pour l'unité maître référence du circuit électronique à référence de courant PTAT auto-calibrée selon l'invention.
The aims, advantages and characteristics of the self-calibrated PTAT current reference electronic circuit, as well as the method of calibrating a current source of the PTAT type, will appear better in the following description on the basis of at least one form of non-limiting execution and illustrated by the drawings on which:
  • the figure 1 represents in a simplified manner the various components of the self-calibrated PTAT current reference electronic circuit according to the invention, and
  • the figure 2 shows a graph of the timing signals of the switches in conjunction with at least one capacitor for the master unit reference of the self-calibrated PTAT current reference electronic circuit according to the invention.

Dans la description suivante, tous les composants électroniques du circuit électronique à référence de courant PTAT, qui sont bien connus d'un homme du métier dans ce domaine technique, ne sont décrits que de manière simplifiée.In the following description, all the electronic components of the electronic circuit with current reference PTAT, which are well known to a person skilled in the art in this technical field, are only described in a simplified manner.

A la figure 1, une première forme d'exécution du circuit électronique 1 est représentée. Le circuit électronique 1 comprend une unité dite maître pour la fourniture d'un courant de référence Iref de calibration, et une unité dite esclave 3 pour la fourniture d'une référence de courant PTAT en sortie IOUT. L'unité maître 2 est un générateur de courant de référence Iref de calibration dépendant d'une résistance à condensateur commuté 12. L'unité esclave PTAT 3 est un générateur de courant pour la fourniture d'une référence de courant PTAT en sortie IOUT. La référence de courant PTAT fournie par le générateur PTAT est dépendante d'une résistance 8, dont la valeur résistive R peut être ajustée numériquement comme expliqué ci-après. Toutefois, il est aussi possible d'adapter numériquement un rapport dimensionnel de transistors d'un miroir de courant dans le générateur du courant PTAT pour la fourniture du courant adapté PTAT.To the figure 1 , a first embodiment of the electronic circuit 1 is shown. The electronic circuit 1 comprises a so-called master unit for supplying a calibration reference current I ref , and a so-called slave unit 3 for supplying a current reference PTAT at output I OUT . The master unit 2 is a calibration reference current generator I ref dependent on a switched capacitor resistor 12. The PTAT slave unit 3 is a current generator for supplying a PTAT current reference at output I OUT . The current reference PTAT supplied by the generator PTAT is dependent on a resistor 8, the resistive value of which R can be adjusted digitally as explained below. However, it is also possible to digitally adapt a dimensional ratio of transistors of a current mirror in the generator of the current PTAT for the supply of the adapted current PTAT.

Pour adapter le courant de sortie PTAT IOUT, une comparaison dans un comparateur 6 est effectuée entre le courant de référence Iref de calibration de l'unité maître 2 et le courant de sortie PTAT IOUT de l'unité esclave 3. Dans un cas idéal ou après calibration, le courant de sortie PTAT IOUT est identique au courant de référence Iref. Cependant comme le circuit électronique avec la résistance 8 est intégré dans un substrat semiconducteur, tel qu'un substrat en silicium, la valeur résistive de la résistance 8 à la sortie du procédé de fabrication de type MOS n'est pas précise. De ce fait, le courant de sortie PTAT IOUT n'est pas identique au courant Iref. Dans ces conditions, la résistance programmable 8 est adaptée numériquement. La résistance programmable 8 peut être adaptée pour devenir équivalente à la résistance à condensateur commuté 12. En fonction de la comparaison entre les deux courants, une information en sortie du comparateur 6 est fournie à une unité de traitement 7 de manière à commander une adaptation numérique de la résistance programmable 8.To adapt the output current PTAT I OUT , a comparison in a comparator 6 is performed between the calibration reference current I ref of the master unit 2 and the output current PTAT I OUT of the slave unit 3. In a ideal case or after calibration, the PTAT output current I OUT is identical to the reference current I ref . However, since the electronic circuit with resistor 8 is integrated into a semiconductor substrate, such as a silicon substrate, the resistive value of resistor 8 at the output of the MOS-type manufacturing process is not precise. Consequently, the output current PTAT I OUT is not identical to the current I ref . Under these conditions, the programmable resistor 8 is digitally matched. Programmable resistor 8 can be adapted to become equivalent to switched capacitor resistor 12. Depending on the comparison between the two currents, information at the output of the comparator 6 is supplied to a processing unit 7 so as to control a digital adaptation of the programmable resistor 8.

Cette résistance programmable 8 peut être composée d'un réseau de résistances et de commutateurs programmables. Le réseau de résistances comprend plusieurs résistances de valeur unitaire en série et/ou également en partie en parallèle. Dans le cas de résistances unitaires en série, des commutateurs peuvent être prévus en étant connectés en parallèle de chaque résistance unitaire ou de groupes de résistances unitaires, ce qui est bien connu. Les commutateurs sont commandés par des signaux numériques ou un mot binaire de commande provenant de l'unité de traitement 7 de manière à court-circuiter un certain nombre de résistances unitaires pour adapter la valeur résistive de la résistance programmable 8.This programmable resistor 8 can be composed of a network of resistors and programmable switches. The resistor network comprises several unit value resistors in series and/or also partly in parallel. In the case of unit resistors in series, switches can be provided by being connected in parallel to each unit resistor or groups of unit resistors, which is well known. The switches are controlled by digital signals or a binary command word coming from the processing unit 7 so as to short-circuit a certain number of unit resistors to adapt the resistive value of the programmable resistor 8.

L'unité de traitement 7 fournit donc un mot binaire pour commander les commutateurs et adapter la résistance programmable. Il peut être prévu un mot binaire de commande par exemple sur 16 bits de manière à ajuster ladite résistance programmable 8. Ceci permet de garantir une précision au moins de l'ordre de ±5% par rapport à la résistance estimée, alors que sans calibration, l'erreur de la résistance programmable peut être voisine de ±30% comme susmentionné. Cependant il doit être tenu compte dans la précision des erreurs d'appariement des miroirs de courant et du comparateur de courants 6, ce qui peut réduire quelque peu la précision.The processing unit 7 therefore provides a binary word to control the switches and adapt the programmable resistor. A command binary word, for example on 16 bits, can be provided so as to adjust said programmable resistor 8. This makes it possible to guarantee an accuracy of at least the order of ±5% with respect to the estimated resistance, whereas without calibration , the error of the programmable resistor can be close to ±30% as mentioned above. However, account must be taken in the precision of the pairing errors of the current mirrors and of the current comparator 6, which can reduce the precision somewhat.

Pour adapter la résistance programmable 8, il est de préférence utilisé un algorithme de dichotomie dans l'unité de traitement 7. Cela permet de converger rapidement vers une valeur finale de la résistance programmable. Cette adaptation est effectuée pendant un certain nombre de cycles selon l'algorithme de dichotomie. Une fois que le courant de sortie PTAT IOUT devient identique au courant de référence Iref, une mémorisation du mot binaire de programmation de la résistance programmable est effectuée notamment dans une mémoire dans l'unité de traitement 7.To adapt the programmable resistor 8, a dichotomy algorithm is preferably used in the processing unit 7. This makes it possible to converge quickly towards a final value of the programmable resistor. This adaptation is performed for a certain number of cycles according to the dichotomy algorithm. Once the output current PTAT I OUT becomes identical to the reference current I ref , the programming binary word of the programmable resistor is memorized in particular in a memory in the processing unit 7.

L'unité maître ou générateur de courant de référence 2 comprend tout d'abord un premier miroir de courant composé de transistors N1, N2 d'un premier type de conductivité, par exemple de transistors de type NMOS. L'unité maître 2 comprend encore un second miroir de courant composé de transistors P1, P2, P3 d'un second type de conductivité, par exemple de transistors de type PMOS. Les premier et second miroirs de courant sont montés en série entre deux bornes d'une source de tension d'alimentation VDD. Le premier miroir de courant est de préférence relié à une première borne de la source de tension, qui est dans ce cas une borne de masse, alors que le second miroir de courant est de préférence relié à une seconde borne de la source de tension, qui est la borne de potentiel haut VDD.The master unit or reference current generator 2 firstly comprises a first current mirror composed of transistors N1, N2 of a first type of conductivity, for example NMOS type transistors. The master unit 2 further comprises a second current mirror composed of transistors P1, P2, P3 of a second type of conductivity, for example PMOS type transistors. The first and second current mirrors are connected in series between two terminals of a supply voltage source V DD . The first current mirror is preferably connected to a first terminal of the voltage source, which is in this case a ground terminal, while the second current mirror is preferably connected to a second terminal of the voltage source, which is the high potential terminal V DD .

Selon la première forme d'exécution de la figure 1, le premier miroir de courant comprend un premier transistor NMOS N1, dont la source est reliée à la masse, et le drain et la grille sont reliés ensemble, et un second transistor NMOS N2, dont la grille est reliée à la grille du premier transistor NMOS N1 et la source est reliée à la résistance à condensateur commuté 12, ainsi qu'à un condensateur de filtrage Cf. La résistance à condensateur commuté 12 et le condensateur de filtrage Cf sont également connectés à la borne de masse dans cette forme d'exécution.According to the first embodiment of the figure 1 , the first current mirror comprises a first NMOS transistor N1, the source of which is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N2, the gate of which is connected to the gate of the first transistor NMOS N1 and the source is connected to the switched capacitor resistor 12, as well as a filter capacitor Cf. The switched capacitor resistor 12 and the filter capacitor C f are also connected to the ground terminal in this form of 'execution.

Le drain et la grille du premier transistor NMOS N1 sont reliés au drain d'un premier transistor PMOS P1 du second miroir de courant. Le drain du second transistor NMOS N2 est relié à la grille et au drain d'un second transistor PMOS P2 du second miroir de courant. La grille du premier transistor PMOS P1 est reliée à la grille du second transistor PMOS P2. Le second miroir de courant comprend encore un troisième transistor PMOS P3 monté en parallèle des premier et second transistors PMOS P1, P2. La grille du troisième transistor PMOS P3 est reliée aux grilles des premier et second transistors PMOS P1, P2. Les sources des premier, second et troisième transistors PMOS P1, P2, P3 sont connectées à la borne de potentiel haut VDD de la source de tension. Le drain du troisième transistor PMOS P3 fournit le courant de référence Iref du générateur de courant de référence 2.The drain and the gate of the first NMOS transistor N1 are connected to the drain of a first PMOS transistor P1 of the second current mirror. The drain of the second NMOS transistor N2 is connected to the gate and to the drain of a second PMOS transistor P2 of the second current mirror. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2. The second current mirror further comprises a third PMOS transistor P3 mounted in parallel with the first and second PMOS transistors P1, P2. The gate of the third PMOS transistor P3 is connected to the gates of the first and second PMOS transistors P1, P2. The sources of the first, second and third PMOS transistors P1, P2, P3 are connected to the high potential terminal V DD of the voltage source. The drain of the third PMOS transistor P3 supplies the reference current I ref of the reference current generator 2.

Comme une résistance à condensateur commuté 12 est reliée à la source du second transistor NMOS N2, ce transistor NMOS N2 est N fois plus grand que le premier transistor NMOS N1, qui est considéré comme un transistor unitaire. Cela signifie que le second transistor NMOS N2 est composé de N premiers transistors NMOS N1, où N est un nombre entier plus grand ou égal à 2. Il peut par exemple être choisi N = 6 de manière à avoir un second transistor N2 6 fois plus grand que le premier transistor N1 ou au moins avoir une largeur de canal MOS 6 fois plus grande que la largeur de canal MOS du premier transistor N1.Since a switched capacitor resistor 12 is connected to the source of the second NMOS transistor N2, this NMOS transistor N2 is N times larger than the first NMOS transistor N1, which is considered as a unit transistor. This means that the second NMOS transistor N2 is composed of N first NMOS transistors N1, where N is an integer greater than or equal to 2. It can for example be chosen N = 6 so as to have a second transistor N2 6 times more larger than the first transistor N1 or at least have an MOS channel width 6 times greater than the MOS channel width of the first transistor N1.

La résistance à condensateur commuté 12 comprend donc un condensateur C, dont une première électrode est reliée à un premier commutateur 4 et à un second commutateur 5. Une seconde électrode du condensateur C est reliée à la borne de masse. Dans la technologie CMOS du procédé de fabrication du circuit électronique, ce condensateur C peut être un condensateur du type CMOS à accumulation ou un condensateur à électrode métallique à oxyde mince. Cela permet d'avoir une résistance à condensateur commuté 12 avec une précision de l'ordre de ±5%, alors qu'une résistance standard intégrée 8 est réalisée avec une précision de l'ordre de ±30%.The switched capacitor resistor 12 therefore comprises a capacitor C, a first electrode of which is connected to a first switch 4 and to a second switch 5. A second electrode of the capacitor C is connected to the ground terminal. In the CMOS technology of the electronic circuit fabrication process, this capacitor C can be a capacitor of the CMOS accumulation type or a capacitor with a thin oxide metal electrode. This makes it possible to have a switched capacitor resistor 12 with an accuracy of the order of ±5%, whereas a standard integrated resistor 8 is produced with an accuracy of the order of ±30%.

Le premier commutateur 4 est disposé entre la première électrode du condensateur C et la borne de masse, alors que le second commutateur 5 est disposé entre la première électrode du condensateur C et la source du second transistor NMOS N2. Le premier commutateur 4 est commandé par un premier signal de commande Φ1, alors que le second commutateur 5 est commandé alternativement par un second signal de commande Φ2. Le premier commutateur 4 est fermé, quand le second commutateur 5 est ouvert, dans une première phase, et le premier commutateur 4 est ouvert, quand le second commutateur 5 est fermé, dans une seconde phase. Chaque commutateur peut avantageusement être réalisé au moyen d'un transistor MOS, par exemple un transistor NMOS, qui est commandé sur sa grille par le signal de commande correspondant.The first switch 4 is arranged between the first electrode of capacitor C and the ground terminal, while the second switch 5 is arranged between the first electrode of capacitor C and the source of the second NMOS transistor N2. The first switch 4 is controlled by a first control signal Φ1, while the second switch 5 is controlled alternately by a second control signal Φ2. The first switch 4 is closed, when the second switch 5 is open, in a first phase, and the first switch 4 is open, when the second switch 5 is closed, in a second phase. Each switch can advantageously be made by means of an MOS transistor, for example an NMOS transistor, which is controlled on its gate by the corresponding control signal.

La figure 2 représente de manière simplifiée les deux signaux de commande Φ1 et Φ2, qui sont de préférence non recouvrant. Ces signaux de commande peuvent être obtenus par l'intermédiaire d'une base de temps avec un oscillateur à quartz. Cette base de temps de l'oscillateur à quartz peut également cadencer les opérations de l'unité de traitement 7. Chaque signal de commande comprend une impulsion rectangulaire de commande par période temporelle T. L'impulsion rectangulaire du premier signal de commande Φ1 est d'une durée t1, qui peut être égale à T/4, alors que l'impulsion rectangulaire du second signal de commande Φ2 est d'une durée t2, qui peut être aussi égale à T/4. Un espace temporel de T/4 entre les impulsions rectangulaires des premier et second signaux de commande Φ1 et Φ2 peut aussi être envisagé. L'impulsion rectangulaire à l'état "1" du premier signal de commande Φ1 commande la fermeture du premier commutateur 4, alors que l'impulsion rectangulaire à l'état "1" du second signal de commande Φ2 commande la fermeture du second commutateur 5.The picture 2 represents in a simplified way the two control signals Φ1 and Φ2, which are preferably not overlapping. These control signals can be obtained via a time base with a quartz oscillator. This quartz oscillator time base can also clock the operations of the processing unit 7. Each control signal comprises one rectangular control pulse per time period T. The rectangular pulse of the first control signal Φ1 is d 'a duration t1, which can be equal to T/4, whereas the rectangular pulse of the second control signal Φ2 has a duration t2, which can also be equal to T/4. A time space of T/4 between the rectangular pulses of the first and second control signals Φ1 and Φ2 can also be considered. The rectangular pulse at state "1" of the first control signal Φ1 controls the closing of the first switch 4, while the rectangular pulse at state "1" of the second control signal Φ2 controls the closing of the second switch 5.

La résistance équivalente, obtenue par la commande des premier et second commutateurs 4 et 5 avec les premier et second signaux de commande Φ1 et Φ2, est égale à T/C. T est la période de chaque signal de commande et C définit la capacité du condensateur. En modifiant la période T, la valeur résistive de la résistance équivalente peut être modifiée. Cette résistance équivalente de l'unité maître 2 peut être établie avec une précision de ±5% selon le procédé de fabrication du circuit électronique intégré dans un substrat en silicium traditionnel. Cette résistance équivalente 12 peut être identique à la résistance programmable 8 adaptée numériquement dans l'unité esclave 3 après la calibration du courant PTAT.The equivalent resistance, obtained by controlling the first and second switches 4 and 5 with the first and second control signals Φ1 and Φ2, is equal to T/C. T is the period of each control signal and C defines the capacitance of the capacitor. By changing the period T, the resistive value of the equivalent resistance can be changed. This equivalent resistance of the master unit 2 can be established with an accuracy of ±5% according to the manufacturing method of the electronic circuit integrated in a traditional silicon substrate. This equivalent resistor 12 may be identical to the programmable resistor 8 digitally adapted in the slave unit 3 after the calibration of the PTAT current.

A la suite de la calibration du courant de sortie PTAT IOUT, le générateur du courant de référence 2 et la base de temps pour la fourniture des signaux de commande Φ1 et Φ2 peuvent être déconnectés. Uniquement le générateur du courant PTAT calibré reste fonctionnel avec une précision du courant de sortie PTAT IOUT garanti avec une précision, qui peut être d'au moins ±5% de la valeur attendue.Following the calibration of the output current PTAT I OUT , the reference current generator 2 and the time base for supplying the control signals Φ1 and Φ2 can be disconnected. Only the calibrated PTAT current generator remains functional with an accuracy of the output current PTAT I OUT guaranteed with an accuracy, which can be at least ±5% of the expected value.

De manière similaire à l'unité maître 2, l'unité esclave PTAT 3 ou le générateur de courant PTAT 3 comprend un premier miroir de courant composé de transistors N11, N12 d'un premier type de conductivité, par exemple de transistors de type NMOS. L'unité esclave PTAT 3 comprend encore un second miroir de courant composé de transistors P11, P12, P13 d'un second type de conductivité, par exemple de transistors de type PMOS. Les premier et second miroirs de courant sont montés en série entre deux bornes d'une source de tension d'alimentation VDD. Le premier miroir de courant est de préférence relié à la première borne de la source de tension, qui est dans ce cas la borne de masse, alors que le second miroir de courant est de préférence relié à la seconde borne de la source de tension, qui est la borne de potentiel haut VDD.In a similar way to the master unit 2, the PTAT slave unit 3 or the PTAT current generator 3 comprises a first current mirror composed of transistors N11, N12 of a first type of conductivity, for example NMOS type transistors . The PTAT slave unit 3 further comprises a second current mirror composed of transistors P11, P12, P13 of a second type of conductivity, for example PMOS type transistors. The first and second current mirrors are connected in series between two terminals of a supply voltage source V DD . The first current mirror is preferably connected to the first terminal of the voltage source, which in this case is the ground terminal, while the second current mirror is preferably connected to the second terminal of the voltage source, which is the high potential terminal V DD .

Comme montré à la figure 1, le premier miroir de courant comprend un premier transistor NMOS N11, dont la source est reliée à la masse, et le drain et la grille sont reliés ensemble, et un second transistor NMOS N12, dont la grille est reliée à la grille du premier transistor NMOS N11 et la source est reliée à la résistance programmable 8, qui est également reliée à la borne de masse.As shown at figure 1 , the first current mirror comprises a first NMOS transistor N11, whose source is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N12, whose gate is connected to the gate of the first transistor NMOS N11 and the source is connected to the programmable resistor 8, which is also connected to the ground terminal.

Le drain et la grille, du premier transistor NMOS N11 sont reliés au drain d'un premier transistor PMOS P11 du second miroir de courant. Le drain du second transistor NMOS N12 est relié à la grille et au drain d'un second transistor PMOS P12 du second miroir de courant. La grille du premier transistor PMOS P11 est reliée à la grille du second transistor PMOS P12. Le second miroir de courant de l'unité esclave PTAT 3 comprend encore un troisième transistor PMOS P13 monté en parallèle des premier et second transistors PMOS P11, P12. La grille du troisième transistor PMOS P13 est reliée aux grilles des premier et second transistors PMOS P11, P12. Les sources des premier, second et troisième transistors PMOS P11, P12, P13 sont connectées à la borne de potentiel haut VDD de la source de tension. Le drain du troisième transistor PMOS P13 fournit le courant de sortie PTAT IOUT du générateur de courant PTAT 3.The drain and the gate of the first NMOS transistor N11 are connected to the drain of a first PMOS transistor P11 of the second current mirror. The drain of the second NMOS transistor N12 is connected to the gate and to the drain of a second PMOS transistor P12 of the second current mirror. The gate of the first PMOS transistor P11 is connected to the gate of the second PMOS transistor P12. The second current mirror of the PTAT slave unit 3 further comprises a third PMOS transistor P13 connected in parallel with the first and second PMOS transistors P11, P12. The gate of the third PMOS transistor P13 is connected to the gates of the first and second PMOS transistors P11, P12. The sources of the first, second and third PMOS transistors P11, P12, P13 are connected to the high potential terminal V DD of the voltage source. The drain of the third PMOS transistor P13 supplies the output current PTAT I OUT of the current generator PTAT 3.

Comme la résistance programmable 8 est reliée à la source du second transistor NMOS N12, ce transistor NMOS N2 est N' fois plus grand que le premier transistor NMOS N11, qui est considéré comme un transistor unitaire. Cela signifie que le second transistor NMOS N12 est composé de N' premiers transistors NMOS N11, où N' est un nombre entier plus grand ou égal à 2. Il peut par exemple être choisi N' = 6 comme pour le second transistor N2 de l'unité maître 2. Cela permet d'avoir un second transistor N12 6 fois plus grand que le premier transistor N11 ou au moins avoir une largeur de canal MOS 6 fois plus grande que la largeur de canal MOS du premier transistor N11. Cependant le nombre N' peut être différent du nombre N.As the programmable resistor 8 is connected to the source of the second NMOS transistor N12, this NMOS transistor N2 is N′ times larger than the first NMOS transistor N11, which is considered as a single transistor. This means that the second NMOS transistor N12 is composed of N' first NMOS transistors N11, where N' is an integer greater than or equal to 2. It can for example be chosen N'=6 as for the second transistor N2 of the master unit 2. This makes it possible to have a second transistor N12 6 times larger than the first transistor N11 or at least to have a MOS channel width 6 times larger than the MOS channel width of the first transistor N11. However, the number N' can be different from the number N.

Il est encore à noter que le troisième transistor PMOS P13 peut également être prévu M fois plus grand que le premier transistor PMOS P11 et le second transistor PMOS P12 du second miroir de courant de l'unité esclave PTAT 3. M est un nombre entier plus grand ou égal à 1. Dans le cas où M est égal à 1, la résistance programmable 8, qui a été adaptée, peut être équivalente à la résistance à condensateur commuté 12 de l'unité maître 2.It should also be noted that the third PMOS transistor P13 can also be provided M times larger than the first PMOS transistor P11 and the second PMOS transistor P12 of the second current mirror of the slave unit PTAT 3. M is an integer plus large or equal to 1. In the case where M is equal to 1, the programmable resistor 8, which has been adapted, can be equivalent to the switched capacitor resistor 12 of the master unit 2.

Selon une variante d'exécution du circuit électronique 1 non illustrée, il peut être utilisé à la place du troisième transistor PMOS P13, un ensemble de transistors unitaires combinés avec des commutateurs contrôlés numériquement. En lieu et place d'adapter numériquement la résistance programmable 8, il peut être envisagé d'avoir une résistance 8 de valeur définie, et d'adapter numériquement un rapport dimensionnel de transistors PMOS du second miroir de courant, qui fournissent le courant de sortie PTAT IOUT. Un mot binaire d'adaptation est fourni au terme des cycles de calibration par l'algorithme de dichotomie. Ce mot binaire pour configurer l'ensemble de transistors est mémorisé dans l'unité de traitement 7.According to a variant of the electronic circuit 1 not illustrated, it can be used instead of the third PMOS transistor P13, a set of unitary transistors combined with digitally controlled switches. Instead of digitally adapting the programmable resistor 8, it can be envisaged to have a resistor 8 of defined value, and to digitally adapt a dimensional ratio of PMOS transistors of the second current mirror, which provide the output current PTAT I OUT . An adaptation binary word is supplied at the end of the calibration cycles by the dichotomy algorithm. This binary word for configuring the set of transistors is stored in the processing unit 7.

Il peut aussi être envisagé d'avoir plusieurs résistances à condensateur commuté disposés en parallèle et commandées chacune par deux signaux de commande propres à chaque résistance à condensateur commuté.It can also be envisaged to have several resistors with switched capacitor arranged in parallel and each controlled by two control signals specific to each resistor with switched capacitor.

A partir de la description qui vient d'être faite, plusieurs variantes de réalisation du circuit électronique à référence de courant PTAT peuvent être conçues par l'homme du métier sans sortir du cadre de l'invention définie par les revendications.From the description which has just been given, several variant embodiments of the electronic circuit with current reference PTAT can be designed by those skilled in the art without departing from the scope of the invention defined by the claims.

Claims (10)

  1. Electronic circuit (1) with a self-calibrated PTAT current reference, the electronic circuit (1) including a unit called master unit (2) which is a reference current generator (2) and a unit called slave unit (3), which is a PTAT current generator (3) dependent on at least one integrated resistor (8), for supplying a PTAT output current (IOUT), the PTAT current generator (3) including a first current mirror formed of NMOS transistors (N11, N12), and a second current mirror formed of PMOS transistors (P11, P12, P13), the first and second current mirrors of the slave unit (3) being series-mounted between two terminals of a supply voltage source (VDD), the first current mirror includes a first NMOS transistor (N11) and a second NMOS transistor (N12), in that the first NMOS transistor (N11) includes a source connected to an earth terminal, and a gate connected to a drain, in that the second NMOS transistor (N12) has a source connected to the resistor (8), which is connected to the earth terminal, a gate connected to the gate of the first NMOS transistor (N11), in that the second current mirror includes a first PMOS transistor (P11), a second PMOS transistor (P12) and a third PMOS transistor (P13), the three PMOS transistors each having a source connected to a high potential terminal of the voltage source (VDD) and gates connected to each other, in that the first PMOS transistor (P11) includes a drain connected to the gate and to the drain of the first NMOS transistor (N11), in that the second PMOS transistor (P12) includes a drain connected to the gate thereof and to a drain of the second NMOS transistor (N12), and in that the third PMOS transistor (P13) includes a drain for supplying the PTAT output current (IOUT).
    characterised in that the reference current generator (2) depends on at least one switched capacitor resistor (12), for supplying a reference current (Iref),
    in that the reference current generator (2) includes a first current mirror formed of NMOS transistors (N1, N2), and a second current mirror formed of PMOS transistors (P1, P2, P3), the first and second current mirrors of the master unit (2) being series-mounted between two terminals of a supply voltage source (VDD), in that the first current mirror includes a first NMOS transistor (N1) and a second NMOS transistor (N2), in that the first NMOS transistor (N1) includes a source connected to an earth terminal, and a gate connected to a drain, in that the second NMOS transistor (N2) has a source connected to the switched capacitor resistor (12), which is connected to the earth terminal, a gate connected to the gate of the first NMOS transistor (N1), in that the second current mirror includes a first PMOS transistor (P1), a second PMOS transistor (P2) and a third PMOS transistor (P3), the three PMOS transistors each having a source connected to a high potential terminal of the voltage source (VDD) and gates connected to each other, in that the first PMOS transistor (P1) includes a drain connected to the gate and to the drain of the first NMOS transistor (N1), in that the second PMOS transistor (P2) includes a drain connected to the gate and to a drain of the second NMOS transistor (N2), and in that the third PMOS transistor (P3) includes a drain for supplying the reference current (Iref),
    in that the reference current (Iref) supplied by the third PMOS transistor (P3) of the master unit (2) and the PTAT output current (IOUT) supplied by the third transistor (P13) of the slave unit (3) are compared in a comparator (6) so as to digitally adapt the integrated resistor (8), which is programmable, or to digitally adapt a dimensional ratio of PMOS transistors (P11, P12, P13) of a current mirror in the PTAT current generator, to supply the adapted PTAT output current (IOUT), and
    in that the comparator (6) is connected to a processing unit (7) to receive output data from the comparator (6), resulting from the comparison between the reference current (Iref) and the PTAT output current (IOUT) to control the digital adaptation of the programmable resistor (8) or of the dimensional ratio of the transistors (P11, P12, P13).
  2. Electronic circuit (1) according to claim 1, characterised in that the processing unit (7) is intended to implement a dichotomy algorithm for the cyclical adaptation of the programmable resistor (8) or of the dimensional ratio of the transistors (P11, P12, P13), and in that the processing unit includes a memory for storing a final binary word for the digital adaptation of the programmable resistor (8) or of the dimensional ratio of the transistors (P11, P12, P13).
  3. Electronic circuit (1) according to claim 1, characterised in that the second NMOS transistor (N2) is N times greater than the first NMOS transistor (N1), where N is an integer number greater than or equal to 2, and preferably equal to 6.
  4. Electronic circuit (1) according to claim 1, characterised in that the switched capacitor resistor (12) includes a capacitor (C), a first switch (4) connected in parallel to the capacitor, and a second switch (5) connected between an electrode of the capacitor and the source of the second transistor (N2) of the first current mirror of the reference current generator,
    in that the first switch (4) is controlled by a first control signal (Φ1), and in that the second switch (5) is controlled by a second control signal (Φ2), the first and second control signals being generated via a time base and arranged such that the first switch is open when the second switch is closed, and vice versa.
  5. Electronic circuit (1) according to claim 1, characterised in that the second NMOS transistor (N12) is N' times greater than the first NMOS transistor (N1), where N' is an integer number greater than or equal to 2, and preferably equal to 6.
  6. Electronic circuit (1) according to claim 1, characterised in that the third PMOS transistor (P13) is formed of a set of unit transistors, which are combined with digitally controlled switches to adapt the PTAT output current (IOUT).
  7. Method for calibrating a PTAT current source of the electronic circuit (1) according to any of the preceding claims, characterised in that the method includes the steps of:
    - supplying a PTAT output current (IOUT) of the PTAT current generator (3), by the third PMOS transistor (P13) of the PTAT current generator,
    - supplying a reference current (Iref) of the reference current generator (2), by the third PMOS transistor (P3) of the reference current generator,
    - comparing the PTAT output current (IOUT) and the reference current (Iref),and
    - digitally adapting the programmable integrated resistor (8), or a dimensional ratio of the PMOS transistors (P11, P12, P13) of a current mirror in the PTAT current generator.
  8. Method according to claim 7, characterised in that the digital adaptation is performed over a certain number of cycles according to a dichotomy algorithm in a processing unit (7).
  9. Method according to claim 8, characterised in that a memorisation of the digital word supplied by the processing unit (7) is performed in a memory of the processing unit at the end of the PTAT output current (IOUT) adaptation cycles.
  10. Method according to one of claims 8 and 9, characterised in that at the end of the PTAT output current (IOUT) adaptation cycles, the reference current generator (2) is disconnected, as the supply of control signals from the switched capacitor resistor (12).
EP13198965.9A 2013-12-20 2013-12-20 Electronic circuit with self-calibrated PTAT current reference, and method for operating same Active EP2887176B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP13198965.9A EP2887176B1 (en) 2013-12-20 2013-12-20 Electronic circuit with self-calibrated PTAT current reference, and method for operating same
US14/558,839 US9442509B2 (en) 2013-12-20 2014-12-03 Electronic circuit with self-calibrated PTAT current reference and method for actuating the same
TW103142196A TWI675275B (en) 2013-12-20 2014-12-04 Electronic circuit with self-calibrated ptat current reference and method for actuating the same
JP2014253730A JP5918344B2 (en) 2013-12-20 2014-12-16 Electronic circuit with self-calibrated PTAT current reference and method of operating same
CN201410784806.4A CN104731148B (en) 2013-12-20 2014-12-17 There is the electronic circuit of PTAT current benchmark and activate the method for this circuit
KR1020140184793A KR101749794B1 (en) 2013-12-20 2014-12-19 Electronic circuit with self-calibrated ptat current reference and method for actuating the same
HK15112380.6A HK1211715A1 (en) 2013-12-20 2015-12-16 Electronic circuit with self-calibrated ptat current reference and method for actuating the same ptat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP13198965.9A EP2887176B1 (en) 2013-12-20 2013-12-20 Electronic circuit with self-calibrated PTAT current reference, and method for operating same

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EP2887176A1 EP2887176A1 (en) 2015-06-24
EP2887176B1 true EP2887176B1 (en) 2022-09-14

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EP (1) EP2887176B1 (en)
JP (1) JP5918344B2 (en)
KR (1) KR101749794B1 (en)
CN (1) CN104731148B (en)
HK (1) HK1211715A1 (en)
TW (1) TWI675275B (en)

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CN106055009A (en) * 2016-06-17 2016-10-26 中国科学院微电子研究所 High-precision band-gap reference circuit
CN108566173A (en) * 2018-06-11 2018-09-21 杨俊杰 A kind of RC time constant correcting circuits using CMOS technology chip interior
CN109341890B (en) * 2018-10-22 2021-05-14 安徽鸿创新能源动力有限公司 BMS temperature acquisition system and measurement method based on NTC temperature sensor
US10747254B1 (en) * 2019-09-03 2020-08-18 Globalfoundries Inc. Circuit structure for adjusting PTAT current to compensate for process variations in device transistor
CN113253787A (en) * 2021-06-17 2021-08-13 苏州裕太微电子有限公司 On-chip resistor correction circuit
US11962311B2 (en) 2021-10-20 2024-04-16 Samsung Electronics Co., Ltd. Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same
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HK1211715A1 (en) 2016-05-27
JP5918344B2 (en) 2016-05-18
EP2887176A1 (en) 2015-06-24
KR20150073122A (en) 2015-06-30
US9442509B2 (en) 2016-09-13
KR101749794B1 (en) 2017-06-21
CN104731148A (en) 2015-06-24
TW201541219A (en) 2015-11-01
CN104731148B (en) 2016-08-31
US20150177772A1 (en) 2015-06-25
TWI675275B (en) 2019-10-21
JP2015122494A (en) 2015-07-02

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