JP2013214915A - Oscillating device, semiconductor device, and method of operating oscillating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the frequency accuracy of an oscillating device (an on-chip oscillator).SOLUTION: An oscillating device includes: an oscillation circuit 25 generating a clock signal CKOUT on the basis of a voltage VCNT; a control circuit 26 generating signals CHOP and ZCHR synchronized with the clock signal CKOUT; a current generating circuit 22 generating a current I1 on the basis of a resistor R; a frequency voltage conversion circuit 23 converting the frequency of the signal ZCHR to a voltage Vfv by using the current I1 and generating a sampling voltage VSAMP; and an integration circuit 24 generating a voltage VCNT on the basis of the sampling voltage VSAMP and a voltage VREFC.

Description

  The present invention relates to a semiconductor device and can be suitably used for a semiconductor device using a clock signal, for example.

  2. Description of the Related Art Electronic devices and home appliances equipped with a semiconductor device such as a microcomputer are known. In response to demands for downsizing and cost reduction of these electronic devices and household electrical appliances, the reduction of external components necessary for semiconductor devices is being promoted. An on-chip oscillator is known as a technique for reducing external components in a clock generation circuit that generates a clock signal of a semiconductor device. The on-chip oscillator is a clock generation circuit built in the chip. On-chip oscillators do not require external components.

  An on-chip oscillator is disclosed in, for example, International Publication No. WO2011 / 101981. FIG. 1 is a circuit diagram showing a configuration of an on-chip oscillator disclosed in International Publication No. WO2011 / 101981. The on-chip oscillator (oscillator unit 102) includes a reference voltage generation circuit 110, a constant current generation circuit 111, a control circuit 112, a frequency voltage conversion circuit 113, an integration circuit 114, and a voltage control oscillation circuit 115. Yes. The voltage controlled oscillation circuit 115 generates the clock signal CKOUT based on the control voltage VCNT. The control circuit 112 generates a charge signal ZCHR based on the clock signal CKOUT. The reference voltage generation circuit 110 generates a reference voltage VREFI having temperature dependence and a power supply and a reference voltage VREFC having little temperature dependence. The constant current generating circuit 111 generates a reference current Iref (= Iconst) having almost no power source and temperature dependency using the reference voltage VREFI. The frequency voltage conversion circuit 113 converts the oscillation frequency of the charge signal ZCHR into a voltage using the reference current Iconst (= Iref). The integration circuit 114 integrates the voltage output from the frequency voltage conversion circuit 113 to generate a control voltage VCNT.

式（１）において、Ｒは、定電流発生回路１１１の抵抗Ｒ_ＯＳＣの抵抗値である。また、Ｃは、周波数電圧変換回路１１３の容量Ｃ１の容量値である。基準電圧ＶＲＥＦＣは、基準電圧発生回路１１０で生成する電圧であり、積分回路１１４の差動アンプＡＭＰ２に供給される。基準電圧ＶＲＥＦＩは、基準電圧発生回路１１０で生成する電圧であり、定電流発生回路１１１の差動アンプＡＭＰ１に供給される。 The on-chip oscillator is a clock generation circuit that forms a feedback loop with these circuits. The oscillation period T of the clock signal generated by the on-chip oscillator is expressed by the following equation (1).

In the formula (1), R is the resistance value of the resistor R _OSC of the constant current generating circuit 111. Further, C is a capacitance value of the capacitor C1 of the frequency voltage conversion circuit 113. The reference voltage VREFC is a voltage generated by the reference voltage generation circuit 110 and is supplied to the differential amplifier AMP2 of the integration circuit 114. The reference voltage VREFI is a voltage generated by the reference voltage generation circuit 110 and is supplied to the differential amplifier AMP1 of the constant current generation circuit 111.

The constant current generation circuit 111 includes a differential amplifier AMP1, PMOS transistors T1 and T2, and a resistor _ROSC . A feedback loop constituted by the differential amplifier AMP1 and the MOS transistor T1, MOS transistors T1-side node of the resistors _{R OSC} becomes the same voltage value as the reference voltage VREFI. Therefore, the constant current generation circuit 111 can generate the reference current Iref obtained by dividing the reference voltage VREFI by the resistance R as represented by the following equation (2) (as described above, R is a resistance R _OSC resistance value).

The PMOS transistors T1 and T2 constitute a current mirror circuit. The current mirror circuit passes a reference current Iconst (= Iref) equal to the reference current Iref flowing through the PMOS transistor T1 to the PMOS transistor T2. The reference current Iconst (= Iref) is supplied to the frequency voltage conversion circuit 113. The reference current Iref generated by the constant current generation circuit 111 is a current having no temperature dependence. This is because the temperature characteristic is offset because the temperature dependence of the resistance value R of the resistor R _OSC and the temperature dependence of the reference voltage VREFI have opposite characteristics. The reference voltage generation circuit 110 creates temperature dependency of the resistance value of the resistor R _OSC and temperature dependency of the reference voltage VREFI having a reverse characteristic by temperature trimming. When the two-point temperature trimming is performed, the reference current Iref having no primary temperature dependency can be generated. When trimming is performed at three or more temperatures, the secondary temperature dependency can be canceled in addition to the primary. The absolute value of the oscillation frequency of the clock signal is made variable by switching the resistance value R of the resistor R _OSC .

Next, the operation of this on-chip oscillator will be described.
The reference voltage generation circuit 110 generates reference voltages VREFC and VREFI and outputs them to the constant current generation circuit 111 and the integration circuit 114, respectively. As described above, the constant current generation circuit 111 generates the reference current Iref (= Iconst) having no power supply and temperature dependency. The frequency voltage conversion circuit 113 charges the capacitor C1 using the reference current Iconst (= Iref) while the switch SW1 is turned on by the charge signal ZCHR. Thereby, the frequency of the charge signal ZCHR is converted to the voltage V. The converted voltage V is represented by the following expression (3) (as described above, C is the capacitance value of the capacitor C1).

  The control circuit 112 generates a charge signal ZCHR, a discharge signal DISC, and a sample signal SAMP using the output clock signal CKOUT. The charge signal ZCHR is a signal having the same pulse width as the cycle T of the clock signal CKOUT. The frequency voltage conversion circuit 113 samples the voltage V using the sample signal SAMP and outputs it to the integration circuit 114. The integrating circuit 114 is a parallel type switched capacitor integrating circuit. The integration circuit 114 integrates an error between the sampled voltage V and the reference voltage VREFC having no power supply and temperature dependency to generate a control voltage VCONT. By integrating the error between the voltage V and the reference voltage VREFC, the control voltage VCONT changes, and the period T, that is, the frequency (1 / T) of the clock signal CKOUT of the voltage controlled oscillation circuit 115 changes. When the sampled voltage V becomes equal to the reference voltage VREFC, the frequency of the clock signal CKOUT of the voltage controlled oscillation circuit 115 becomes a desired frequency and stable oscillation occurs.

  As a related technique, Japanese Unexamined Patent Application Publication No. 2011-166368 (US2011 / 193640 (A1)) discloses a semiconductor device. The semiconductor device includes a first on-chip oscillator, a temperature sensor, a voltage sensor, a power supply module, a storage unit, and a logic unit. The first on-chip oscillator receives a reference current and a reference voltage, and outputs a clock signal having a first frequency having a magnitude determined by the reference current and the reference voltage. The temperature sensor detects an ambient temperature of the first on-chip oscillator. The voltage sensor detects the value of the operating voltage of the first on-chip oscillator. The power supply module includes a reference circuit that generates a reference voltage, and generates the reference voltage, the reference current, and the operating voltage of the first on-chip oscillator based on the reference voltage output by the reference circuit. The storage unit stores a table defining the reference voltage and the trimming code of the reference current corresponding to the ambient temperature of the first on-chip oscillator and the operating voltage of the first on-chip oscillator. The logic unit reads trimming codes of the reference voltage and the reference current corresponding to the detected ambient temperature and operating voltage from the table, and based on the read trimming code, the reference current and the reference voltage Adjust the value.

  Japanese Patent Laid-Open No. 2006-319921 (US 2006/255856 (A1)) discloses an operational amplifier. The operational amplifier includes a differential pair section, a first switch section, a current mirror circuit section, and a second switch section. The first switch unit switches a signal input to the input terminal of the differential pair unit. The current mirror circuit unit becomes an active load of the differential pair unit. The second switch unit is connected between the differential pair unit and the current mirror circuit unit, and switches the connection between the differential pair unit and the current mirror circuit unit. The offset voltage is canceled by switching each of the first switch unit and the second switch unit.

  Japanese Unexamined Patent Application Publication No. 2009-124588 (US2009 / 128243 (A1)) discloses a semiconductor device. This semiconductor device includes a voltage controlled oscillation circuit, a frequency / voltage conversion circuit, a control voltage generation circuit, and an analog integration circuit. The voltage controlled oscillation circuit outputs an oscillation signal by oscillating at a frequency corresponding to the first control voltage. The frequency / voltage conversion circuit converts the frequency of the oscillation signal received from the voltage controlled oscillation circuit into a voltage. The control voltage generation circuit generates a new second control voltage having a level between the voltage converted by the frequency / voltage conversion circuit and the previously generated second control voltage. The analog integration circuit integrates the second control voltage to generate the first control voltage, and outputs the first control voltage to the voltage controlled oscillation circuit.

International Publication WO2011 / 101981 JP 2011-166368 A JP 2006-319921 A JP 2009-124588 A

In order to apply the on-chip oscillator to a wide range of applications (eg, UART communication), it is desirable to suppress the frequency fluctuation of the clock signal generated by the on-chip oscillator as low as possible and increase the accuracy. Specifically, the frequency variation of the clock signal generated by the on-chip oscillator is preferably within a desired range (eg, ± 1.0%) regardless of the process, power supply variation, and temperature variation. Therefore, in the example of FIG. 1, for example, ideally, switches the reference voltage VREFI the temperature dependence of the resistance _{R OSC,} capacitor C1 having a temperature dependent resistance _{R OSC,} to cancel the temperature dependency of the capacitance C1 By performing the temperature trimming, a frequency having no temperature dependency is generated (formula (1)). However, the conventional on-chip oscillator does not become an ideal state as shown in the equation (1), and it is difficult to achieve an accuracy improvement of a certain degree or more. According to the inventor's research, there are many errors due to the circuit, which makes it difficult to improve the frequency accuracy.

As one of the causes of the error, there is a current error I _missmatch generated in the current mirror circuit of the constant current generation circuit 111. However, it is Iconst = Iref ± _{I mismatch.} This current error I _missmatch occurs as follows. Even if the two PMOS transistors T1 and T2 of the current mirror circuit are manufactured in the same size and shape, a mismatch (offset) voltage ΔVth is generated in the threshold voltage Vth. The current error due to the offset voltage ΔVth is I _missmatch .

すなわち、カレントミラーのオフセット電圧ΔＶｔｈに起因してオンチップオシレータの周期Ｔ、すなわち周波数（１／Ｔ）が変動し、その精度が悪化してしまう。 At this time, the offset voltage ΔVth drifts with temperature. Therefore, the current error I _missmatch also drifts with temperature. As a result, the copy current Iconst of the current Iref to be transferred from the current mirror circuit to a frequency-voltage conversion circuit 113 (= Iref ± _{I mismatch),} it will also be divided by the temperature drift of at least the current error _{I mismatch.} Therefore, temperature dependency occurs in the reference current Iconst. At this time, the equation (1) indicating the ideal state is actually the following equation (4).

That is, due to the offset voltage ΔVth of the current mirror, the cycle T of the on-chip oscillator, that is, the frequency (1 / T) fluctuates and the accuracy deteriorates.

  In the conventional circuit, measures are taken to increase the size of the two PMOS transistors against the temperature drift of the mismatch (offset) voltage ΔVth. Thus, the mismatch voltage ΔVth is physically reduced to a level that does not affect the frequency accuracy. However, if this measure is taken, there are side effects such as an increase in the area of the IP corresponding to an increase in the size of the transistor and an increase in the start-up time of the on-chip oscillator for driving a device with a large area. It is not necessarily a preferable measure.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in an oscillation device that generates a clock signal, a chopping circuit is connected to a current mirror circuit of a current generation circuit, and an input-side current path and an output-side current path are used to generate a clock signal. Switch alternately with no effect.

  According to the embodiment, it is possible to improve the frequency accuracy of the oscillation device (on-chip oscillator).

FIG. 1 is a circuit diagram showing a configuration of an on-chip oscillator disclosed in International Publication WO2011 / 101981. FIG. 2 is a block diagram illustrating a configuration example of a semiconductor device to which the oscillation device according to the first embodiment is applied. FIG. 3 is a block diagram showing a modification of the configuration of the CPG according to the first embodiment. FIG. 4 is a block diagram illustrating a configuration example of the oscillation device according to the first embodiment. FIG. 5 is a block diagram illustrating a configuration example of the current generation circuit, the frequency voltage conversion circuit, and the integration circuit according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration example of the current generation circuit and the frequency voltage conversion circuit according to the first embodiment. FIG. 7 is a plan view showing a layout example of the current mirror circuit and the chopping circuit. FIG. 8 is a circuit diagram illustrating a specific configuration example of the resistor R. FIG. 9 is a plan view showing a specific layout example of the resistor R. FIG. FIG. 10 is a circuit diagram illustrating a specific configuration example of the control circuit. FIG. 11 is a timing chart showing an operation example of the control circuit. FIG. 12A is a timing chart illustrating an operation example of the oscillation device according to the first embodiment. FIG. 12B is a timing chart illustrating another operation example of the oscillation device according to the first embodiment. FIG. 13 is a block diagram illustrating another configuration example of the semiconductor device to which the oscillation device according to the first embodiment is applied. FIG. 14 is a block diagram illustrating a configuration example of a current generation circuit according to the second embodiment. FIG. 15 is a circuit diagram showing a configuration example of a current generation circuit and a frequency-voltage conversion circuit according to the second embodiment. FIG. 16 is a block diagram illustrating a configuration example of the oscillation device according to the third embodiment. FIG. 17 is a block diagram illustrating a configuration example of a reference voltage generation circuit, a current generation circuit, a frequency voltage conversion circuit, and an integration circuit according to the third embodiment. FIG. 18 is a circuit diagram showing a configuration example of a current generation circuit and a frequency voltage conversion circuit according to the third embodiment. FIG. 19 is a block diagram illustrating a configuration example of a current generation circuit according to the fourth embodiment. FIG. 20 is a circuit diagram illustrating a configuration example of a current generation circuit and a frequency-voltage conversion circuit according to the fourth embodiment.

  Hereinafter, embodiments of an oscillation device, a semiconductor device, and an operation method of the oscillation device will be described with reference to the accompanying drawings.

(First embodiment)
A configuration of a semiconductor device to which the oscillation device according to the first embodiment is applied will be described. FIG. 2 is a block diagram illustrating a configuration example of a semiconductor device to which the oscillation device according to the first embodiment is applied. The semiconductor device 1 is exemplified by a microcomputer, and includes a CPU (Central Processing Unit) 5, a peripheral function block 6, a flash memory 4, a register 3, and a CPG (Clock Pulse Generator) 2. The peripheral function block 6 includes a RAM (Random Access Memory 15), a BUS 16, an ADC (Analog Digital Converter) 17, and a Timer 18. The CPG 2 includes an on-chip oscillator 11 as an oscillation device. The on-chip oscillator 11 can generate a clock signal of several tens of MHz necessary for the operation of each of the above-described components of the semiconductor device 1 (eg, a microcomputer) as a single unit. The on-chip oscillator 11 receives data stored in the flash memory 4 as a control signal via the register 3 when the semiconductor device 1 is activated, and generates a clock signal based on the data. The clock signal generated by the on-chip oscillator 11 can be used as a main clock such as a system clock or a bus clock. Since the semiconductor device 1 includes the on-chip oscillator 11 as the oscillation device according to the present embodiment, the effect of the on-chip oscillator 11 described later can be obtained.

  Here, a modified example of the CPG according to the present embodiment will be described. FIG. 3 is a block diagram showing a modification of the configuration of the CPG according to the first embodiment. In the CPG 2, the on-chip oscillator 11 may constitute a clock generation circuit together with the frequency dividers A 12 and B 13 and supply a clock signal to the CPU 5 and the peripheral function block 6. A clock signal may be output from the frequency divider A12. The reason why the frequency divider A12 and the frequency divider B13 are incorporated is to increase the choice of clock frequency by combining the frequency division numbers.

  Next, the configuration of the oscillation device according to the first embodiment will be described. FIG. 4 is a block diagram illustrating a configuration example of the oscillation device according to the first embodiment. The on-chip oscillator 11 as an oscillation device includes a current generation circuit 22, a frequency / voltage conversion circuit 23, an integration circuit 24, an oscillation circuit 25, and a control circuit 26. The on-chip oscillator 11 is a clock generation circuit that forms a feedback loop with these circuits.

  The oscillation circuit 25 generates a clock signal CKOUT based on the control voltage VCNT. Based on the clock signal CKOUT, the control circuit 26 is a chopping signal (first control signal) CHOP, a charge signal (second control signal) ZCHR, a sampling signal (third control signal) SAMP, and a discharge synchronized with the clock signal CKOUT. A signal (fourth control signal) DISC is generated. The current generation circuit 22 generates a reference current I1 in response to a control signal and a chopping signal CHOP from the outside (flash memory 4, register 3). The frequency voltage conversion circuit 23 converts the frequency of the charge signal ZCHR into the converted output voltage Vfv using the reference current I1, samples the converted output voltage Vfv in response to the sampling signal SAMP, and generates the sampling voltage VSAMP. . The integration circuit 24 generates the control voltage VCNT based on the sampling voltage VSAMP and the reference voltage VREFC.

  Next, configuration examples of the current generation circuit 22, the frequency voltage conversion circuit 23, and the integration circuit 24 will be described. FIG. 5 is a block diagram illustrating a configuration example of the current generation circuit, the frequency voltage conversion circuit, and the integration circuit according to the first embodiment. The current generation circuit 22 includes a current mirror circuit 30, a chopping circuit 31, and a resistor R. The current mirror circuit 30 includes, for example, PMOS transistors MP1 and MP2. The PMOS transistor MP1 has a source connected to the power supply voltage VDD, a gate connected to the node VF, and a drain connected to the chopping circuit 31. The PMOS transistor MP2 has a source connected to the power supply voltage VDD, a gate connected to the gate and the node VF of the PMOS transistor MP1, and a drain connected to the chopping circuit 31. One of the PMOS transistor MP1 and the PMOS transistor MP2 generates a reference current Iref that flows through the resistor R, and the other generates a reference current I1 that is substantially equal to the reference current Iref. However, the current mirror circuit 30 is not limited to the configuration shown in FIG. For example, in addition to the PMOS transistors MP1 and MP2, a configuration having an additional element having a symmetrical arrangement may be used.

  When the current mirror circuit 30 is composed of PMOS transistors MP1 and MP2, it is designed so that the same current value flows through the PMOS transistors MP1 and MP2. That is, the PMOS transistors MP1 and MP2 are preferably designed with the same size and shape. With the same size, the gate length L and the gate width W of the transistor are designed to be the same. However, even if the gate width W is the same, two transistors having a gate width W / 2 obtained by dividing the gate width of one transistor into two are arranged in parallel, and the other transistor is arranged with one transistor having a gate width W. However, since the same current value cannot be obtained, it is preferable to arrange the same number of transistors having the same shape.

  The chopping circuit 31 has one input terminal connected to the drain of the PMOS transistor MP1, and the other input terminal connected to the drain of the PMOS transistor MP2. One output terminal is connected to the node VF, and the other output terminal is connected to the frequency-voltage conversion circuit 23 (node N1 thereof). Thereby, in response to the chopping signal CHOP, the chopping circuit 31 has one of the drains of the PMOS transistor MP1 and the PMOS transistor MP2 as the node VF (resistor R) and the other as the frequency voltage conversion circuit 23 (node N1 thereof). In addition, the connection is periodically switched alternately. The resistor R has one end connected to the node VF and the other end connected to the ground.

  The resistor R is a variable resistor, and a resistance value is set by a control signal based on data of the flash memory 4 and the register 3. The value of the resistor R is adjusted so that a desired reference current Iref = VREFI / R flows through the current path of one of the PMOS transistors MP1 and MP2, the chopping circuit 31 and the resistor R. Note that VREFI is the potential of the node VF. The absolute value of the oscillation frequency of the clock signal is variable by switching the resistor R and changing the reference current Iref. In other words, the value of the resistor R is adjusted so that the oscillation frequency of the clock signal becomes a desired frequency (= desired reference current). As an actual setting, for example, in a manufacturing test (wafer test or final test), the on-chip oscillator 11 is chopped at a predetermined temperature to set the resistance R so as to have a desired frequency.

  In the present embodiment, as described above, the chopping circuit 31 is connected to the current mirror circuit 30 of the current generation circuit. Thereby, the path of the input side current and the path of the output side current of the current mirror circuit 30 are chopped between the first current path passing through the PMOS transistor MP1 and the second current path passing through the PMOS transistor MP2. In response to the signal, it can be switched alternately. That is, as a countermeasure against the mismatch voltage ΔVth of the PMOS transistors MP1 and MP2, by adopting the chopping circuit 31 in the current generation circuit 22, the connection destinations of the drains of the PMOS transistors MP1 and MP2 are cycled in response to the chopping signal CHOP signal. Can be alternately switched and connected. Thereby, mismatch voltage ΔVth is substantially canceled, and mismatch voltage ΔVth can be reduced.

  In other words, in the present embodiment, even when there is a mismatch voltage ΔVth between the PMOS transistors MP1 and MP2, the connection destinations of the drains of the PMOS transistors MP1 and MP2 are alternately alternately connected at a predetermined temperature to connect the resistors R Adjustments are being made. As a result, it is possible to set the value of the resistor R in which the influence of the mismatch voltage ΔVth is substantially canceled. As a result, even when the operating temperature of the on-chip oscillator 11 may deviate from the predetermined temperature, the connection destinations of the drains of the PMOS transistors MP1 and MP2 are alternately alternated in the same manner as when the value of the resistor R is set. By operating the current generation circuit 22 by switching, the reference current I1 in which the influence of the mismatch voltage ΔVth is substantially canceled can be output.

  The frequency voltage conversion circuit 23 includes switches SW1, SW2, and SW3 and a capacitor C. The switches SW1 and SW2 are connected in series. The switch SW1 has one end connected to the node N1 (connected to the current generation circuit 22) and the other end connected to the node Nc. The switch SW1 is turned on or off in response to the charge signal ZCHR. The switch SW2 has one end connected to the node Nc and the other end connected to the ground. The switch SW2 is turned on or off in response to the discharge signal DISC. The capacitor C has one end connected to the node Nc and the other end connected to the ground. The capacitor C is charged with the reference current I1 from the current generation circuit 22 when the switch SW1 is turned on and the switch SW2 is turned off. The capacitor C is discharged to the ground via the switch SW2 when the switch SW1 is turned off and the switch SW2 is turned on. The switch SW3 has one end connected to the node Nc and the other end connected to the integration circuit 24. The switch SW3 is turned on or off in response to the sampling signal SAMP. The voltage (conversion output voltage Vfv) of the node Nc sampled when the switch SW3 is on is supplied to the integration circuit 24 as the sampling voltage VSAMP.

  The integrating circuit 24 is a parallel switched capacitor integrating circuit, and includes a differential amplifier AMP2 and an integrating capacitor Cint. An integration capacitor Cint is connected in parallel to the inverting input terminal and the output terminal of the differential amplifier AMP2. The inverting input terminal of the differential amplifier AMP2 is connected to the switch SW3, the non-inverting input terminal is connected to a wiring for supplying the reference voltage VREFC, and the output terminal is connected to the oscillation circuit 25. The integration circuit 24 integrates a difference voltage (error) between the reference voltage VREFC and the sampled voltage (conversion output voltage) Vfv of the node Nc as an error charge in the integration capacitor Cint. As a result, the oscillation voltage is changed by changing the control voltage VCNT supplied to the oscillation circuit 25, and the converted voltage output Vfv and the reference voltage VREFC are fed back so as to be equal to each other, thereby controlling the frequency of the oscillation circuit 25.

  Next, specific configuration examples of the current generation circuit 22 and the frequency / voltage conversion circuit 23 will be described. FIG. 6 is a circuit diagram showing a configuration example of the current generation circuit and the frequency voltage conversion circuit according to the first embodiment. In the current generation circuit 22, the chopping circuit 31 includes PMOS transistors MP5, MP6, MP7, and MP8. The PMOS transistor MP5 is connected between the PMOS transistor MP1 and the resistor R. The PMOS transistor MP6 is connected between the PMOS transistor MP1 and the frequency-voltage conversion circuit 23 (node N1 thereof). The PMOS transistor MP7 is connected between the PMOS transistor MP2 and the frequency / voltage conversion circuit 23 (node N1 thereof). The PMOS transistor MP8 is connected between the PMOS transistor MP2 and the resistor R. The chopping signal CHOP signal is commonly supplied to the gates of the PMOS transistors MP5 and MP7. On the other hand, the inverted signal of the chopping signal CHOP signal is supplied in common to the gates of the PMOS transistors MP6 and MP8. As a result, when the PMOS transistors MP5 and MP7 are turned on / off, the PMOS transistors MP6 and MP8 are turned off / on.

  Specifically, when the chopping signal CHOP signal is L, the PMOS transistors MP5 and MP7 are turned on, the PMOS transistors MP6 and MP8 are turned off, and the PMOS transistor MP1-MP5-resistance R current path (path on the input current side). ) And MP2-MP7-node N1 current paths (paths on the output current side), respectively. On the other hand, when the chopping signal CHOP signal is H, the PMOS transistors MP6 and MP8 are turned on, the PMOS transistors MP5 and MP7 are turned off, and the current path of the PMOS transistors MP1 to MP6-node N1 (the path on the output current side), In addition, current paths (paths on the input current side) of MP2-MP8-resistance R are formed. As a result, the current generated by the PMOS transistor MP1 and the current generated by the PMOS transistor MP2 can be alternately and periodically switched as the reference current Iref flowing through the resistor R. That is, as the reference current I1 supplied to the frequency voltage conversion circuit 23, the current generated by the PMOS transistor MP2 and the current generated by the PMOS transistor MP1 can be switched alternately and periodically. Thereby, the mismatch voltage ΔVth generated between the devices of the PMOS transistors MP1 and MP2 can be canceled in a circuit.

  In the frequency voltage conversion circuit 23, the switch SW1 includes a PMOS transistor MP12. The PMOS transistor MP12 has a source connected to the node N1, a drain connected to the node Nc, and a gate supplied with the charge signal ZCHR. The PMOS transistor MP12 has a function of charging the capacitor C with the reference current I1 in response to the charge signal ZCHR. The switch SW2 includes an NMOS transistor MN12. The NMOS transistor MN12 has a source connected to the ground, a drain connected to the node Nc, and a gate supplied with a discharge signal DISC. The NMOS transistor MN12 has a function of discharging the capacitor C in response to the discharge signal DISC. The switch SW3 includes an NMOS transistor MN12. The NMOS transistor MN13 has a source connected to the node Nc, a drain connected to the integrating circuit 24, and a gate supplied with the sampling signal SAMP. The NMOS transistor MN13 has a function of sampling the voltage of the node Nc (conversion output voltage Vfv).

  The node N1 is connected in parallel with another current path of the PMOS transistor MP11 and the NMOS transistor MN11 connected in series to the current path of the PMOS transistor MP12 and the NMOS transistor MN12 connected in series. The PMOS transistors MP11 and MP12 function as a current switch that operates with a charge signal ZCHR that is a charge signal and its inverted signal. The PMOS transistors MP11 and MP12 take the shape of a current switch in order to prevent the node N1 from changing due to the switching operation by the charge signal ZCHR. The NMOS transistor MN11 is a dummy corresponding to the NMOS transistor MN12, and pulls up the gate to VDD or applies a VDD level signal.

FIG. 7 is a plan view showing a layout example of the current mirror circuit 30 and the chopping circuit 31. The PMOS transistors MP1, MP2 of the current mirror circuit 30 and the PMOS transistors MP5, MP6, MP7, MP8 of the chopping circuit 31 are arranged in a common centroid type. That is, the plurality of PMOS transistors are arranged at positions that are symmetric (line symmetric, point symmetric) with respect to a specific reference point. In the example of this figure, at least for the virtual line C ₀ , the two current paths are arranged in line symmetry in any case of each of the two patterns selected by the chopping signal CHOP signal. . Thereby, the variation of the PMOS transistor can be canceled (cancelled). However, the two current paths of the first pattern are the PMOS transistors MP1-MP5 (-resistance R) and MP2-MP7 (-node N1). On the other hand, the current path of the second pattern is PMOS transistors MP1-MP6 (-node N1) and MP2-MP8 (-resistance R). Also, the current mirror circuit 30 and the chopping circuit 31 on the lower side of the drawing and the current mirror circuit 30 and the chopping circuit 31 (not shown) on the upper side of the drawing are between the current mirror circuits 30 on the virtual line C _0. They are arranged symmetrically with respect to a point (not shown). This arrangement is an example, and other layouts may be used as long as they are arranged in a common centroid type.

FIG. 8 is a circuit diagram illustrating a specific configuration example of the resistor R. The resistor R is a variable resistor, and the magnitude of the resistance value is controlled by a control signal. The resistor R is composed of a resistor ladder circuit. In the illustrated example, the resistor R has a plurality of resistors connected in series elements _{R 0, 2R 0, 4R 0} , 8R 0, 16R 0, 32R 0, 64R 0, 128R 0, 256R 0, connected in series The plurality of transistor elements M1, M2, M3, M4, M5, M6, M7, and M8 are provided. However, for example, “4R ₀ ” indicates that the resistance value is 4 × R ₀ together with the sign of the resistance element. Each of the plurality of resistance elements R ₀ ,..., 128 R ₀ is connected in parallel to a corresponding one of the plurality of transistor elements M ₁ ,. Specifically, the resistance elements R ₀ , 2R ₀ , 4R ₀ , 8R ₀ , 16R ₀ , 32R ₀ , 64R ₀ , and 128R ₀ are the corresponding transistor elements M1, M2, M3, M4, M5, M6, M7, M8 is connected in parallel. An 8-bit control signal is input to the gate of a corresponding one of the plurality of transistor elements M1,..., M8 for each bit. When the bit signal input to the gate is H, the transistor element is turned on, so that the corresponding resistance element is passed. Conversely, when the bit signal input to the gate is L, the transistor element is turned off, so that the corresponding resistance element becomes a current path. In this way, the resistance value can be freely adjusted by the control signal.

FIG. 9 is a plan view showing a specific layout example of the resistors R in FIG. The resistor R is configured by connecting in series resistance elements composed of unit resistors 57. The unit resistors 57 are arranged uniformly in the local area (region 55), thereby improving the pair accuracy between the resistors. In the resistance element 256R _0, unit resistor 57 is connected to the 32 series. In the resistance element 128R _0, unit resistor 57 is connected to the 16 series. In the resistance element 64R _0, unit resistor 57 is connected to the eight series. In the resistance element 32R _0, unit resistor 57 is connected to the four series. In the resistance element 16R _0, unit resistor 57 is connected to two series. In the resistance element 8R _0, unit resistor 57 is connected to the 32 series. In the resistance element 4R _0, unit resistor 57 is connected to two parallel. In resistive element 2R _0, unit resistor 57 is connected to four parallel. In the resistance element R ₀ , eight unit resistors 57 are connected in parallel. The transistor elements M1,..., M8 are provided in the region 56 (not individually indicated). Each transistor element and each resistance element are connected by a wiring 58. The absolute value of the frequency of the oscillation circuit 25 is made variable by switching the resistor R and changing the reference current supplied to the frequency voltage conversion circuit 23.

  FIG. 10 is a circuit diagram illustrating a specific configuration example of the control circuit. The control circuit 26 includes flip-flop circuits FF1 to FF5, inverter circuits IV1 to IV2, IV11 to IV15, IV21 to IV24, and NAND circuits NAND1 to NAND3. In FF1, the clock signal CKOUT is input to the clock terminal via IV1, and the output signal of FF2 is input to the input terminal. In the FF2, the clock signal CKOUT is input to the clock terminal, and the output signal of the FF3 is input to the input terminal. In the FF3, the clock signal CKOUT is input to the clock terminal via IV1, and the output signal of the FF4 is input to the input terminal. In FF4, the clock signal CKOUT is input to the clock terminal, and the output signal of FF1 is input to the input terminal via IV2. NAND1 receives the output signal of FF1 via IV11 at one input terminal, and the output signal of FF3 via IV14 at the other input terminal, and discharges the NAND operation result of both output signals via IV21. (Fourth control signal) Output as DISC. NAND2 receives the output signal of FF2 through IV12 and 13 at one input terminal, the output signal of FF4 through IV15 and 16 at the other input terminal, and both output signals through IV22 and 23, respectively. The NAND operation result is output as a charge signal (second control signal) ZCHR. NAND3 receives the output signal of FF2 via IV12, 13, 17, 18 at one input terminal, the output signal of FF3 via IV14 to the other input terminal, and both output signals via IV24. The NAND operation result is output as a sampling signal (third control signal) SAMP. The FF 5 receives the output signal of the NAND 3 at the clock terminal and the output signal (CHOP) of its own at the input terminal, and outputs a chopping signal (first control signal) CHOP.

  The operation of the control circuit will be described. FIG. 11 is a timing chart showing an operation example of the control circuit. (A) is a clock signal CKOUT, (b) is a charge signal (second control signal) ZCHR, (c) is a sampling signal (third control signal) SAMP, (d) is a discharge signal (fourth control signal) DISC, (E) shows a chopping signal (first control signal) CHOP.

  The charge signal ZCHR signal is used to charge the capacitor C with the reference current I1 when the frequency / voltage conversion circuit 23 converts the period of the clock signal CKOUT, that is, the frequency (1 / T) into a voltage. Accordingly, the L period (eg, t1 to t2) of the charge signal ZCHR signal is one cycle of the clock signal CKOUT. The sampling signal SAMP is used in the frequency voltage conversion circuit 23 to sample the converted output voltage Vfv after charging the capacitor C with the reference current I1. Therefore, the H period (example: t3 to t4) of the sampling signal SAMP is a period after the charge of the capacitor C (example: t1 to t2). The chopping signal CHOP is used in the current generation circuit 22 to control the chopping operation. Therefore, it is necessary to execute the chopping operation without affecting the frequency voltage conversion operation of the frequency voltage conversion circuit 23. Therefore, after the conversion output voltage Vfv is transferred to the integration circuit 24, that is, after the sampling operation (example: t3 to t4), switching (chopping) is performed (example: t4). When the control circuit 26 of FIG. 10 is used, the halving output of the negative edge of the sampling signal SAMP is used as the chopping signal CHOP. The negative edge of the sampling signal SAMP means the completion of the sampling operation. The discharge signal DISC is used in the frequency voltage conversion circuit 23 to discharge the capacitor C in preparation for the next frequency voltage conversion operation. Accordingly, the H period (example: t5 to t6) of the discharge signal DISC is a period after the sampling operation (example: t3 to t4).

  Next, the operation of the on-chip oscillator 11 as the oscillation device according to the present embodiment will be described. FIG. 12A is a timing chart illustrating an operation example of the oscillation device according to the first embodiment. The on-chip oscillator 11 operates using a control signal from the control circuit 26. Here, (a) is a clock signal CKOUT, (b) is a charge signal (second control signal) ZCHR, (c) is a sampling signal (third control signal) SAMP, and (d) is a discharge signal (fourth control signal). ) DISC, (e) shows the converted output voltage (voltage of the node Nc) Vfv, (f) shows the control voltage VCNT, and (g) shows the chopping signal (first control signal) CHOP. FIG. 12A shows a case where the clock signal CKOUT has a desired frequency.

  When the chopping signal CHOP signal is H (t10), the PMOS transistors MP6 and MP8 of the current generation circuit 22 are turned on, the PMOS transistors MP5 and MP7 are turned off, and the current path of the PMOS transistors MP1 to MP6 to the node N1, and A current path of MP2-MP8-resistance R is formed. As a result, the reference current Iref flows in the current path of the PMOS transistors MP2-MP8-resistor R, and the reference current I1 equal to the reference current Iref flows in the current path of the PMOS transistors MP1-MP6-node N1. 23.

  When the charge signal ZCHR becomes L (t10), the switch SW1 (MP12) of the frequency voltage conversion circuit 23 is turned on. At this time, the sampling signal SAMP and the discharge signal DISC are L, and the switch SW3 (MN13) and the switch SW2 (MN12) of the frequency voltage conversion circuit 23 are off. Thereby, the current I1 (= Iref) generated by the current generation circuit 22 is supplied to the capacitor C of the frequency voltage conversion circuit 23 via the node N1 and the switch SW1 (MP12). That is, the capacitor C is charged with the current I1 (= Iref). As a result, the voltage at the node Nc, that is, the converted output voltage Vfv increases.

When the charge signal ZCHR becomes H (t11), the switch SW2 (MP12) is turned off. As a result, the supply of the current I1 (= Iref) is stopped. That is, charging of the capacitor C is stopped. That is, the current generation circuit 22 charges the capacitor I with the current Iref during the period when the charge signal ZCHR is L (t11 to t12). At this time, the frequency (1 / Tout) is converted into a voltage by making the L period (t11 to t12) of the charge signal ZCHR equal to the oscillation period Tout of the oscillation circuit 25 (= one period of the clock signal CKOUT). be able to. The converted output voltage Vfv can be expressed by Equation (5).

  When the sampling signal SAMP becomes H (t12), the switch SW3 (MN13) is turned on. As a result, the converted output voltage Vfv is transferred to the integrating circuit 24. When the converted output voltage Vfv is the reference voltage VREFC, the control voltage VCNT output from the integrating circuit 24 is a predetermined constant value and does not change. That is, the clock signal CKOUT has a desired frequency. As a result, the oscillation circuit 25 continues to output the clock signal CKOUT.

  The frequency voltage conversion operation of the frequency voltage conversion circuit 23 ends, and after the sampling operation ends, the chopping signal CHOP becomes L (t13). As a result, in the current generation circuit 22, the PMOS transistors MP5 and MP7 are turned on, the PMOS transistors MP6 and MP8 are turned off, the current path of the PMOS transistors MP1 to MP5 and the resistor R, and the current of MP2 to MP7 and the node N1. Each pass is formed. That is, the current path is switched. As a result, the reference current Iref flows in the current path of the PMOS transistors MP1-MP5-resistor R, and the reference current I1 equal to the reference current Iref flows in the current path of the PMOS transistors MP2-MP7-node N1 to the frequency voltage conversion circuit 23. Supplied.

  After the conversion output voltage Vfv is transferred and held (after the sampling signal SAMP is switched from H to L), the discharge signal DISC becomes H at a timing that does not cause a problem in the operation of the frequency voltage conversion circuit 23 (t14). The switch SW2 (MN12) is turned on. Thereby, the electric charge charged in the capacitor C is discharged to the ground via the switch SW2 (MN12). As a result, the converted output voltage Vfv becomes 0V which is the initial state (t15). Hereinafter, similarly, t16, t17, t18, t19, t20, t21,.

  FIG. 12B is a timing chart illustrating another operation example of the oscillation device according to the first embodiment. (A) and (g) are the same as FIG. 12A. FIG. 12B shows a case where the clock signal CKOUT deviates from a desired frequency. However, time t30 to t35 is a case where the cycle is long (frequency is low), and time t36 to t41 is a case where the cycle is short (frequency is high).

First, a case where the period from time t30 to t35 is long (frequency is low) will be described.
When the chopping signal CHOP signal is H (t30), in the current generation circuit 22, the reference current Iref flows in the current path of the PMOS transistors MP2-MP8-resistor R, and the reference current flows in the current path of the PMOS transistors MP1-MP6-node N1. I1 (= Iref) flows and is supplied to the frequency voltage conversion circuit 23.

  When the charge signal ZCHR becomes L (t30), the switch SW1 (MP12) is turned on. As a result, the current I1 (= Iref) generated by the current generation circuit 22 is supplied to the capacitor C of the frequency voltage conversion circuit 23 via the node N1 and the switch SW1 (MP12), and the capacitor C becomes the current I1 (= Iref). It is charged with. As a result, the voltage at the node Nc, that is, the converted output voltage Vfv increases.

  When the charge signal ZCHR becomes H (t31), the switch SW2 (MP12) is turned off. As a result, the supply of the current I1 (= Iref) is stopped. That is, charging of the capacitor C is stopped. Here, the converted output voltage Vfv (= Iref · Tout / C) is converted to a voltage higher than the reference voltage VREFC because the cycle Tout of the clock signal CKOUT is longer than a desired value.

  When the sampling signal SAMP becomes H (t32), the switch SW3 (MN13) is turned on. As a result, the converted output voltage Vfv is transferred to the integrating circuit 24. When the converted output voltage Vfv is larger than the reference voltage VREFC, the control voltage VCNT output from the integrating circuit 24 is smaller than a predetermined constant value. That is, the clock signal CKOUT is lower than the desired frequency. As a result, the oscillation circuit 25 changes the clock signal CKOUT to shorten the cycle (increase the frequency).

  The frequency voltage conversion operation of the frequency voltage conversion circuit 23 is finished, and after the sampling operation is finished, the chopping signal CHOP becomes L (t33). As a result, the current generation circuit 22 switches the current path, the reference current Iref flows in the current path of the PMOS transistors MP1-MP5-resistance R, and the reference current I1 (== in the current path of the PMOS transistor MP2-MP7-node N1. Iref) flows and is supplied to the frequency voltage conversion circuit 23.

  The discharge operation (t34-t35) after the converted output voltage Vfv is transferred and held (after the sampling signal SAMP switches from H to L) is the same as in the case of FIG. 12A (t14-t15).

In the on-chip oscillator 11, when the operating temperature varies, a mismatch voltage ΔVth may occur. For example, consider a case where the threshold voltage of the PMOS transistor MP1 on the reference current I1 side is slightly lower than the threshold voltage of the PMOS transistor MP2 on the reference current Iref side in the same period as the times t30 to t35 (t10 to t15). . In that case, normally, the reference current I1 is slightly larger than the reference current Iref (I1 = Iref + I _missmatch ). As a result, even the period Tout of the clock signal CKOUT has a desired value, the conversion output voltage _{Vfv (= (Iref + I mismatch} ) · Tout / C) is greater than the desired value (= Iref · Tout / C) The voltage is converted to a voltage higher than the reference voltage VREFC. This situation is similar to the situation at time t31 described above.
In this case, since a value that substantially cancels the influence of the mismatch voltage ΔVth is preset in the resistor R, the value of I _missmatch is extremely small. Therefore, it is possible to output the reference current I1 that is extremely less affected by the mismatch voltage ΔVth. That is, the converted output voltage Vfv is a voltage higher than a desired value, but the difference between the two can be suppressed to a very small value. The operation when the converted output voltage Vfv becomes a voltage larger than a desired value is the same as the operation after t32.

Next, the case where the period from time t36 to t41 is short (frequency is high) will be described.
When the chopping signal CHOP is L (t36), in the current generation circuit 22, the reference current Iref flows through the current path of the PMOS transistors MP1-MP5-resistance R, and the reference current I1 flows through the current path of the PMOS transistor MP2-MP7-node N1. (= Iref) flows and is supplied to the frequency voltage conversion circuit 23.

  When the charge signal ZCHR becomes L (t36), the switch SW1 (MP12) is turned on. As a result, the current I1 (= Iref) generated by the current generation circuit 22 is supplied to the capacitor C of the frequency voltage conversion circuit 23 via the node N1 and the switch SW1 (MP12), and the capacitor C becomes the current I1 (= Iref). It is charged with. As a result, the voltage at the node Nc, that is, the converted output voltage Vfv increases.

  When the charge signal ZCHR becomes H (t37), the switch SW2 (MP12) is turned off. As a result, the supply of the current I1 (= Iref) is stopped. That is, charging of the capacitor C is stopped. Here, the converted output voltage Vfv (= Iref · Tout / C) is converted to a voltage smaller than the reference voltage VREFC because the cycle Tout of the clock signal CKOUT is shorter than a desired value.

  When the sampling signal SAMP becomes H (t38), the switch SW3 (MN13) is turned on. As a result, the converted output voltage Vfv is transferred to the integrating circuit 24. When the converted output voltage Vfv is smaller than the reference voltage VREFC, the control voltage VCNT output from the integrating circuit 24 is larger than a predetermined constant value. That is, the clock signal CKOUT is higher than the desired frequency. As a result, the oscillation circuit 25 changes the clock signal CKOUT to lengthen the period (lower the frequency).

  The frequency voltage conversion operation of the frequency voltage conversion circuit 23 is finished, and after the sampling operation is finished, the chopping signal CHOP becomes H (t39). As a result, the current generation circuit 22 switches the current path, the reference current Iref flows in the current path of the PMOS transistors vMP2-MP8-resistance R, and the reference current I1 (== in the current path of the PMOS transistors MP1-MP6-node N1. Iref) is supplied to the frequency-voltage conversion circuit 23.

  The discharge operation (t40-t41) after the converted output voltage Vfv is transferred and held (after the sampling signal SAMP is switched from H to L) is the same as the discharge operation (t34-t35).

In the on-chip oscillator 11, when the operating temperature varies, a mismatch voltage ΔVth may occur. For example, consider a case where the threshold voltage of the PMOS transistor MP2 on the reference current I1 side is slightly higher than the threshold voltage of the PMOS transistor MP1 on the reference current Iref side in the same cycle as the times t36 to t41 (t16 to t21). . In that case, normally, the reference current I1 is slightly smaller than the reference current Iref (I1 = Iref−I _missmatch ). As a result, even the period Tout of the clock signal CKOUT has a desired value, the conversion output voltage _{Vfv (= (Iref-I mismatch} ) · Tout / C) , from the desired value (= Iref · Tout / C) Is also converted to a smaller voltage, that is, a voltage smaller than the reference voltage VREFC. This situation is the same as the situation at time t37 described above.
In this case, since a value that substantially cancels the influence of the mismatch voltage ΔVth is preset in the resistor R, the value of I _missmatch is extremely small. Therefore, it is possible to output the reference current I1 that is extremely less affected by the mismatch voltage ΔVth. That is, the converted output voltage Vfv is a voltage smaller than a desired value, but the difference between the two can be suppressed extremely small. The operation when the converted output voltage Vfv becomes a voltage smaller than a desired value is the same as the operation after t37.

  As described above, when the converted output voltage Vfv transferred by sampling is larger than the reference voltage VREFC (FIG. 12B: t31 to t32), the control voltage VCNT decreases (t32 to t34), and the oscillation circuit 25 has a higher oscillation frequency. Controlled. On the other hand, when the converted output voltage Vfv is smaller than the reference voltage VREFC (FIG. 12B: t37 to t38), the control voltage VCNT increases (t38 to t40), and the oscillation circuit 25 is controlled so that the oscillation frequency is lowered. When the operation shown in FIG. 12B is repeated and the converted output voltage Vfv becomes equal to the reference voltage VREFC as shown in FIG. 12A, the on-chip oscillator 11 stably oscillates at the target frequency.

  As described above, the on-chip oscillator 11 according to the present embodiment operates.

  As described above, the on-chip oscillator 11 as the oscillation device of the present embodiment has the chopping circuit 31 connected to the current mirror circuit 30 of the current generation circuit 22. The input-side current path (power supply voltage VDD to resistor R) and the output-side current path (power supply voltage VDD to node N1) respond to the chopping signal CHOP signal at a timing that does not affect the generation of the clock signal. Are switched alternately. That is, the connection destinations of the drains of the PMOS transistors MP1 and MP2 of the current mirror circuit 30 are periodically switched alternately. As a result, the mismatch (offset) voltage ΔVth in the threshold voltage Vth of the two PMOS transistors MP1 and MP2 can be canceled by canceling in a circuit manner. As a result, the influence of the temperature drift of the mismatch (offset) voltage ΔVth can be eliminated, and the temperature dependence of the reference current I1 can be reduced. Thereby, the output of the frequency voltage conversion circuit 23 can be stabilized, and the accuracy of the clock signal can be further improved.

  The on-chip oscillator 11 itself generates the chopping signal CHOP indicating the switching timing of the chopping circuit 31 inside (the control circuit 26). That is, it is generated from the sampling signal SAMP based on the clock signal using a simple circuit. Therefore, it is not necessary to provide a circuit for generating the chopping signal CHOP outside, and an external circuit is unnecessary.

  Further, the adoption of the chopping circuit 31 not only improves the frequency accuracy, but also makes it possible to reduce the device sizes of the PMOS transistors MP1 and MP2 of the current mirror circuit 30 of the current generation circuit 22. As a result, it is possible to reduce the chip area and shorten the startup time of the on-chip oscillator.

  Ordinary oscillators perform continuous system control. For this reason, when a chopping circuit is used in a normal oscillator, it is considered that, for example, a change in the gate voltage of the transistor and a change in the output current accompanying the change occur. Then, the fluctuations propagate and the control voltage fluctuates periodically, and jitter (deterministic jitter) is expected to occur in the generated clock signal. That is, the jitter characteristics of the clock signal are expected to deteriorate. As a result, the frequency accuracy of the clock signal is degraded. Therefore, no chopping circuit is provided in the oscillator.

  However, the on-chip oscillator 11 according to the present embodiment can improve the accuracy of the frequency of the clock signal by applying the chopping circuit 31 in the current generation circuit 22. The reason is that the on-chip oscillator 11 is a circuit that performs discrete system control. Specifically, it is as follows. In the on-chip oscillator 11 of the present embodiment, as shown in FIGS. 4 and 5, the output voltage (Vfv) of the frequency voltage conversion circuit 23 is sampled (VSAMP) before the integration circuit 24. If sampling is performed in this manner, the operation of the current generation circuit 22 is separated from the operation and characteristics of the oscillation circuit 25 during the period from the sampling operation to the next frequency-voltage conversion operation. Therefore, even if the chopping circuit operates during that period and the gate voltage fluctuation or the output current fluctuation caused by the chopping operation occurs, the fluctuation is not transmitted to the oscillation circuit 25 and the clock characteristics are not affected. Therefore, the chopping circuit 31 can be applied to the current generation circuit 22 of the on-chip oscillator 11 of the present embodiment. As a result, the offset voltage ΔVth generated in the PMOS transistors MP1 and MP2 can be canceled by the effect of the chopping circuit 31, and the frequency accuracy can be improved.

  The semiconductor device 1 is not limited to the example of FIG. FIG. 13 is a block diagram illustrating another configuration example of the semiconductor device to which the oscillation device according to the first embodiment is applied. The semiconductor device 1 is exemplified by a microcomputer, and includes a CPU 5, a peripheral function block 6, an RTC (Real Time Clock) 7, a flash memory 4, a register 3, and a CPG 2. The peripheral function block 6 includes a RAM 15, a BUS 16, and an ADC 17. In this example, the CPG 2 includes an on-chip oscillator 11, a PLL (Phase-Locked Lod) 44, an oscillator (OSC) 45, and a 32 KHz oscillator (32 KHz OSC) 46, and is used for the operation of the semiconductor device 1 (example: microcomputer). Generate clocks with multiple required frequencies. A main clock such as a system clock and a bus clock of several tens of MHz necessary for microcomputer operation is generated by combining a crystal oscillator of several MHz to several tens of MHz (arranged outside the semiconductor device 1), the oscillators 45 and 46, and the PLL 44. be able to. The 32.768 KHz crystal oscillator and the 32 KHz oscillator 46 can generate a 32.768 KHz clock for RTC. The on-chip oscillator 11 can generate a clock of several tens of MHz necessary for the operation of the semiconductor device 1 with the on-chip oscillator alone. In the operation mode using the oscillators 45 and 46 and the PLL 44, the on-chip oscillator 11 can be used to supply a clock having an arbitrary frequency different from the operation frequency of the semiconductor device 1 to the application. Further, in an operation mode in which the oscillators 45 and 46 and the PLL 44 are not used, it can be used as a main clock such as a system clock and a bus clock instead of the PLL output. Also in this case, the same effect as that of the semiconductor device 1 of FIG. 2 can be obtained.

(Second Embodiment)
An oscillation device according to a second embodiment and a semiconductor device using the oscillation device will be described. In the present embodiment, the configuration of the current generator is different from that of the first embodiment. In the following, differences will be mainly described.

A configuration example of a current generation circuit according to this embodiment will be described. FIG. 14 is a block diagram illustrating a configuration example of a current generation circuit according to the second embodiment. In the current generation circuit 22, a cascode circuit 32 is added as a circuit that reduces the voltage dependence of the generated reference current. The cascode circuit 32 is provided between the chopping circuit 31, the node VF (resistor R), and the frequency / voltage conversion circuit 23. The cascode circuit 32 includes a PMOS transistor MP3 provided between one output terminal of the chopping circuit 31 and the node VF, and a PMOS transistor MP4 provided between the other output terminal of the chopping circuit 31 and the node N1. It has. A common bias voltage V _Bias is supplied to the gates of the PMOS transistors MP3 and MP4. Does not depend on the power supply voltage VDD _{V Bias} and Vgs_mp3 (of PMOS transistor MP3 gate - between the source voltage) and Vgs_mp4 (gate of the PMOS transistor MP4 - source voltage) by the source of the PMOS transistor MP1, MP2 of the current mirror circuit 30 - A drain-to-drain voltage Vds is determined. Therefore, it is possible to reduce the dependency of the reference current I1 (= Iref) on the power supply voltage VDD.

Next, specific configuration examples of the current generation circuit 22 and the frequency / voltage conversion circuit 23 will be described. FIG. 15 is a circuit diagram showing a configuration example of a current generation circuit and a frequency-voltage conversion circuit according to the second embodiment. The current generation circuit 22 is a circuit obtained by adding a cascode circuit 32 shown in FIG. 14 to the current generation circuit of FIG. The PMOS transistor MP3 of the cascode circuit 32 is provided between the PMOS transistors MP5 and MP8 of the chopping circuit 31 and the node VF. The PMOS transistor MP4 of the cascode circuit 32 is provided between the PMOS transistors MP7 and MP6 of the chopping circuit 31 and the node N1. A common bias voltage V _Bias is supplied to the gates of the PMOS transistors MP3 and MP4.

  In this case, the same effect as that of the first embodiment can be obtained. Furthermore, since the cascode circuit 32 is provided in the current generation circuit 22, the power supply voltage dependency of the reference current Iref (= I1) can be reduced. Thereby, the magnitude of the reference current I1 (= Iref) is stabilized, so that the accuracy of the generated clock signal CKOUT can be further improved.

(Third embodiment)
An oscillation device according to a third embodiment and a semiconductor device using the oscillation device will be described. The present embodiment is different from the first embodiment in that the reference voltage generation circuit 21 is further provided and the configuration of the current generation circuit 22 is changed accordingly. . In the following, differences will be mainly described.

  FIG. 16 is a block diagram illustrating a configuration example of the oscillation device according to the third embodiment. In the present embodiment, the on-chip oscillator 11 as the oscillation device further includes a reference voltage generation circuit 21 as compared with the case of FIG. The reference voltage generation circuit 21 generates a reference voltage VREFC having no temperature dependence and a reference voltage VREFI having a predetermined temperature dependence. The reference voltage VREFC is supplied to the integration circuit 24. The reference voltage VREFI is supplied to the current generation circuit 22. The resistor R of the current generation circuit 22 has a temperature dependency opposite to the temperature dependency of the second reference voltage VREFI. Therefore, the current generation circuit 22 can generate the reference current Iref (= I1) having no temperature dependency based on the reference voltage VREFI and the resistor R. Thereby, a clock signal with improved accuracy can be generated. The reference voltage generation circuit 21 and the current generation circuit 22 can also be regarded as the current output circuit 20.

  Next, configuration examples of the reference voltage generation circuit 21, the current generation circuit 22, the frequency voltage conversion circuit 23, and the integration circuit 24 will be described. FIG. 17 is a block diagram illustrating a configuration example of a reference voltage generation circuit, a current generation circuit, a frequency voltage conversion circuit, and an integration circuit according to the third embodiment.

  The reference voltage generation circuit 21 includes resistors R1, R2, R3, and R4, a bipolar transistor Q1, and a band gap reference circuit 41. The band gap reference circuit 41 generates a PTAT (Proportional To Absolute Temperature) current Iptat. The generated PTAT current Iptat is supplied to a resistance ladder circuit (resistance R1). The PTAT current Iptat that has passed through the resistor ladder circuit (resistor R1) is a first path (current I01) composed of the bipolar transistor Q1 and resistor R2, and a second path (current I02) of the resistor ladder circuit (resistors R3 and R4). It is divided into. At this time, the reference voltage VREFI and the reference voltage VREFC generated from the reference voltage generation circuit 21 can be expressed by the following equations.

ただし、Ｖｂｅは、バイポーラトランジスタＱ１のベース−エミッタ間電圧である。 First, the voltage VFLAT at the connection node between the resistance ladder circuit (resistor R1) and the first path / second path is expressed by the following equation (6).

Vbe is the base-emitter voltage of the bipolar transistor Q1.

Therefore, the reference voltage VREFC is expressed by the following equation (7).

The reference voltage VREFI is expressed by the following formula (8).

  By adjusting the resistance value so that the temperature dependence of Vbe of the bipolar transistor Q1 and the temperature dependence of the product of the PTAT current Iptat and the resistance R2 are offset, a voltage VFLAT having no temperature dependence can be realized. The reference voltage VREFC can be realized by resistance-dividing VFLAT having no temperature dependence as shown in Expression (7). Therefore, the reference voltage VREFC is a flat voltage with respect to the temperature having no temperature dependency.

  On the other hand, the reference voltage VREFI is the product of the resistor R1 and the PTAT current Iptat as shown in the equation (8), so that the temperature characteristic of the resistor R used in the current generation circuit 22 in the figure is canceled. The temperature characteristic is trimmed. Trimming is realized by switching the location where the voltage (VREFI) from the resistance ladder circuit of the resistor R1 is taken out by the control signal A. The configuration of the resistor R1 can also be realized, for example, with a configuration similar to the configuration of FIGS. The generated reference voltage VREFC and reference voltage VREFI are output to the integration circuit 24 and the current generation circuit 22, respectively.

  The current generation circuit 22 further includes a differential amplifier AMP1 as compared with the case of FIG. In the differential amplifier AMP1, the reference voltage VREFI is supplied to the inverting input terminal, the voltage of the node VF is supplied to the non-inverting input terminal, and the output is supplied to the gates of the PMOS transistors MP1 and MP2 of the current mirror circuit 30. That is, by using the reference voltage VREFI and the node VF as inputs of the differential amplifier AMP1, feedback control is performed so that the node VF has the same potential as the reference voltage VREFI. Therefore, the current generation circuit 22 can generate the reference current Iref (= VREFI / R) obtained by dividing the reference voltage VREFI by the resistance R. The reference current Iref is current mirrored by the PMOS transistors MP1 and MP2. Then, it is output to the node N1 as the reference current I1 (= Iref). Since the reference voltage VREFI having a temperature characteristic opposite to the temperature dependence of the resistor R is generated by the reference voltage generation circuit 21, the reference current Iref generated by the current generation circuit 22 has no temperature dependence. When the two-point temperature trimming is performed, a current Iref having no primary temperature dependency can be generated. When trimming is performed at three or more temperatures, it is possible to cancel the secondary temperature dependency in addition to the primary. However, in this embodiment, since the chopping circuit 31 is used, the temperature trimming is performed while the chopping circuit 31 is operated and the current path of the reference current Iref is switched. The resistance R is as described in FIGS. 8 and 9, and in this case, the resistance value is changed by the control signal B.

  Next, specific configuration examples of the current generation circuit 22 and the frequency / voltage conversion circuit 23 will be described. FIG. 18 is a circuit diagram showing a configuration example of a current generation circuit and a frequency voltage conversion circuit according to the third embodiment. The current generation circuit 22 further includes a differential amplifier AMP1 as compared with the case of FIG. The differential amplifier AMP1 is as described in FIG.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained. In addition, the reference current Iref (= I1) generated by the current generation circuit 22 is generated because the temperature dependency is taken by temperature trimming (offset of the temperature characteristic of the resistor R by the reference voltage VREFI). The accuracy of the clock signal CKOUT can be further improved.

(Fourth embodiment)
An oscillation device according to a fourth embodiment and a semiconductor device using the oscillation device will be described. In the present embodiment, the configuration of the current generator is different from that of the third embodiment. In the following, differences will be mainly described.

A configuration example of a current generation circuit according to this embodiment will be described. FIG. 19 is a block diagram illustrating a configuration example of a current generation circuit according to the fourth embodiment. In the current generation circuit 22, a cascode circuit 32 is added as a circuit that reduces the voltage dependence of the generated reference current. The cascode circuit 32 is provided between the chopping circuit 31, the node VF (resistor R), and the frequency / voltage conversion circuit 23. The cascode circuit 32 includes a PMOS transistor MP3 provided between one output terminal of the chopping circuit 31 and the node VF, and a PMOS transistor MP4 provided between the other output terminal of the chopping circuit 31 and the node N1. It has. A common bias voltage V _Bias is supplied to the gates of the PMOS transistors MP3 and MP4. Does not depend on the power supply voltage VDD _{V Bias} and Vgs_mp3 (of PMOS transistor MP3 gate - between the source voltage) and Vgs_mp4 (gate of the PMOS transistor MP4 - source voltage) by the source of the PMOS transistor MP1, MP2 of the current mirror circuit 30 - A drain-to-drain voltage Vds is determined. Therefore, it is possible to reduce the dependency of the reference current I1 (= Iref) on the power supply voltage VDD.

Next, specific configuration examples of the current generation circuit 22 and the frequency / voltage conversion circuit 23 will be described. FIG. 20 is a circuit diagram illustrating a configuration example of a current generation circuit and a frequency-voltage conversion circuit according to the fourth embodiment. The current generation circuit 22 is a circuit obtained by adding a cascode circuit 32 shown in FIG. 19 to the current generation circuit of FIG. The PMOS transistor MP3 of the cascode circuit 32 is provided between the PMOS transistors MP5 and MP8 of the chopping circuit 31 and the node VF. The PMOS transistor MP4 of the cascode circuit 32 is provided between the PMOS transistors MP7 and MP6 of the chopping circuit 31 and the node N1. A common bias voltage V _Bias is supplied to the gates of the PMOS transistors MP3 and MP4.

  In this case, the same effect as that of the third embodiment can be obtained. Furthermore, since the cascode circuit 32 is provided in the current generation circuit 22, the power supply voltage dependency of the reference current Iref (= I1) can be reduced. Thereby, the magnitude of the reference current I1 (= Iref) is stabilized, so that the accuracy of the generated clock signal CKOUT can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 Semiconductor Device 2 CPG (Clock Pulse Generator)
3 Register 4 Flash memory 5 CPU (Central Processing Unit)
6 Peripheral function block 7 RTC (Real Time Clock)
11 On-Chip Oscillator (On-Chip Oscillator)
12 Divider A
13 Divider B
15 RAM (Random Access Memory 15)
16 BUS
17 ADC (Analog Digital Converter)
18 Timer
DESCRIPTION OF SYMBOLS 20 Current output circuit 21 Reference voltage generation circuit 22 Current generation circuit 23 Frequency voltage conversion circuit 24 Integration circuit 25 Oscillation circuit 26 Control circuit 30 Current mirror circuit 31 Chopping circuit 32 Cascode circuit 41 Band gap reference circuit 44 PLL (Phase-Locked Loop)
45 Oscillator (OSC)
46 32KHz oscillator (32KHz OSC)
55 area 56 area 57 unit resistance 58 wiring

Claims (13)

An oscillation circuit that generates a clock signal based on the control voltage;
A control circuit for generating a first control signal and a second control signal synchronized with the clock signal based on the clock signal;
A current generating circuit including a resistor and generating a reference current based on the resistor;
A frequency voltage conversion circuit that converts the frequency of the second control signal into a voltage using the reference current, samples the voltage, and generates a sampling voltage;
An integration circuit for generating the control voltage based on the sampling voltage and the first reference voltage;
The current generation circuit includes:
A current mirror circuit including a first transistor and a second transistor, the gates of which are connected in common, and generating the reference current;
In response to the first control signal, a chopping circuit that alternately switches and connects one of the first transistor and the second transistor to the resistor and the other to the frequency voltage conversion circuit. . The oscillation device according to claim 1,
The chopping circuit switches the connection between the first transistor and the second transistor, the resistor, and the frequency voltage conversion circuit during a period when the sampling is not performed. The oscillation device according to claim 1,
A reference voltage generation circuit for generating the first reference voltage not having temperature dependence and the second reference voltage having predetermined temperature dependence;
The current generation circuit includes:
The resistor has a temperature dependency opposite to the temperature dependency of the second reference voltage;
A voltage control unit for controlling a node on the current mirror circuit side of the resistor to the second reference voltage;
An oscillation device that generates the reference voltage based on the second reference voltage and the resistor. The oscillation device according to claim 1,
The chopping circuit is
A third transistor connected to the first transistor and the resistor;
A fourth transistor connected to the first transistor and the frequency-voltage conversion circuit;
A fifth transistor connected to the second transistor and the frequency-voltage conversion circuit;
A sixth transistor connected to the second transistor and the resistor;
The third transistor and the fifth transistor are turned off when the fourth transistor and the sixth transistor are turned on, and turned on when turned off. The oscillation device according to claim 4,
The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have a common centroid so that two current paths of the current mirror circuit are axisymmetric. Oscillator arranged in a mold. The oscillation device according to claim 1,
The current generation circuit includes:
An oscillation device further comprising a cascode circuit provided between the chopping circuit, the resistor, and the frequency-voltage conversion circuit. The oscillation device according to claim 6,
The cascode circuit is
A seventh transistor provided between the chopping circuit and a node of the resistor on the current mirror circuit side;
An eighth transistor provided between the chopping circuit and the frequency-voltage conversion circuit,
The seventh transistor and the eighth transistor have gates connected in common and are supplied with a bias voltage. The oscillation device according to claim 1,
The resistance is
A plurality of resistance elements connected in series;
A plurality of transistor elements connected in series, and
Each of the plurality of transistor elements is connected in parallel to a corresponding one of the plurality of resistance elements,
The value of the resistor can be changed by a signal supplied to gates of the plurality of transistor elements. The oscillation device according to claim 8, wherein
The resistance is
A transistor region in which the plurality of transistor elements are disposed;
A resistance region in which the plurality of resistance elements are arranged, and
Each of the plurality of resistance elements includes a part of a plurality of identical strip-shaped resistors arranged in a matrix in the resistance region. An oscillation device according to claim 1, which outputs a clock signal;
A semiconductor device comprising: a circuit (CPU, RAM,...) That performs arithmetic processing based on the clock signal. An operating method of the oscillation device,
Here, the oscillation device includes an oscillation circuit, a control circuit, a current generation circuit including a resistor, a frequency voltage conversion circuit, and an integration circuit.
The current circuit includes a current mirror circuit including a first transistor and a second transistor, the gates of which are commonly connected, and a chopping circuit.
The operation method of the oscillation device is:
The oscillation circuit generates a clock signal based on a control voltage;
The control circuit generating, based on the clock signal, a first control signal and a second control signal synchronized with the clock signal;
The current generating circuit generates a reference current based on a resistance;
The frequency voltage conversion circuit converts the frequency of the second control signal into a voltage using the reference current, samples the voltage, and generates the sampling voltage;
The integrating circuit comprises the step of generating the control voltage based on the sampling voltage and a first reference voltage;
The step of generating the reference current by the current generation circuit includes:
In response to the first control signal, the chopping circuit switches and connects one of the first transistor and the second transistor to the resistance side and the other to the frequency voltage conversion circuit;
The current mirror circuit includes the step of generating the reference current flowing from the other to the frequency voltage conversion circuit based on an input reference current flowing from the one to the resistor. The operation method of the oscillation device according to claim 11,
The step of switching and connecting the chopping circuit includes:
The chopping circuit includes a step of switching connection between the first transistor and the second transistor, the resistor, and the frequency voltage conversion circuit during a period when the sampling is not performed. The operation method of the oscillation device according to claim 11,
The oscillation device further includes a reference voltage generation circuit,
The operation method of the oscillation device is:
The reference voltage generation circuit further includes the step of generating the first reference voltage having no temperature dependence and the second reference voltage having a predetermined temperature dependence;
The step of generating the reference current by the current generation circuit includes:
Controlling the current mirror circuit side node of the resistor having a temperature dependence opposite to the temperature dependence of the second reference voltage to the second reference voltage;
And a step of generating the reference voltage based on the second reference voltage and the resistance.

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