EP2887176A1 - Electronic circuit with self-calibrated PTAT current reference, and method for operating same - Google Patents

Abstract

The electronic circuit (1) with current reference of the self-calibrated PTAT type comprises a PTAT current generator (3) dependent on an integrated resistor (8) for supplying a PTAT output current (I OUT). It further comprises a reference current generator (2) dependent on at least one switched capacitor resistor (12) for providing a reference current (I ref). The reference current (I ref) and the output current PTAT (I OUT) are compared in a comparator (6) to digitally adapt the programmable integrated resistor (8) or a transistor aspect ratio (P11, P12, P13) d a current mirror in the PTAT current generator for supplying the adapted PTAT (I OUT) output current.

Description

The invention relates to an electronic circuit provided with a self-calibrated PTAT current reference.

The invention also relates to the method of calibrating a current source of the PTAT type of the electronic circuit.

A PTAT type current is a current proportional to the absolute temperature. PTAT current sources are used in electronic circuits for providing at least one temperature dependent current. They can also be used in electronic circuits with a temperature sensor or in function management circuits in connection with a time base.

Generally for the generation of a current reference of the PTAT type in an electronic circuit integrated in a silicon substrate, it is used in a current generation branch a conventional resistor. The accuracy of such a resistance can vary by ± 30% with respect to a value estimated according to the manufacturing method, for example of the MOS type. It often has to be planned to calibrate such a resistance at the end of the manufacturing process to be able to ensure a sufficient accuracy of a current reference of the PTAT type, which is a drawback.

To calibrate the current reference of the PTAT type, it is possible to use a network of resistors and programmable switches connected to the resistors for the generation of this current. This requires at the end of any manufacturing process to measure the value of this current and to control the connection of several resistors to obtain the desired reference of this current PTAT. This complicates the adaptation operations of this current reference, which is a drawback.

The object of the invention is therefore to provide an electronic circuit provided with a self-calibrated PTAT type current reference to improve the current reference accuracy independently of any variation in the manufacturing process of the electronic circuit and overcoming the aforementioned drawbacks of the state of the art.

To this end, the invention relates to an electronic circuit provided with a self-calibrated PTAT type current reference, which comprises the characteristics mentioned in the independent claim 1.

Particular embodiments of the electronic circuit are defined in the dependent claims 2 to 13.

An advantage of the electronic circuit lies in the fact that it is possible to numerically adjust a resistor network for the generation of a PTAT current reference, by comparing an output current of a PTAT current generating unit with a current. reference current. The reference current is generated in a reference current generator based on a switched capacitor equivalent resistance.

Advantageously, it is also possible to digitally adapt a dimensional ratio of transistors of a current mirror of the PTAT current generation unit by the comparison between the PTAT output current and the reference current. Several transistors are therefore connectable in parallel in a current mirror of the generation unit for supplying the PTAT current.

Advantageously, a calibration of the PTAT current reference of the electronic circuit can be performed automatically as soon as the electronic circuit is turned on. The calibration is performed by several successive comparisons of the PTAT output current with the reference current by dichotomy. The comparison can be performed in a comparator. An adaptation of the resistive value of the resistance network or of the value of the output current by paralleling transistors of a current mirror is controlled via a processing unit receiving the information of the comparator.

Advantageously after the calibration of the PTAT current reference in a first phase, the reference unit, which supplies the reference current for comparison with the PTAT output current, can be disconnected. The timing signals of the switches of the switched capacitor resistor, which come from a time base, are suppressed to reduce consumption and avoid spectral pollution. With this automatic calibration of the PTAT output current, this PTAT current can be at least 2 to 3 times more accurate than such a current obtained with a standard integrated resistance of the state of the art, while taking into account the errors of pairing of the current mirrors and the current comparator.

For this purpose, the invention also relates to a method for calibrating a current source of the PTAT type of the electronic circuit, which comprises the characteristics defined in the independent claim 14.

Particular steps of the process are defined in dependent claims 15 to 17.

• la figure 1 représente de manière simplifiée les différents composants du circuit électronique à référence de courant PTAT auto-calibrée selon l'invention, et
• la figure 2 représente un graphique des signaux de cadencement des commutateurs en liaison à au moins un condensateur pour l'unité maître référence du circuit électronique à référence de courant PTAT auto-calibrée selon l'invention.

The aims, advantages and characteristics of the self-calibrated PTAT current reference electronic circuit, as well as the method of calibrating a current source of the PTAT type, will appear better in the following description on the basis of at least one form of non-limiting embodiment and illustrated by the drawings in which:

• the figure 1 represents in a simplified manner the various components of the self-calibrated PTAT current reference electronic circuit according to the invention, and
• the figure 2 represents a graph of the timing signals of the switches in connection with at least one capacitor for the reference master unit of the self-calibrated PTAT current reference electronic circuit according to the invention.

In the following description, all the electronic components of the PTAT current reference electronic circuit, which are well known to those skilled in the art, are only described in a simplified manner.

To the figure 1 , a first embodiment of the electronic circuit 1 is shown. The electronic circuit 1 comprises a so-called master unit for supplying a reference current I _ref of calibration, and a so-called slave unit 3 for supplying a PTAT current reference at the output I _OUT . The master unit 2 is a reference current generator I _ref of calibration dependent on a switched capacitor resistor 12. The slave unit PTAT 3 is a current generator for the supply of a current reference PTAT output I _OUT . The PTAT current reference provided by the PTAT generator is dependent on a resistor 8 whose resistive value R can be adjusted numerically as explained below. However, it is also possible to digitally adapt a transistor current transistors ratio in the current generator PTAT for the supply of the adapted current PTAT.

To adapt the output current PTAT I _OUT , a comparison in a comparator 6 is performed between the reference current I _ref of calibration of the master unit 2 and the output current PTAT I _OUT of the slave unit 3. In a ideal case or after calibration, the output current PTAT I _OUT is identical to the reference current I _ref . However, since the electronic circuit with the resistor 8 is integrated in a semiconductor substrate, such as a silicon substrate, the resistive value of the resistor 8 at the output of the MOS type manufacturing method is not precise. As a result, the output current PTAT I _OUT is not identical to the current I _ref . Under these conditions, the programmable resistor 8 is digitally adapted. The programmable resistor 8 can be adapted to become equivalent to the switched capacitor resistor 12. According to the comparison between the two currents, an output information of the comparator 6 is supplied to a processing unit 7 so as to control a digital adaptation of the programmable resistor 8.

This programmable resistor 8 can be composed of a network of resistors and programmable switches. The resistor network comprises several resistors of unit value in series and / or partly in parallel. In the case of unit resistors in series, switches may be provided by being connected in parallel with each unit resistor or groups of unit resistors, which is well known. The switches are controlled by digital signals or a control bit word from the processing unit 7 so as to bypass a number of unit resistors to adapt the resistive value of the programmable resistor 8.

The processing unit 7 thus provides a binary word for controlling the switches and adapting the programmable resistor. It is possible to provide a control bit word for example on 16 bits so as to adjust said programmable resistor 8. This makes it possible to guarantee an accuracy of at least ± 5% with respect to the estimated resistance, whereas without calibration , the error of the programmable resistor can be close to ± 30% as mentioned above. However, it must be taken into account in the accuracy of the pairing errors of the current mirrors and the current comparator 6, which can reduce the accuracy somewhat.

To adapt the programmable resistor 8, a dichotomy algorithm is preferably used in the processing unit 7. This makes it possible to converge rapidly to a final value of the programmable resistor. This adaptation is performed for a number of cycles according to the dichotomy algorithm. Once the output current PTAT I _OUT becomes identical to the reference current I _ref , a storage of the programmable programming bit word of the programmable resistor is performed in particular in a memory in the processing unit 7.

The master unit or reference current generator 2 comprises, first of all, a first current mirror composed of transistors N1, N2 of a first type of conductivity, for example NMOS type transistors. The master unit 2 further comprises a second current mirror composed of transistors P1, P2, P3 of a second conductivity type, for example PMOS type transistors. The first and second current mirrors are connected in series between two terminals of a supply voltage source V _DD . The first current mirror is preferably connected to a first terminal of the voltage source, which in this case is a ground terminal, while the second current mirror is preferably connected to a second terminal of the voltage source, which is the potential terminal high V _DD .

According to the first embodiment of the figure 1 , the first current mirror comprises a first NMOS transistor N1 whose source is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N2 whose gate is connected to the gate of the first transistor NMOS N1 and the source is connected to the switched capacitor resistor 12, as well as to a filter capacitor C _f . The switched capacitor resistor 12 and the filter capacitor C _f are also connected to the ground terminal in this embodiment.

The drain and the gate of the first NMOS transistor N1 are connected to the drain of a first PMOS transistor P1 of the second current mirror. The drain of the second NMOS transistor N2 is connected to the gate and the drain of a second PMOS transistor P2 of the second current mirror. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2. The second current mirror further comprises a third PMOS transistor P3 connected in parallel with the first and second PMOS transistors P1, P2. The gate of the third PMOS transistor P3 is connected to the gates of the first and second PMOS transistors P1, P2. The sources of the first, second and third PMOS transistors P1, P2, P3 are connected to the high potential terminal V _DD of the voltage source. The drain of the third PMOS transistor P3 provides the reference current I _ref of the reference current generator 2.

Since a switched capacitor resistor 12 is connected to the source of the second NMOS transistor N2, this NMOS transistor N2 is N times larger than the first NMOS transistor N1, which is considered a unitary transistor. This means that the second NMOS transistor N2 is composed of N first NMOS transistors N1, where N is an integer greater than or equal to 2. It can for example be chosen N = 6 so as to have a second transistor N2 6 times more large than the first transistor N1 or at least have a MOS channel width 6 times larger than the MOS channel width of the first transistor N1.

The switched capacitor resistor 12 therefore comprises a capacitor C, a first electrode of which is connected to a first switch 4 and to a second switch 5. A second electrode of the capacitor C is connected to the ground terminal. In the CMOS technology of the electronic circuit fabrication process, this capacitor C may be a CMOS capacitor type capacitor or a thin oxide metal electrode capacitor. This makes it possible to have a switched capacitor resistor 12 with an accuracy of the order of ± 5%, whereas an integrated standard resistor 8 is produced with an accuracy of the order of ± 30%.

The first switch 4 is disposed between the first electrode of the capacitor C and the ground terminal, while the second switch 5 is disposed between the first electrode of the capacitor C and the source of the second NMOS transistor N2. The first switch 4 is controlled by a first control signal φ1, while the second switch 5 is alternately controlled by a second control signal φ2. The first switch 4 is closed, when the second switch 5 is open, in a first phase, and the first switch 4 is open, when the second switch 5 is closed, in a second phase. Each switch may advantageously be implemented by means of a MOS transistor, for example an NMOS transistor, which is controlled on its gate by the corresponding control signal.

The figure 2 is a simplified representation of the two control signals φ1 and φ2, which are preferably non-overlapping. These signals control can be obtained via a timebase with a quartz oscillator. This time base of the crystal oscillator can also clock the operations of the processing unit 7. Each control signal comprises a rectangular control pulse per time period T. The rectangular pulse of the first control signal φ1 is a duration t1, which may be equal to T / 4, while the rectangular pulse of the second control signal φ2 has a duration t2, which can also be equal to T / 4. A time space of T / 4 between the rectangular pulses of the first and second control signals φ1 and φ2 can also be considered. The rectangular pulse at state "1" of the first control signal φ1 controls the closing of the first switch 4, while the rectangular pulse at the state "1 of the second control signal φ2 controls the closing of the second switch 5 .

The equivalent resistance, obtained by controlling the first and second switches 4 and 5 with the first and second control signals φ1 and φ2, is equal to T / C. T is the period of each control signal and C defines the capacity of the capacitor. By modifying the period T, the resistive value of the equivalent resistance can be modified. This equivalent resistance of the master unit 2 can be established with an accuracy of ± 5% according to the manufacturing method of the electronic circuit integrated in a traditional silicon substrate. This equivalent resistance 12 may be identical to the programmable resistor 8 adapted numerically in the slave unit 3 after the calibration of the PTAT current.

As a result of the calibration of the output current PTAT I _OUT , the generator of the reference current 2 and the time base for the supply of the control signals φ1 and φ2 can be disconnected. Only the calibrated PTAT current generator remains operational with a PTAT I _OUT output current accuracy guaranteed with accuracy, which can be at least ± 5% of the expected value.

In a manner similar to the master unit 2, the slave unit PTAT 3 or the current generator PTAT 3 comprises a first current mirror composed of transistors N11, N12 of a first conductivity type, for example NMOS type transistors. The slave unit PTAT 3 further comprises a second current mirror composed of transistors P11, P12, P13 of a second conductivity type, for example of PMOS type transistors. The first and second current mirrors are connected in series between two terminals of a supply voltage source V _DD . The first current mirror is preferably connected to the first terminal of the voltage source, which in this case is the ground terminal, while the second current mirror is preferably connected to the second terminal of the voltage source, which is the potential terminal high V _DD .

As shown in figure 1 the first current mirror comprises a first NMOS transistor N11, whose source is connected to ground, and the drain and the gate are connected together, and a second NMOS transistor N12, whose gate is connected to the gate of the first transistor NMOS N11 and the source is connected to the programmable resistor 8, which is also connected to the ground terminal.

The drain and the gate of the first NMOS transistor N11 are connected to the drain of a first PMOS transistor P11 of the second current mirror. The drain of the second NMOS transistor N12 is connected to the gate and the drain of a second PMOS transistor P12 of the second current mirror. The gate of the first PMOS transistor P11 is connected to the gate of the second PMOS transistor P12. The second current mirror of the slave unit PTAT 3 further comprises a third PMOS transistor P13 connected in parallel with the first and second PMOS transistors P11, P12. The gate of the third PMOS transistor P13 is connected to the gates of the first and second PMOS transistors P11, P12. The sources of the first, second and third PMOS transistors P11, P12, P13 are connected to the high potential terminal V _DD of the voltage source. The drain of the third PMOS transistor P13 provides the output current PTAT I _OUT of the current generator PTAT 3.

Since the programmable resistor 8 is connected to the source of the second NMOS transistor N12, this NMOS transistor N2 is N 'times larger that the first NMOS transistor N11, which is considered a unitary transistor. This means that the second NMOS transistor N12 is composed of N 'first NMOS transistors N11, where N' is an integer greater than or equal to 2. It can for example be chosen N '= 6 as for the second transistor N2 of the 2. This allows to have a second transistor N12 6 times larger than the first transistor N11 or at least have a MOS channel width 6 times larger than the MOS channel width of the first transistor N11. However, the number N 'may be different from the number N.

It should also be noted that the third PMOS transistor P13 may also be provided M times larger than the first PMOS transistor P11 and the second PMOS transistor P12 of the second current mirror of the slave unit PTAT 3. M is an integer more greater than or equal to 1. In the case where M is equal to 1, the programmable resistor 8, which has been adapted, may be equivalent to the switched capacitor resistor 12 of the master unit 2.

According to an alternative embodiment of the electronic circuit 1 not shown, it can be used in place of the third PMOS transistor P13, a set of unit transistors combined with digitally controlled switches. Instead of digitally adapting the programmable resistor 8, it can be envisaged to have a resistance 8 of defined value, and to digitally adapt a PMOS transistors ratio of the second current mirror, which provide the output current. PTAT I _OUT . A binary adaptation word is provided at the end of the calibration cycles by the dichotomy algorithm. This binary word for configuring the set of transistors is stored in the processing unit 7.

It can also be envisaged to invert the electronic structure of the master unit 2 and of the slave unit 3. The first current mirror with the NMOS transistors can be replaced by a first current mirror with PMOS transistors, which is connected to the high potential terminal V _DD , while the second current mirror with the PMOS transistors can be replaced by a second current mirror with NMOS transistors, which is connected to the ground terminal. In this case, the switched capacitor resistor 12 and the programmable resistor 8 are connected to the high potential terminal V _DD .

It may also be envisaged to have several switched capacitor resistors arranged in parallel and each controlled by two control signals specific to each switched capacitor resistor.

From the description that has just been given, several alternative embodiments of the current reference electronic circuit PTAT can be designed by those skilled in the art without departing from the scope of the invention defined by the claims.

Claims (17)

Electronic circuit (1) with self-calibrated PTAT type current reference, the electronic circuit (1) comprising a PTAT current generator (3) depending on at least one integrated resistor (8) for supplying a current PTAT output (I _OUT ),
characterized in that the electronic circuit (1) further comprises a reference current generator (2) dependent on at least one switched capacitor resistor (12) for supplying a reference current (I _ref ), and
in that the reference current (I _ref ) and the output current PTAT (I _OUT ) are compared in a comparator (6) so as to digitally adapt the integrated resistor (8), which is programmable, or to digitally adapt a dimensional ratio of transistors (P11, P12, P13) of a current mirror in the PTAT current generator, for providing the adapted PTAT (I _OUT ) output current. Electronic circuit (1) according to claim 1, characterized in that the comparator (6) is connected to a processing unit (7) for receiving information at the output of the comparator (6), as a function of the comparison between the reference current (I _ref ) and the output current PTAT (I _OUT ) for controlling a digital adaptation of the programmable resistor (8) or the transistors (P11, P12, P13). Electronic circuit (1) according to claim 2, characterized in that the processing unit (7) is intended to implement a dichotomy algorithm for the cyclic adaptation of the programmable resistor (8) or the transistors dimensional ratio. (P11, P12, P13), and in that the processing unit comprises a memory for storing a final binary word of digital adaptation of the programmable resistor (8) or of the transistors (P11, P12, P13) . Electronic circuit (1) according to claim 1, characterized in that the reference current generator (2) comprises a first mirror of a current composed of transistors (N1, N2) of a first conductivity type, and a second current mirror composed of transistors (P1, P2, P3) of a second conductivity type, the first and second current mirrors being serially connected between two terminals of a supply voltage source (V _DD ), and in that the switched capacitor resistor (12) is connected to a source or emitter of a transistor (N2) of the first mirror of current and in series with the first and second current mirrors between the terminals of the voltage source. Electronic circuit (1) according to claim 4, characterized in that the first current mirror comprises NMOS transistors (N1, N2), and in that the second current mirror comprises PMOS transistors (P1, P2 , P3). Electronic circuit (1) according to claim 5, characterized in that the first current mirror comprises a first NMOS transistor (N1) and a second NMOS transistor (N2), in that the first NMOS transistor (N1) comprises a connected source to a ground terminal, and a gate connected to a drain, in that the second NMOS transistor (N2) comprises a source connected to the switched capacitor resistor (12), which is connected to the ground terminal, a connected gate to the gate of the first NMOS transistor (N1), in that the second current mirror comprises a first PMOS transistor (P1), a second PMOS transistor (P2) and a third PMOS transistor (P3), the three PMOS transistors each having a source connected to a high potential terminal of the voltage source (V _DD ) and gates connected to each other, in that the first PMOS transistor (P1) comprises a drain connected to the gate and the drain of the first transistor NMOS (N1), in that the second transistor or PMOS (P2) comprises a drain connected to its gate and to a drain of the second NMOS transistor (N2), and in that the third PMOS transistor (P3) comprises a drain for supplying the reference current (I _ref ). Electronic circuit (1) according to claim 6, characterized in that the second NMOS transistor (N2) is N times larger than the first NMOS transistor (N1), where N is an integer greater than or equal to 2, preferably equal to 6. Electronic circuit (1) according to claim 4, characterized in that the switched capacitor resistor (12) comprises a capacitor (C), a first switch (4) connected in parallel with the capacitor, and a second switch (5) connected between an electrode of the capacitor and the source or emitter of the transistor (N2) of the first current mirror, in that the first switch (4) is controlled by a first control signal (φ1), and in that the second switch (5) is controlled by a second control signal (φ2), the first and second control signals being generated via a time base and arranged in such a manner that the first switch is open when the second switch is closed, and vice versa. Electronic circuit (1) according to claim 1, characterized in that the PTAT current generator (3) comprises a first current mirror composed of transistors (N11, N12) of a first conductivity type, and a second current mirror composed of transistors (P11, P12, P13) of a second conductivity type, the first and second current mirrors being connected in series between two terminals of a supply voltage source (V _DD ), and in that the resistor (8) is connected to a source or emitter of a transistor (N12) of the first current mirror and in series with the first and second current mirrors between the terminals of the voltage source. Electronic circuit (1) according to claim 9, characterized in that the first current mirror comprises NMOS transistors (N11, N12), and in that the second current mirror comprises PMOS transistors (P11, P12). , P13). Electronic circuit (1) according to claim 10, characterized in that the first current mirror comprises a first NMOS transistor (N11) and a second NMOS transistor (N12), in that the first NMOS transistor (N11) comprises a connected source to a ground terminal, and a gate connected to a drain, in that the second NMOS transistor (N12) comprises a source connected to the resistor (8), which is connected to the ground terminal, a gate connected to the gate of the first NMOS transistor (N11), in that the second current mirror comprises a first PMOS transistor (P11), a second PMOS transistor (P12) and a third PMOS transistor (P13), the three PMOS transistors each having a source connected to a high potential terminal of the voltage source (V _DD ) and gates connected to each other, in that the first PMOS transistor (P11) comprises a drain connected to the gate and the drain of the first NMOS transistor (N11), in that the second PMOS transistor (P12) comprises a drain connected to its gate and to a drain of the second NMOS transistor (N12), and in that the third PMOS transistor (P13) comprises a drain for providing the output current PTAT (I _OUT ). Electronic circuit (1) according to claim 11, characterized in that the second NMOS transistor (N12) is N 'times larger than the first NMOS transistor (N1), where N' is an integer greater than or equal to 2, preferably equal to 6. Electronic circuit (1) according to claim 11, characterized in that the third PMOS transistor (P13) is composed of a set of unitary transistors, which are combined with digitally controlled switches to adapt the output current PTAT (I _OUT ) . Method for calibrating a current source of the PTAT type of the electronic circuit (1) according to one of the preceding claims, characterized in that it comprises the steps of: - supply a PTAT output current (I _OUT ) of the PTAT current generator (3), supplying a reference current (I _ref ) of the reference current generator (2), comparing the output current PTAT (I _OUT ) and the reference current (I _ref ), and - Digitally adapt the programmable integrated resistor (8), or a dimensional ratio of transistors (P11, P12, P13) of a current mirror in the generator of the PTAT current. Method according to claim 14, characterized in that the digital adaptation is carried out for a number of cycles according to a dichotomy algorithm in a processing unit (7). Method according to Claim 15, characterized in that storage of a digital word supplied by the processing unit (7) is carried out in a memory of the processing unit at the end of the cycles of adaptation of the output current PTAT (I _OUT ). Method according to one of Claims 15 and 16, characterized in that, at the end of the PTAT output current matching cycles (I _OUT ), the reference current generator (2) is disconnected, as well as the supply of control signals of the switched capacitor resistor (12).

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