EP2677652A1 - Dispositif d'inversion de source de courant, et procédé de commande de dispositif d'inversion de source de courant - Google Patents

Dispositif d'inversion de source de courant, et procédé de commande de dispositif d'inversion de source de courant Download PDF

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Publication number
EP2677652A1
EP2677652A1 EP12869041.9A EP12869041A EP2677652A1 EP 2677652 A1 EP2677652 A1 EP 2677652A1 EP 12869041 A EP12869041 A EP 12869041A EP 2677652 A1 EP2677652 A1 EP 2677652A1
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EP
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Prior art keywords
current
switching element
commutation
resonant
source
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EP12869041.9A
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German (de)
English (en)
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EP2677652A4 (fr
EP2677652B1 (fr
Inventor
Itsuo Yuzurihara
Toshiyuki Adachi
Shinichi Kodama
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Kyosan Electric Manufacturing Co Ltd
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Kyosan Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/01—Resonant DC/DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571—Half-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4815—Resonant converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a current source inverter for supplying current to a load such as a plasma load, for example, and a method for controlling the current source inverter.
  • a current source inverter is provided with a DC reactor connected to a DC source, a converter for converting DC power from the DC reactor into AC power, and a controller for performing a drive control of switching elements in the converter, and this current source inverter is characterized in that it operates on reducing fluctuations of load impedance caused by a load short or the like, since the inverter is allowed to be treated as a current source when viewed from the load side.
  • the inverter operates to maintain the plasma.
  • the current source inverter has such an advantage as supplying current stably to the load, even when the load fluctuates as described above, it is suitable for supplying power to the plasma load where impedance varies depending on circumstances.
  • the current source inverter supplies a steady current to the load, and thus suppressing excessive supply of current to the plasma load. Therefore, it is possible to reduce damage on the plasma load.
  • FIG. 15 illustrates one configuration example of the current source inverter.
  • the current source inverter 100 is provided with a current source step-down type chopper circuit 101, a three-phase inverter circuit 102, and a three-phase transformer 103.
  • the current source step-down type chopper circuit 101 performs chopper control of a switching element Q1, thereby stepping down DC, being inputted from an AC source and a rectifier circuit not illustrated, smoothing the current in a DC reactor LF1, and inputting the current into the three-phase inverter circuit 102.
  • a current source step-down and -up type chopper circuit may be employed, instead of the current source step-down type chopper circuit 101.
  • the three-phase inverter circuit 102 controls at a predetermined timing, arc striking and arc extinguishing of the switching elements Q R , Q S , Q T , Q X , Q Y , and Q Z , thereby causing commutation between the elements, so as to supply AC power to the three-phase transformer 103.
  • This current source inverter has a problem that when all the switching elements break the passage of electric current, there is a possibility that current from the DC reactor applies overvoltage on the switching elements and causes element destruction. There is another problem that at the time of commutation, current and voltage are generated on the switching elements, and this may cause the element destruction.
  • FIG. 16 and FIG. 17 illustrate the switching loss at the time of commutation in the circuit operation shown in FIG. 15 .
  • FIG. 16 illustrates the case where the commutation is performed, without overlapping of the ON state between the switching element being the commutation source and the switching element being the commutation target.
  • the switching element Q R is assumed as the commutation source
  • the switching element Q S is assumed as the commutation target
  • gate pulse signals G R and G S set those elements to be the ON state, respectively ( FIG. 16A and 16B ). Since a falling edge of the gate pulse signal G R agrees with a rising edge of the gate pulse signal G S , commutation between the switching elements is performed without overlapping.
  • FIG. 16 illustrates the case where the commutation is performed, without overlapping of the ON state between the switching element being the commutation source and the switching element being the commutation target.
  • the switching element Q R is assumed as the commutation source
  • the switching element Q S is
  • the time constants of the current I QR and the voltage V QR (drain-to-source voltage of the switching element) flowing in the switching element Q R at the commutation source change at the time of being turned OFF, under the influence of wiring inductance, element capacity, load inductance, and the like. Therefore, they do not achieve ZCS and ZVS at the time of commutation, and a switching loss occurs. In addition, surge voltage is generated, and this may cause damage on the switching element.
  • the resonant inverter connects a freewheeling diode and a resonant capacitor with the switching element in parallel, and a resonant circuit is made up of the resonant capacitor, the resonant inductance, and the switching element connected to the resonant circuit. Discharging and charging of the resonant capacitor by the resonant current from the resonant circuit, and conduction of the freewheeling diode achieve ZVS (zero voltage switching) and ZCS (zero current switching) in the switching element (e.g., Patent Document 2).
  • the timing for driving the switching element is controlled to prevent the switching loss and/or element destruction. Therefore, it is necessary to detect load current, or current in the switching element, for instance. Further in the configuration for controlling the switching element by detecting the current overlap time during when the current of the switching element at the commutation source becomes zero, it is necessary to detect the load current and load voltage so as to detect the current overlap time.
  • An object of the present invention is to solve the aforementioned conventional problems, and in controlling the switching element in the current source inverter, the switching loss of the switching element is prevented according to a normal switching operation for the commutation, without requiring any particular control.
  • the present invention provides a fixed overlap period in commutation, in which an overlap time duration (phase width) is predetermined so as to obtain an overlap time being sufficient for addressing fluctuation in a load current.
  • an overlap time duration (phase width) of the overlap period in commutation is a width that is determined regardless of the load current fluctuation.
  • Setting of the overlap period in commutation controls the timing for driving the switching element. A drive timing control by the overlap period in commutation between the switching elements controls the resonant circuit, and reduces the switching loss at the commutation operation in the switching elements according to resonant current of the resonant circuit.
  • the overlap period in commutation is predetermined so that sufficient overlap time duration (phase component) is obtained, and in addition, the switching elements are controlled within the overlap period in commutation to allow resonant current to flow in the resonant circuit, thereby reducing the switching loss according to the resonant current.
  • the present invention is directed not only to the generation of the overlap period during when both the switching element at the commutation source and the switching element at the commutation target are set to be the ON state, so as to reduce the switching loss of the switching element.
  • the present invention is also directed to a control of resonant current generation in the resonant circuit by using the control of the switching elements having the overlap period, and according to this resonant current being generated in this control, the current and the voltage of the switching element at the commutation source to be zero upon commutation, thereby reducing the switching loss at the time of the commutation operation.
  • One aspect of the present invention is directed to a current source inverter, and another aspect of the present invention is directed to a method for controlling the current source inverter.
  • the current source inverter is provided with a current source chopper constituting a DC source, a multiphase inverter for converting DC output from the current source chopper into multiphase AC power according to operations of multiple switching elements, a controller for controlling the current source chopper and the multiphase inverter, and a resonant circuit for supplying resonant current to the switching elements in the multiphase inverter.
  • the controller controls timing for driving a switching element at the commutation target and a switching element at the commutation source, upon commutation between the switching elements in the multiphase inverter. Controlling of the timing for driving the switching elements allows generation of an overlap period during when both the switching element at the commutation target and the switching element at the commutation source to be set to the ON state, and simultaneously allows the resonant current in the resonant circuit to be controlled.
  • the resonant current of the resonant circuit is supplied to the switching element at the commutation source in the reverse biased direction, and it is also supplied to the freewheeling diode in the forward biased direction, the diode being connected to the switching element in inverse-parallel.
  • the current source inverter and the control method thereof according to the present invention are not limited to a three-phase inverter for converting DC power into three-phase AC power, but it is also applicable to a multiphase inverter for converting DC power into optional multiphase AC power, i.e., equal to or more than two-phase AC power.
  • the resonant circuit according to the present invention is configured in such a manner that an output from the switching element at the commutation target is set as a source for supplying the resonant current, and during the overlap period, the switching element at the commutation target is set to be the ON state before the switching element at the commutation source is set to be the OFF state, thereby introducing the current which flows in the forward direction to the switching element at the commutation target, into the resonant circuit to generate the resonant current.
  • the resonant circuit of the present invention is provided with current feed ends, the number of which is equal to the number of phases of the AC power being converted by the multiphase inverter.
  • the current feed ends are respectively connected to connection terminals of opposed switching elements in the bridge configuration of the switching elements which form the multiphase inverter.
  • the resonant current introduced into the switching element at the commutation source flows inversely relative to the forward current flowing in the switching element at the commutation source, the resonant current cancels the forward current, thereby rendering the current flowing in the switching element at the commutation source to zero.
  • the resonant current also flows into the freewheeling diode, thereby rendering the voltage in the switching element at the commutation source to be zero.
  • the zero current state and the zero voltage state of the switching element at the commutation source are maintained during the overlap period, and switching of the switching element at the commutation source, from the ON state to the OFF state is carried out under the condition of zero current and zero voltage, thereby achieving the commutation according to ZCS and ZCS.
  • the circuit of the resonant circuit according to the present invention may be configured in such a manner that an LC series circuit is provided in each between terminals which are formed by the current feed ends, for instance.
  • the LC series circuit inputs forward current of the switching element at the commutation target, upon commutation between the switching elements of the multiphase inverter, and generates resonant current, and supplies the resonant current thus generated to the switching element at the commutation source in the reverse biased direction.
  • the multiphase inverter of the present invention converts DC power into n-phase AC power
  • reactance L and capacitance C of the LC series circuit constituting the resonant circuit satisfies the condition of (L ⁇ C) 1/2 > n/n, so that the resonant current does not flow in another switching element which is set to be the ON state next.
  • the condition which the reactance L and capacitance C of the LC series circuit are required to satisfy is; (L ⁇ C) 1/2 > ⁇ /3.
  • the multiphase inverter of the present invention converts DC power into n-phase AC power
  • the phase component ⁇ t during the overlap period satisfies n/2n > ⁇ t as a condition for preventing a short circuit between the switching elements.
  • phase component ⁇ t during the overlap period satisfies ⁇ /2n> ⁇ t, thereby preventing the short circuit between the two switching elements, being opposed upside and downside of DC power within the inverter bridge configuration.
  • the condition which the phase component ⁇ t of the overlap period is required to satisfy is n/6 > ⁇ t.
  • the maximum peak value of the resonant current in the resonant circuit is set to be larger than a phase current value of each phase in the multiphase inverter.
  • the method for controlling the current source inverter is a method which converts DC power from the current source chopper into multiphase AC power, according to the operation of multiple switching elements held in the multiphase inverter.
  • timing for driving the switching element at the commutation target and the switching element at the commutation source is controlled, thereby generating an overlap period during when both the switching element at the commutation target and the switching element at the commutation source are set to be the ON state, and controlling the resonant current.
  • the resonant current in the resonant circuit is supplied to the switching element at the commutation source in the reverse biased direction, and the freewheeling diode being connected to this switching element in inverse-parallel is supplied with the resonant current in the forward biased direction.
  • this current supply zero current and the zero voltage are achieved during the overlap period in the switching element at the commutation source, and the commutation operation is performed under the condition of the zero current and zero voltage, at the point when the switching element at the commutation source is switched from the ON state to the OFF state.
  • the multiphase inverter is provided with a bridge configuration of the switching elements, and the resonant circuit is connected to inter-connection terminals of the switching elements being opposed in the bridge configuration.
  • the resonant circuit is connected to inter-connection terminals of the switching elements being opposed in the bridge configuration.
  • the multiphase inverter is an inverter which converts DC power into n-phase AC power
  • a condition to be satisfied by the phase component ⁇ t of the overlap period in order to prevent a short circuit between the switching elements is n/2n > ⁇ t.
  • the condition to be satisfied by the phase component ⁇ t of the overlap period is n/6 > ⁇ t.
  • the condition for reducing the forward current flowing in the switching element at the commutation source to zero, during the overlap period, is as the following; sin( ⁇ t) > (phase current of the multiphase inverter / the maximum peak value of the resonant current).
  • the maximum peak value of the resonant current in the resonant circuit is set to be larger than the phase current value of each phase in the multiphase inverter.
  • the current source inverter and the method for controlling the current source inverter of the present invention it is possible to prevent a switching loss by a normal switching operation for the commutation operation, without requiring any particular additional control, in the control of the switching elements of the current source inverter.
  • FIG. 1 and FIG. 2 are used to illustrate the configuration example of the current source inverter
  • FIG. 3 and FIG. 4 are used to illustrate the control example of the current source inverter.
  • FIG. 5 to FIG. 13 the inverter circuit and the resonant circuit according to the present invention will be explained.
  • a three-phase inverter is illustrated as an example of the multiphase inverter.
  • the current source inverter 1 of the present invention as shown FIG. 1 is provided with a rectifier 10 for rectifying AC power of an AC source 2, a snubber 20 for constituting a protection circuit which suppresses high voltage generated transiently, a current source step-down type chopper 30 for converting voltage of DC power inputted from the rectifier 10 into a predetermined voltage to output DC power, a multiphase inverter 40 for converting the DC output from the current source step-down type chopper 30 into multiphase AC output, a multiphase transformer 50 for converting the AC output from the multiphase inverter 40 into a predetermined voltage, and a multiphase rectifier 60 for converting the AC from the multiphase transformer 50 into DC.
  • a rectifier 10 for rectifying AC power of an AC source 2
  • a snubber 20 for constituting a protection circuit which suppresses high voltage generated transiently
  • a current source step-down type chopper 30 for converting voltage of DC power inputted from the rectifier 10 into a pre
  • a step-down and -up type chopper may be employed as the chopper for carrying out the DC-AC conversion, instead of the aforementioned current source step-down type chopper 30.
  • the current source step-down type chopper 30 is provided with a switching element Q 1 , a diode D 1 , and a DC reactor L F1 .
  • the switching element Q 1 performs chopper control on the DC voltage having been rectified by the rectifier 10, thereby accomplishing step-down of voltage.
  • the DC reactor L F1 subjects the DC after the chopper control is performed to current smoothing, and inputs the smoothed current into the multiphase inverter 40.
  • the control circuit 80 inputs chopper current of the current source step-down type chopper 30 and a detection value of the output voltage from the current source inverter 1, and performs the chopper control on the switching element Q 1 so that the inputted current and the output voltage become a predetermined current and a predetermined output voltage, respectively.
  • FIG. 2 shows an example of the current source inverter 1 according to the present invention, where another configuration example of the current source step-down type chopper 30 is included.
  • the current source step-down type chopper 30 as shown in FIG. 2 has a configuration that an output capacitor C F1 is connected in parallel to the output end.
  • the output capacitor is installed, which is not usually provided in the current source step-down type chopper.
  • the output capacitor C F1 is connected to the output end of the current source step-down type chopper 30
  • the output capacitor absorbs a surge voltage generated when commutation operation is performed between the switching elements in the multiphase inverter 40, and energy of the inductance connected in series with each switching element, thereby achieving protection of the switching elements.
  • a value of the output capacitor C F1 is set to such an extent that a delay of the current does not have an impact on the commutation of the inverter operation, according to a time constant of this output capacitor and wiring inductance.
  • the multiphase inverter 40 is provided with a multiphase inverter circuit which is made up of a bridge connection of switching elements, the number of which is associated with the number of phases.
  • the three-phase inverter circuit is made up of six switching elements.
  • the switching element for instance, a semiconductor switching element such as IGBT and MOSFET may be employed.
  • Each switching element of the inverter circuit performs switching operation based on a control signal from the switching controller 81, and converts DC power into AC power to output the AC power.
  • the multiphase inverter 40 is provided with a resonant circuit 70, and introduces the resonant current generated in the resonant circuit 70 into the switching elements in the commutation state in the multiphase inverter circuit, and performs commutation between those switching elements under the condition of zero current and zero voltage.
  • the resonant circuit 70 of the present invention generates the resonant current in sync with the commutation operation of each switching element in the multiphase inverter circuit, introduces the resonant current into the switching element at the commutation source, and performs the commutation operation of the switching element at the commutation source according to ZCS (zero current switching) and ZVS (zero voltage switching).
  • the AC output from the multiphase inverter 40 is allowed to become high frequency output by increasing switching frequency of the switching element.
  • the current source inverter for instance, supplies high-frequency output of 200 KHz to the load.
  • the multiphase inverter circuit performs switching operation of the switching element at high frequency. As thus described, when the switching element is switched at a high drive frequency, the AC output includes a high-frequency ripple component.
  • the multiphase rectifier 60 is provided with a DC filter circuit on the output part, similar to a normal multiphase rectifier circuit, as one configuration example for removing the high-frequency ripple component included in the AC output from the multiphase inverter 40.
  • the DC filter circuit may be made up of an output capacitor C FO connected in parallel to the output end, and an output reactor L FO connected in series therewith.
  • the current source inverter 1 may be configured in such a manner as outputting DC output from the multiphase rectifier 60, via wiring inductance L 0 provided in the wiring, without the aforementioned series filter circuit, and connecting the current source inverter 1 with the plasma generator 4 being a plasma load via the output cable 3, thereby allowing a use of parasitic impedance of the current source inverter as a configuration for removing the high-frequency ripple component.
  • inductance held by the wiring impedance 90 between the multiphase rectifier 60 and the output terminal, inductance L FO included in the output cable connected between the current source inverter 1 and the load, and electrode capacity C 0 of the plasma generator 4 in the case of plasma load may constitute a filter circuit for removing the high frequency component, similar to the series filter circuit, thereby reducing the high-frequency ripple component.
  • the current source inverter is assumed as a power supply source for the plasma generator, when an arc is generated in the plasma generator 4 on the load side, it is possible to assume that the load is short-circuited, and arc energy P c is supplied from the output capacitor C FO of the series filter circuit which is provided on the current source inverter side.
  • the arc energy P c of the plasma generator 4 is equal to or less than 1 mJ per 1 kW power output.
  • the inductance L FO and L O indicate small values, and therefore, the energy (L FO + L O ) ⁇ I O 2 of the inductance L FO and L O may be ignored relative to 1 mJ/kW.
  • 1 mJ/kW represents energy in the unit of mJ per 1 kW of output power, and the energy for the output power 100 kW corresponds to 100 mJ.
  • the current source inverter has a configuration which utilizes the wiring impedance or the parasitic impedance of the output cable or of the electrode capacity of the plasma generator, instead of the DC filter circuit, it is possible to remove the high-frequency ripple component and supply the arc energy P c , as far as the capacity corresponding to the output capacity C FO is large enough for supplying the arc energy P c .
  • the high-frequency ripple component possesses a property to increase, when the drive frequency of the multiphase inverter circuit is decreased. Therefore, by increasing the drive frequency of the multiphase inverter circuit, it is possible to reduce the necessity of the output capacitor C FO and the output reactor L FO . In addition, increase of the drive frequency of the multiphase inverter circuit may cause suppression on the energy held inside the current source inverter 1.
  • FIG. 3 illustrates schematic block diagrams and operation diagrams of the current source inverter
  • FIG. 4 is a timing chart for explaining a commutation state of the switching elements in the current source inverter. It is to be noted that in FIG. 3 , the state of current flow through the elements and the wiring is represented by light and dark in color, and a conduction state is illustrated being dark in color, and a non-conduction state is illustrated being light in color.
  • the current source inverter shown in FIG. 3 is made up of a bridge connection of six switching elements Q R , Q S , Q T , Q X , Q Y , and Q Z , the switching element Q R and the switching element Q X are connected in series, the switching element Q S and the switching element Q Y are connected in series, and the switching element Q T and the switching element Q Z are connected in series.
  • connection point between the switching element Q R and the switching element Q X is connected as an R-phase component of the three-phase transformer 51 via the inductance L m1
  • the connection point between the switching element Q S and the switching element Q Y is connected as an S-phase component of the three-phase transformer 51 via the inductance L m2
  • the connection point between the switching element Q T and the switching element Q YZ is connected as a T-phase component of the three-phase transformer 51 via the inductance L m3 .
  • connection point between the switching element Q R and the switching element Q X , the connection point between the switching element Q S and the switching element Q Y , and the connection point between the switching element Q ST and the switching element Q Z are respectively connected to the terminals of the resonant circuit, and resonant current is supplied from the resonant circuit.
  • the timing chart as shown in FIG. 4 illustrates an example of the commutation operation between the switching element Q R and the switching element Q S .
  • the switching element Q R is assumed as the switching element at the commutation source
  • the switching element Q S is assumed as the switching element at the commutation target.
  • the commutation operation is controlled so that an overlap period is generated during when both the switching element at the commutation source and the switching element at the commutation target are set to be the ON state, and the resonant current of the resonant circuit is controlled in sync with this commutation operation, thereby supplying the resonant current to the switching element at the commutation source.
  • the overlap period during when both the switching element Q R at the commutation source and the switching element Q S at the commutation target are set to be the ON state is generated, by setting the timing for rising edge of a gate pulse signal G S ( FIG. 4B ) of the switching element Q S , to be prior to the falling edge of the gate pulse signal G R ( FIG. 4A ) of the switching element Q R , whereby the gate pulse signal G R which sets the switching element Q R to be the ON state and the gate pulse signal G S ( FIG. 4B ) which sets the switching element Q S to be the ON state are allowed to overlap one another in time wise. Therefore, the switching element Q S is set to be the ON state before the switching element Q R is switched from the ON state to the OFF state, and during the overlap period, both the switching element Q R and the switching element Q S are set to be the ON state.
  • the switching element Q R is in the ON state, and current I QR ( FIG. 4C ) flows in the switching element Q R , and the current I QS ( FIG. 4D ) of the switching element Q S does not flow.
  • FIG. 3A illustrates an operating state and a current state of the switching elements during the period A.
  • the current I QR ( FIG. 4C ) of the switching element Q R is supplied to the three-phase transformer 51 as primary current in R phase I R ( FIG. 4H ), and returns via the switching element Q Z .
  • the gate pulse signal G S sets the switching element Q S to be the ON state, and the current I QS ( FIG. 4D ) starts to flow in the switching element Q S .
  • the current I QS of the switching element Q S increases by the time constant according to the resonance circuit 70, inductance L m1 , and inductance L m2 , and therefore, at the time when the switching element Q S is turned to be the ON state, ZCS (zero current switching) is performed ( FIG. 4D ).
  • resonant current starts flowing into the resonant circuit 70 ( FIG. 4G ).
  • the resonant current flows in the reverse biased direction to the switching element Q R . Since this resonant current is inversely directed relative to the forward current I QR in the switching element Q R , the resonant current cancels the current I QR and decreases the current ( FIG. 4C ).
  • the number 1 each enclosed within a circle in FIG. 4C and FIG. 4G indicates current components in the relationship canceling each other.
  • FIG. 3B illustrates the operating state and the current state of the switching elements during the period B.
  • the forward current of the switching element Q R is canceled by the resonant current, and the primary current I R ( FIG. 4H ) according to a part of the resonant current and the primary current I S ( FIG. 4H ) according to the switching element Q S are supplied to the three-phase transformer 51, and return via the switching element Q Z .
  • the current I QR of the switching element I QR ( FIG. 4C ) is canceled by the resonant current ( FIG. 4G ) and becomes zero current.
  • a surplus of the resonant current starts flowing in the form of diode current I DR ( FIG. 4E ) into the freewheeling diode D R which is connected in parallel to the switching element Q R .
  • the number 2 each enclosed within a circle in FIG. 4E and FIG. 4G indicates current components in the relationship being associated with each other.
  • both the switching element Q R and the switching element Q S are in the ON state.
  • the current I QR ( FIG. 4C ) of the switching element Q R is continued to be canceled by the resonant current ( FIG. 4G ) to keep zero current, and the current I QS ( FIG. 4D ) of the switching element Q S increases along with the increase of the resonant current. Accordingly, a drain-to-source voltage V D-S of the switching element Q R is kept to be zero voltage ( FIG. 4F ).
  • the switching element Q R at the commutation source is set to be the OFF state at the falling edge of the gate pulse signal G R , the switching element Q S is in the ON state and the switching element Q R is in the OFF state, and accordingly establishing the ON state and OFF state being different from each other.
  • the switching element Q R is set to be the OFF state, and stops the flow of the current I QR , together with stopping the canceling by the resonant current.
  • the resonant current continues to flow in the freewheeling diode D R .
  • the current I QR flowing in the switching element Q R is kept to be in the zero current state after the switching element Q R at the commutation source becomes the OFF state, in succession to the zero current state established by the resonant current, whereby the switching element Q R at the commutation source achieves ZCS (zero current switching).
  • the resonant current flows into the freewheeling diode D R of the switching element Q R , whereby the switching element Q R at the commutation source achieves ZVS (zero voltage switching).
  • This period C ends at the point when the resonant current becomes zero.
  • FIG. 3C illustrates the operating state and the current state of the switching elements during the period C.
  • the resonant current cancels the forward current of the switching element Q R to establish zero current, and flows into the freewheeling diode D R to establish zero voltage.
  • the primary current I R according to a part of the resonant current, and the primary current I S according to the switching element Q S are supplied to the three-phase transformer 51, and return via the switching element Q Z ( FIG. 4H ).
  • the primary current I R has the same current value as the primary current I S , being half relative to the current when either one primary current flows.
  • the period during when both the primary current I R and the primary current I S flow together corresponds to the period C in FIG. 4H , excluding a part when the period C is switched to the period D.
  • the primary current I R decreases toward the intermediate current, and the primary current I S increases toward the intermediate current. Further at the part for switching to the period D in the period C in FIG. 4H , the primary current I R decreases toward zero current from the intermediate current, and the primary current I S increases from the intermediate current to the total primary current. According to the aforementioned switching operation from the current I QR to the current I QS , the primary current is kept to be supplied without interruption, from the current source step-down type chopper to the three-phase transformer 51.
  • FIG. 3D illustrates the operating state and the current state of the switching elements during the D period.
  • the resonant current stops, and the primary current I S according to the switching element Q S is supplied to the three-phase transformer 51, and returns via the switching element Q Z .
  • the resonant current from the resonant circuit is supplied to the switching element at the commutation source in the reverse biased direction, during the overlap period, and the resonant current is also supplied to the freewheeling diode in the forward biased direction, the diode being connected with the switching element in inverse-parallel, thereby establishing zero current and zero voltage in the switching element at the commutation source during the overlap period, and the commutation operation is performed under the condition of zero current and zero voltage at the point when the switching element at the commutation source is switched from the ON state to the OFF state.
  • FIG. 5 illustrates a configuration example of the inverter circuit and the resonant circuit according to the present invention
  • FIG. 6 is a timing chart for explaining a driving of the switching elements in the inverter circuit according to the present invention
  • FIG. 7 illustrates the resonant current of the resonant circuit according to the present invention
  • FIG. 8 illustrates the resonant circuit according to the present invention
  • FIG. 9 illustrates conditions for the overlap period in the inverter control and the resonant circuit according to the present invention
  • FIG. 5 illustrates a configuration example of the inverter circuit and the resonant circuit according to the present invention
  • FIG. 6 is a timing chart for explaining a driving of the switching elements in the inverter circuit according to the present invention
  • FIG. 7 illustrates the resonant current of the resonant circuit according to the present invention
  • FIG. 8 illustrates the resonant circuit according to the present invention
  • FIG. 9 illustrates conditions for the overlap period in the inverter control and the re
  • FIG. 10 illustrates the commutation state of the switching elements in the inverter circuit according to the present invention
  • FIG. 11 to FIG. 14 illustrate operations of the inverter control according to the present invention. It is to be noted that in FIG. 11 to FIG. 14 , the state of current flow through the elements and the wiring is represented by light and dark in color, and a conduction state is illustrated being dark in color, and a non-conduction state is illustrated being light in color.
  • the resonant circuit according to the present invention is provided with LC series circuits respectively between the terminals being formed by the current feed ends of the resonant circuit.
  • Each LC series circuit inputs forward current from the switching element at the commutation target, upon commutation between the switching elements in the inverter circuit, generates resonant current, and supplies the resonant current thus generated to the switching element at the commutation source in the reverse biased direction thereof.
  • the inverter circuit 41 as shown in FIG. 5A is made up of a bridge connection of six switching elements Q R , Q S , Q T , Q X , Q Y , and Q Z , and the switching element Q R and the switching element Q X are connected in series, the switching element Q S and the switching element Q Y are connected in series, and the switching element Q T and the switching element Q Z are connected in series.
  • connection point R between the switching element Q R and the switching element Q X is connected via the inductance L m1 , as the R-phase component of the three-phase transformer 51
  • connection point S between the switching element Q S and the switching element Q Y is connected via the inductance L m2 , as the S-phase component of the three-phase transformer 51
  • connection point T between the switching element Q T and the switching element Q Z is connected via the inductance L m3 , as the T-phase component of the three-phase transformer 51.
  • the resonant circuit 71 is provided with three units of resonant circuit, made up of serial connections of the capacitor C L and the reactance L c , and respective ends of the three units of the resonant circuit are connected to between the terminals of three current feed ends.
  • the terminals of the current feed ends are respectively connected to the connection point R between the switching element Q R and the switching element Q X , the connection point S between the switching element Q S and the switching element Q Y , and the connection point T between the switching element Q ST and the switching element Q Z .
  • the resonant circuit 71 inputs forward current of the switching element at the commutation target out of two switching elements for performing the commutation operation, so as to generate resonant current.
  • the resonant circuit 71 supplies in the reverse biased direction, thus generated resonant current to the switching element at the commutation source out of the two switching elements which perform the commutation operation.
  • the resonant circuit 71 inputs the forward current of the switching element Q S at the commutation target to generate resonant current, and supplies thus generated resonant current to the switching element Q R at the commutation source in the reverse biased direction.
  • the resonant circuit 71 is illustrated as a configuration having a delta connection, but it may be configured as a star connection as shown in FIG. 5B .
  • the timing chart as shown in FIG. 6 for explaining the driving of the switching elements in the inverter circuit according to the present invention illustrates gate pulse signals for driving the switching elements Q R , Q S , Q T , Q X , Q Y , and Q Z .
  • the three-phase inverter is taken as an example here, when one cycle of drive angular frequency ⁇ I of the three-phase inverter is assumed as a phase component of 2n, the period when the switching element is set to be the ON state in each phase corresponds to a phase component of (2n/3).
  • an overlap period ⁇ t is provided between two switching elements in the relationship of commutation with each other, for generating resonant current in the resonant circuit, then supplying thus generated resonant current to the switching element at the commutation source, allowing the switching element at the commutation source to perform the commutation operation according to ZCS (zero current switching) and ZVS (zero voltage switching), and then reducing a switching loss at the time of commutation.
  • FIG. 7 illustrates a relationship between the resonant current I CL for the primary current in R phase I R and the overlap period ⁇ t.
  • FIG. 7A illustrates the primary current in R phase I R and the resonant current I CL
  • FIG. 7B illustrates a gate pulse signal G R for the drive control of the switching element Q R
  • FIG. 7C illustrates a gate pulse signal G S for the drive control of the switching element Q S .
  • FIG. 8 illustrates a configuration example of the resonant circuit.
  • the resonant current I CL generated by the resonant circuit made up of the capacitor C L and the reactor L c being connected in series is expressed by the following formula (2), when equivalent capacitance C e and equivalent reactor L e are used;
  • I CL I max ⁇ sin ⁇ n ⁇ t
  • the maximum value I max of the resonant current and angular frequency ⁇ n are expressed respectively by the following formulas (3) and (4):
  • I max V RS / L e / C e 1 / 2
  • n 1 / L e ⁇ C e 1 / 2
  • V RS , L e , and C e respectively represent the voltage, equivalent reactor, equivalent capacitance between the terminal R and the terminal S of the resonant circuit as shown in FIG. 8A.
  • FIG. 8B illustrates an equivalent circuit of the resonant circuit when commutation is performed from R phase to S phase.
  • the L e and C e since the I CT current of the T-phase does not flow, it is possible to treat the L e and C e as a join impedance circuit viewed from between the phase R and the phase S.
  • the maximum range of the overlap period ⁇ t corresponds to a half cycle component n of the resonant current.
  • the overlap period ⁇ t is set to be within the half cycle n of the resonant current.
  • FIG. 9 illustrates conditions for setting the overlap period ⁇ t, and the capacitor C L and the reactor L C of the resonant circuit.
  • FIG. 9A and 9B illustrate the timing of the gate pulse signals of the switching elements Q R and Q X in a relationship being connected in the bridge configuration
  • FIG. 9C and 9D illustrate the timing of the gate pulse signals of the switching elements Q S and Q Y in a relationship being connected in the bridge configuration
  • FIG. 9G and 9H illustrate the timing of the gate pulse signals of the switching elements Q T and Q Z in a relationship being connected in the bridge configuration.
  • FIG. 9E illustrates the resonant current I CL of the resonant circuit which is connected between the switching element Q R and the switching element Q S
  • FIG. 9F illustrates the forward current I QR which flows in the switching element Q R .
  • FIG. 9 illustrates these conditions (c), (d), and (e) using the reference marks; A, B, and C, respectively.
  • each extended period is shorter than ⁇ /6.
  • the switching element Q S is set to be the ON state
  • the switching element Q X is set to be the ON state after the lapse of n/3, and next resonant current starts to flow. Therefore, the resonant current I CL which is generated by turning ON the switching element Q S is required to be terminated within n/3.
  • This example indicates the commutation operation between the switching element Q R and the switching element Q S during the operation modes 4, 5, and 6 as shown in FIG. 6 .
  • the switching element Q R is assumed as the switching element at the commutation source
  • the switching element Q S is assumed as the switching element at the commutation target.
  • the current source inverter controls the commutation operation to generate the overlap period during when both the switching element Q R at the commutation source and the switching element Q S at the commutation target are set to be the ON state, and allows forward current to flow into the resonant circuit 71, the current flowing when the switching element Q S at the commutation target becomes the ON state, thereby generating resonant current in the resonant circuit in sync with the commutation operation, and supplying thus generated resonant current into the switching element Q R at the commutation source.
  • the commutation period during when both the switching element Q R at the commutation source and the switching element Q S at the commutation target are set to be the ON state is assumed as the time from the rising edge of the gate pulse signal G S ( FIG. 10B ) of the switching element Q S , until the falling edge of the gate pulse signal G R ( FIG. 10A ) of the switching element Q R , and the time when the gate pulse signal G R ( FIG. 10A ) of the switching element Q R is in the ON state and the time when the gate pulse signal G S ( FIG. 10B ) of the switching element Q S is in the ON state overlap one another in time, thereby generating the overlap period.
  • the switching element Q S is turned ON before the switching element Q R is switched from the ON state to the OFF state, and within the overlap period ⁇ t (operation mode 5), both the switching element Q R and the switching element Q S are in the ON state concurrently.
  • the period A is associated with the operation mode 4
  • the period B is associated with a part of the operation mode 5
  • the period C is associated with the remaining part of the operation mode 5
  • the period D is associated with the operation mode 6.
  • the switching element Q R is in the ON state, and the current I QR flows in the switching element Q R , and the current I QS ( FIG. 10C ) of the switching element Q S does not flow.
  • FIG. 11 illustrates the operating state and the current state of the switching elements during the period A.
  • the current I QR of the switching element Q R is supplied to the three-phase transformer 51 as the primary current in R phase I R , and returns via the switching element Q Z .
  • the switching element Q S is set to be the ON state, and the current I QS starts flowing in the switching element Q S .
  • the current I QS of the switching element Q S increases by the time constant according to the inductance L m2 and L C , and therefore, at the time when the switching element Q S is turned to the ON state, ZCS (zero current switching) is performed ( FIG. 10D ).
  • FIG. 12 illustrates the operating state and the current state of the switching elements during the period B.
  • the current in the switching element Q S is introduced into the resonant circuit 71 via the terminal S, and the resonant circuit unit made up of a series connection between the capacitor C L and the reactor L C generates the resonant current I CL .
  • a part of the resonant current I CL is supplied to the three-phase transformer 51 as the primary current in R phase, and a part of the remaining current is supplied to the switching element Q R at the commutation source in the reverse biased direction.
  • the forward current in the switching element Q R is canceled by the resonant current, and the primary current I R according to a part of the resonant current, and primary current I S according to the switching element Q S are supplied to the three-phase transformer 51, and return via the switching element Q Z .
  • the current I QR in the switching element Q R becomes zero current.
  • a surplus of the resonant current flows into the freewheeling diode D R that is connected to the switching element Q R in parallel.
  • the number 2 each enclosed within a circle in FIG. 10E and FIG. 10G indicates current components in the relationship being associated with one another.
  • the drain-to-source voltage of the switching element Q R is kept to be zero voltage ( FIG. 10F ).
  • the overlap period is terminated at the falling edge of the gate pulse signal G R of the switching element Q R at the commutation source.
  • the switching element Q R at the commutation source When the switching element Q R at the commutation source is turned OFF, the current I QR flowing in the switching element Q R is kept to be in the state of zero current, by the OFF state of the switching element Q R at the commutation source, in succession to the zero current state caused by the resonant current. Therefore, the switching element Q R at the commutation source achieves the ZCS (zero current switching).
  • the resonant current flows into the freewheeling diode D R of the switching element Q R , thereby achieving ZVS (zero voltage switching) in the switching element Q R at the commutation source.
  • This period C is terminated at the time when the resonant current becomes zero.
  • FIG. 13 illustrates the operating state and the current state of the switching elements during the period C.
  • the resonant current I LC cancels the forward current in the switching element Q R to establish zero current, and flows into the freewheeling diode D R to establish zero voltage.
  • the primary current I R according to a part of the resonant current, and the primary current I S according to the switching element Q S are supplied to the three-phase transformer 51, and return via the switching element Q Z .
  • FIG. 14 illustrates the operating state and the current state of the switching elements during the period D.
  • the resonant current I LC stops, and the primary current I S according to the switching element Q S is supplied to the three-phase transformer 51, and returns to the switching element Q Z .
  • the resonant current of the resonant circuit is supplied to the switching element at the commutation source in the reverse biased direction, and supplied in the forward biased direction to the freewheeling diode which is connected with the switching element in inverse-parallel, thereby rendering the switching element at the commutation source to be zero current and zero voltage, and performing the commutation operation under the condition of zero current and zero voltage at the time when the switching element at the commutation source is switched from the ON state to the OFF state.
  • the current source inverter of the present invention may be applied to a power source for supplying electric power to a plasma generator.

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EP12869041.9A 2012-02-23 2012-02-23 Dispositif d'inversion de source de courant, et procédé de commande de dispositif d'inversion de source de courant Active EP2677652B1 (fr)

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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE12884309T1 (de) * 2012-09-05 2015-09-17 Kyosan Electric Mfg. Co., Ltd. Gleichstromversorgungsvorrichtung und steuerungsverfahren für die gleichstromversorgungsvorrichtung
DE102012216008A1 (de) * 2012-09-10 2014-03-13 Robert Bosch Gmbh Betriebszustandsschaltung für Wechselrichter und Verfahren zum Einstellen von Betriebszuständen eines Wechselrichters
JP5679239B1 (ja) 2013-08-27 2015-03-04 株式会社京三製作所 単相インバータ
JP5729732B2 (ja) * 2013-09-27 2015-06-03 株式会社京三製作所 直流電源装置、直流電源装置の制御方法
EP3054750B1 (fr) * 2013-10-04 2019-05-01 Toshiba Mitsubishi-Electric Industrial Systems Corporation Dispositif d'alimentation électrique
US10892140B2 (en) 2018-07-27 2021-01-12 Eagle Harbor Technologies, Inc. Nanosecond pulser bias compensation
US10978955B2 (en) 2014-02-28 2021-04-13 Eagle Harbor Technologies, Inc. Nanosecond pulser bias compensation
US9960763B2 (en) 2013-11-14 2018-05-01 Eagle Harbor Technologies, Inc. High voltage nanosecond pulser
US10020800B2 (en) 2013-11-14 2018-07-10 Eagle Harbor Technologies, Inc. High voltage nanosecond pulser with variable pulse width and pulse repetition frequency
US11539352B2 (en) 2013-11-14 2022-12-27 Eagle Harbor Technologies, Inc. Transformer resonant converter
US10483089B2 (en) 2014-02-28 2019-11-19 Eagle Harbor Technologies, Inc. High voltage resistive output stage circuit
EP2937976B1 (fr) * 2014-04-22 2017-11-22 Skf Magnetic Mechatronics Dispositif de commande de palier magnétique électronique avec dispositif de compensation de puissance réactive automatique
CN103973150B (zh) * 2014-05-21 2016-11-09 重庆大学 电流型逆变电源
JP6424533B2 (ja) * 2014-09-17 2018-11-21 株式会社リコー 電圧共振型インバータ装置及びその制御方法と表面改質装置
CN104485825B (zh) * 2014-11-28 2017-02-22 山东华天电气有限公司 单相可编程电流源装置及其控制方法
US9780639B2 (en) 2015-01-19 2017-10-03 Infineon Technologies Austria Ag Protection from hard commutation events at power switches
US9780636B2 (en) 2015-01-19 2017-10-03 Infineon Technologies Austria Ag Protection from hard commutation events at power switches
JP6501064B2 (ja) * 2015-05-12 2019-04-17 富士電機株式会社 誘導加熱装置
CN106329977B (zh) * 2015-07-03 2018-10-09 台达电子工业股份有限公司 逆变电路的控制方法
WO2017210279A1 (fr) * 2016-05-31 2017-12-07 The Regents Of The University Of Colorado, A Body Corporate Câble intelligent et procédés associés
US11430635B2 (en) 2018-07-27 2022-08-30 Eagle Harbor Technologies, Inc. Precise plasma control system
US11004660B2 (en) 2018-11-30 2021-05-11 Eagle Harbor Technologies, Inc. Variable output impedance RF generator
US10177681B2 (en) * 2016-06-24 2019-01-08 Infineon Technologies Austria Ag Power converter including an autotransformer and power conversion method
US10135351B2 (en) 2016-08-11 2018-11-20 MohammadReza Haji Moradi Javarsiani Circuit and method for AC-to-AC voltage conversion
CN115378264A (zh) 2017-02-07 2022-11-22 鹰港科技有限公司 变压器谐振转换器
US11005384B2 (en) * 2017-04-03 2021-05-11 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion device
JP6902962B2 (ja) * 2017-08-22 2021-07-14 ダイヤモンド電機株式会社 コンバータ
KR102208429B1 (ko) 2017-08-25 2021-01-29 이글 하버 테크놀로지스, 인코포레이티드 나노초 펄스를 이용한 임의의 파형 발생
EP3525348B1 (fr) * 2018-02-08 2021-08-25 General Electric Technology GmbH Appareil de commutation
US11532457B2 (en) 2018-07-27 2022-12-20 Eagle Harbor Technologies, Inc. Precise plasma control system
US11222767B2 (en) 2018-07-27 2022-01-11 Eagle Harbor Technologies, Inc. Nanosecond pulser bias compensation
US10607814B2 (en) * 2018-08-10 2020-03-31 Eagle Harbor Technologies, Inc. High voltage switch with isolated power
US11302518B2 (en) 2018-07-27 2022-04-12 Eagle Harbor Technologies, Inc. Efficient energy recovery in a nanosecond pulser circuit
KR20230025034A (ko) * 2018-08-10 2023-02-21 이글 하버 테크놀로지스, 인코포레이티드 RF 플라즈마 반응기용 플라즈마 시스(sheath) 제어
WO2020110225A1 (fr) 2018-11-28 2020-06-04 東芝三菱電機産業システム株式会社 Dispositif de conversion de puissance
TW202308306A (zh) 2019-01-08 2023-02-16 美商鷹港科技股份有限公司 產生高壓脈波之方法
TWI778449B (zh) 2019-11-15 2022-09-21 美商鷹港科技股份有限公司 高電壓脈衝電路
CN110927451B (zh) * 2019-11-28 2021-08-13 中电科仪器仪表有限公司 一种电磁频谱监测接收机分布式信号融合方法
WO2021134000A1 (fr) 2019-12-24 2021-07-01 Eagle Harbor Technologies, Inc. Isolation rf de générateur d'impulsions nanosecondes pour systèmes à plasma
JP7372178B2 (ja) 2020-03-06 2023-10-31 新電元工業株式会社 電源装置
CN113691112B (zh) * 2021-08-12 2023-02-28 苏州汇川控制技术有限公司 三相逆变器及其过流保护方法和变频器
CN116526874B (zh) * 2023-07-04 2023-09-08 湖南大学 一种零电压导通的lc谐振电源控制电路及其控制方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020159281A1 (en) * 2001-04-26 2002-10-31 Honda Giken Kogyo Kabushiki Kaisha Resonant inverter circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2523231B2 (ja) * 1991-04-17 1996-08-07 東洋電機製造株式会社 共振形ｐｗｍインバ―タ
US5280421A (en) * 1992-06-17 1994-01-18 General Electric Company Current regulator for a four-legged three-phase inverter
JPH06284749A (ja) * 1993-03-29 1994-10-07 Nippon Electric Ind Co Ltd スナバレス・インバータ
JP3328758B2 (ja) 1995-04-25 2002-09-30 三井造船株式会社 電流形インバータの転流制御方法および装置
JP3815050B2 (ja) * 1998-05-08 2006-08-30 株式会社デンソー 共振形インバータ装置
JP4097998B2 (ja) 2002-06-14 2008-06-11 本田技研工業株式会社 共振形インバータ
CN2710247Y (zh) * 2004-01-02 2005-07-13 英属开曼群岛凹凸微系国际有限公司 用于非线性负载的高效率转换器电路
CN101217260A (zh) * 2008-01-18 2008-07-09 张振武 无速度传感器电动机转差率控制数字智能调速方法及系统
WO2010073635A1 (fr) 2008-12-26 2010-07-01 ダイキン工業株式会社 Convertisseur de puissance

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020159281A1 (en) * 2001-04-26 2002-10-31 Honda Giken Kogyo Kabushiki Kaisha Resonant inverter circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2013125004A1 *

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US8730700B2 (en) 2014-05-20
CN103477550B (zh) 2015-06-17
JPWO2013125004A1 (ja) 2015-05-21
US20140009969A1 (en) 2014-01-09
TW201336221A (zh) 2013-09-01
CN103477550A (zh) 2013-12-25
KR101441271B1 (ko) 2014-09-17
TWI431920B (zh) 2014-03-21
EP2677652A4 (fr) 2015-01-21
JP5207568B1 (ja) 2013-06-12
PL2677652T3 (pl) 2017-04-28
WO2013125004A1 (fr) 2013-08-29
EP2677652B1 (fr) 2016-11-16
KR20140010978A (ko) 2014-01-27

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