EP2672508A4 - Verfahren zur herstellung eines soi-wafers - Google Patents

Verfahren zur herstellung eines soi-wafers

Info

Publication number
EP2672508A4
EP2672508A4 EP12742138.6A EP12742138A EP2672508A4 EP 2672508 A4 EP2672508 A4 EP 2672508A4 EP 12742138 A EP12742138 A EP 12742138A EP 2672508 A4 EP2672508 A4 EP 2672508A4
Authority
EP
European Patent Office
Prior art keywords
soi wafer
manufacturing soi
manufacturing
wafer
soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP12742138.6A
Other languages
English (en)
French (fr)
Other versions
EP2672508B1 (de
EP2672508A1 (de
Inventor
Shoji Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of EP2672508A1 publication Critical patent/EP2672508A1/de
Publication of EP2672508A4 publication Critical patent/EP2672508A4/de
Application granted granted Critical
Publication of EP2672508B1 publication Critical patent/EP2672508B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
EP12742138.6A 2011-02-02 2012-01-24 Verfahren zur herstellung eines soi-wafers Active EP2672508B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011020706A JP5819614B2 (ja) 2011-02-02 2011-02-02 Ｓｏｉウェーハの製造方法
PCT/JP2012/051412 WO2012105367A1 (ja) 2011-02-02 2012-01-24 Ｓｏｉウェーハの製造方法

Publications (3)

Publication Number Publication Date
EP2672508A1 EP2672508A1 (de) 2013-12-11
EP2672508A4 true EP2672508A4 (de) 2014-07-02
EP2672508B1 EP2672508B1 (de) 2019-06-05

Family

ID=46602586

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12742138.6A Active EP2672508B1 (de) 2011-02-02 2012-01-24 Verfahren zur herstellung eines soi-wafers

Country Status (7)

Country Link
US (1) US20130309842A1 (de)
EP (1) EP2672508B1 (de)
JP (1) JP5819614B2 (de)
KR (1) KR20140005948A (de)
CN (1) CN103339710A (de)
TW (1) TWI570805B (de)
WO (1) WO2012105367A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140107B (zh) * 2015-08-25 2019-03-29 上海新傲科技股份有限公司 带有电荷陷阱和绝缘埋层衬底的制备方法
KR20170002110U (ko) 2015-12-07 2017-06-15 박찬규 휴대폰용 보호 케이스
CN111682108A (zh) * 2020-02-29 2020-09-18 浙江集迈科微电子有限公司 一种三维的电感制作方法
CN112736167B (zh) * 2020-12-29 2022-02-01 济南晶正电子科技有限公司 一种复合衬底、复合薄膜及其制备方法，及射频滤波器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090269906A1 (en) * 2008-04-24 2009-10-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US20100248444A1 (en) * 2009-03-24 2010-09-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077826B2 (ja) * 1983-08-25 1995-01-30 忠弘 大見 半導体集積回路
JPS60254609A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd 半導体装置の製造方法
JP2542609B2 (ja) * 1987-03-16 1996-10-09 富士通株式会社 半導体装置の製造方法
JPH01270311A (ja) * 1988-04-22 1989-10-27 Seiko Epson Corp 薄膜形成方法
JPH08250421A (ja) * 1995-03-10 1996-09-27 Canon Inc 半導体基板の製造方法および半導体基板
US6037199A (en) * 1999-08-16 2000-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. SOI device for DRAM cells beyond gigabit generation and method for making the same
JP4103447B2 (ja) * 2002-04-30 2008-06-18 株式会社Ｉｈｉ 大面積単結晶シリコン基板の製造方法
JP3974542B2 (ja) * 2003-03-17 2007-09-12 株式会社東芝 半導体基板の製造方法および半導体装置の製造方法
KR101155176B1 (ko) * 2005-07-12 2012-06-11 삼성전자주식회사 방향성이 조절된 단결정 와이어 및 이를 적용한트랜지스터의 제조방법
TWI260747B (en) * 2005-08-24 2006-08-21 Quanta Display Inc A method for forming a thin film transistor, and a method for transforming an amorphous layer into a poly crystal layer of a single crystal layer
KR100681262B1 (ko) * 2006-01-24 2007-02-09 삼성전자주식회사 스택형 반도체 장치의 제조 방법
US8193071B2 (en) * 2008-03-11 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP5414203B2 (ja) * 2008-05-23 2014-02-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090269906A1 (en) * 2008-04-24 2009-10-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US20100248444A1 (en) * 2009-03-24 2010-09-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DONOVAN E P ET AL: "Heat of crystallization and melting point of amorphous silicon", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS, US, vol. 42, no. 8, 15 April 1983 (1983-04-15), pages 698 - 700, XP002475236, ISSN: 0003-6951, DOI: 10.1063/1.94077 *
See also references of WO2012105367A1 *

Also Published As

Publication number Publication date
EP2672508B1 (de) 2019-06-05
US20130309842A1 (en) 2013-11-21
CN103339710A (zh) 2013-10-02
TWI570805B (zh) 2017-02-11
TW201246370A (en) 2012-11-16
JP2012160648A (ja) 2012-08-23
EP2672508A1 (de) 2013-12-11
JP5819614B2 (ja) 2015-11-24
WO2012105367A1 (ja) 2012-08-09
KR20140005948A (ko) 2014-01-15

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