EP2593963A1 - Composant semi-conducteur, substrat et procédé de fabrication d'une succession de couches semi-conductrices - Google Patents

Composant semi-conducteur, substrat et procédé de fabrication d'une succession de couches semi-conductrices

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Publication number
EP2593963A1
EP2593963A1 EP11745713.5A EP11745713A EP2593963A1 EP 2593963 A1 EP2593963 A1 EP 2593963A1 EP 11745713 A EP11745713 A EP 11745713A EP 2593963 A1 EP2593963 A1 EP 2593963A1
Authority
EP
European Patent Office
Prior art keywords
substrate
semiconductor
impurities
layer sequence
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11745713.5A
Other languages
German (de)
English (en)
Inventor
Peter Stauss
Patrick Rode
Philipp Drechsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2593963A1 publication Critical patent/EP2593963A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403AIII-nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body

Definitions

  • the present application relates to a semiconductor device, a substrate for the production of a semiconductor device and a method for producing a
  • One object is to specify a semiconductor component which can be produced in a simplified and reliable manner. Furthermore, a substrate and a method are to be specified with which semiconductor layers can be deposited homogeneously and reliably.
  • a semiconductor device includes a semiconductor body mounted on a nitride
  • Compound semiconductor material based and a substrate on which the semiconductor body is disposed on. In the substrate targeted impurities are formed.
  • the semiconductor layer sequence is deposited on a substrate in an embodiment, wherein in the substrate targeted impurities are formed.
  • the semiconductor layer sequence can be separated
  • nitridic compound semiconductors in the present context means that the active epitaxial layer sequence or at least one layer thereof is a nitride Ii / V compound semiconductor material, preferably
  • this material need not necessarily have a mathematically exact composition according to the above formula. Rather, it may have one or more dopants as well as additional ingredients that are the characteristic
  • An impurity is understood to mean that the substrate is at least partially interspersed with impurities from one of a base material of the substrate Material.
  • the foreign atoms can, for example, at lattice sites of the substrate crystal or between
  • Targeted contamination in this context means, in particular, that the impurities are introduced in a defined manner in the production of the substrate, for example by targeted provision of the material for the impurities.
  • a substrate which is optimized for the lowest possible contamination during production and contains only residues of a foreign material that are not completely avoidable due to production is not considered to be contaminated in a targeted manner.
  • the impurities are in particular to increase the upper yield point of the substrate
  • the upper yield point thus provides a transition from one elastic region to one
  • the upper yield point can be increased so that the in the deposition of
  • Bracing leads to no or at least no significant plastic deformation.
  • the deposition can take place in the elastic region of the substrate.
  • the contaminants are formed such that the substrate acts on the substrate
  • Optoelectronic semiconductor devices can be increased by the use of targeted contaminated substrates.
  • the thickness of a substrate with intentionally introduced impurities to a substrate without such impurities be reduced without the upper yield point is exceeded.
  • the material requirements can be reduced and the production costs are reduced.
  • the impurities especially with regard to the material and the concentration, are expediently designed such that they increase the upper yield strength of the substrate.
  • the impurities are formed at a concentration of between 1 * 10 14 cm -3 and 1 * 10 cm m of the substrate.
  • Impurities can be electrically active (ie the
  • the impurities contain carbon, nitrogen, boron or oxygen. Furthermore, the
  • Contaminants may be formed with at least two of these materials, for example with oxygen and carbon, or with oxygen and boron.
  • oxygen and carbon or with oxygen and boron.
  • concentration of impurities is
  • the concentration of impurities is preferably between 1 * 10 14 cm -3 and
  • the deposition of the nitridic substance takes place, preferably epitaxially
  • Compound semiconductor material preferably such that the semiconductor layer sequence is compressively clamped at a deposition temperature with respect to the substrate (or pressure-spanned referred to). That is, that
  • Compound semiconductor material assumes a lattice constant that is smaller in the lateral plane than an intrinsic lattice constant of the compound semiconductor material. Upon cooling of the semiconductor layer sequence, the risk is reduced that the difference of the thermal
  • the strain at room temperature is at most 10%, more preferably at most 5%, most preferably at most 1%.
  • the substrate has a silicon surface that acts as a deposition plane
  • the substrate can be used in particular as a
  • Silicon bulk substrate or as an SOI Silicon On
  • Insulator substrate be formed.
  • the silicon surface is a (111) plane of the substrate.
  • Orientation is distinguished from other orientations by an increased upper yield point. Furthermore, due to its hexagonal symmetry, a (111) plane is particularly suitable for the deposition of nitridic
  • Semiconductor device preferably forms a functional region of the semiconductor device. In other words, the relevant for the functionality of the semiconductor device area outside the substrate is formed. Compared to a silicon-based semiconductor device in which the devices are typically at least partially embedded in the device
  • the semiconductor body has an active region which is provided for generating and / or for receiving radiation.
  • the decisive for the efficiency of the device in its operation active area is thus formed outside the substrate.
  • Semiconductor device as a, preferably active,
  • a transistor such as a high electron mobility transistor (HEMT) or as a bipolar transistor with
  • HBT Heterojunction bipolar transistor
  • Compound semiconductor material is suitable.
  • Such a substrate can also be used for the deposition of other III-V compound semiconductor materials, for example on the basis of phosphidic
  • On phosphidic compound semiconductors in this context means that the semiconductor body, in particular the active region preferably Al n Ga m I Ni n - m P, wherein 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m ⁇ 1,
  • composition according to the above formula may contain one or more dopants as well as additional
  • the above formula includes only the essential constituents of the crystal lattice (Al, Ga, I n, P), even if these may be partially replaced by small amounts of other substances.
  • the substrate can be at least partially removed or thinned, for example mechanically, chemically or by means of coherent radiation.
  • the semiconductor layer sequence can be fixed to a carrier, which in particular mechanically stabilizes the semiconductor layer sequence.
  • a semiconductor device in which a growth substrate is removed is also referred to as a thin-film semiconductor device.
  • a light-emitting diode chip may be formed as a thin-film semiconductor component and in particular by at least one of the following characteristic
  • Characteristics distinguish: on a first end facing a carrier element
  • Epitaxial layer sequence is applied or formed a reflective layer that at least a portion of the generated in the epitaxial layer sequence
  • the epitaxial layer sequence reflects electromagnetic radiation back into them; the epitaxial layer sequence has a thickness in the range of 20 microns or less, more preferably in the range of 10 microns;
  • the epitaxial layer sequence contains at least one
  • Semiconductor layer having at least one surface which has a blending structure which, in the ideal case, results in an approximately ergodic distribution of the light in the epitaxial epitaxial layer sequence, i. it has as ergodically stochastic scattering behavior as possible.
  • a thin-film light-emitting diode chip is, to a good approximation, a Lambert surface radiator and is therefore particularly well suited for use in a headlight.
  • the described method and the described substrate are particularly suitable for the production of the semiconductor device described.
  • Figure 1 shows a first embodiment of a
  • FIGS. 2A to 2D show a first exemplary embodiment of a method for producing a semiconductor component on the basis of intermediate steps respectively shown in a schematic sectional view
  • FIGS. 3A to 3D show a second exemplary embodiment of a method for producing a semiconductor component on the basis of intermediate steps respectively shown in a schematic sectional view
  • Figure 1 is an embodiment of a
  • Semiconductor device 1 shown which is exemplarily formed as a thin-film LED chip.
  • the semiconductor component 1 has a semiconductor body 2 with a semiconductor layer sequence.
  • Semiconductor layer sequence which forms the semiconductor body is preferably epitaxially deposited on a substrate 3, for example by means of MOVPE or MBE.
  • the substrate 3 impurities 4 are formed, which are arranged on lattice sites or between adjacent lattice sites in the crystal structure of the substrate.
  • a substrate in particular, a volume silicon substrate is suitable.
  • SOI substrate it is also possible to use an SOI substrate.
  • the substrate has a
  • Silicon Semiconductor body facing surface in (111) orientation. In this orientation, silicon has an increased upper yield point. Silicon is further characterized by a high thermal conductivity. Furthermore, silicon substrates are in particular compared to others
  • Compound semiconductor material such as sapphire, silicon carbide or gallium nitride over a large area and inexpensive available.
  • the impurities 4 are preferably with a
  • the impurities may be electrically active or electrically inactive.
  • the impurities contain carbon, nitrogen, boron or oxygen.
  • the concentration of impurities is preferably between and including 1 * 10 17 cm -3
  • the concentration of impurities is preferably between 1 * 10 14 cm -3 and
  • Contaminants may be formed with at least two of these materials, for example with oxygen and carbon, or with oxygen and boron.
  • the substrate withstands a strain of at least 0.5 GPa, preferably of at least 1.0 GPa, without any plastic deformation occurring.
  • the semiconductor body 2 has an intermediate region 25 which adjoins the substrate 3. On the substrate
  • Component region 21 is formed.
  • the semiconductor layers of the semiconductor body 2 are based in each case on Al n Ga m In n m - n with 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and
  • the device region 21 has one for the production of
  • Semiconductor layer 24 is arranged.
  • charge carriers can be supplied from a first contact 91 and a second contact 92 different sides are injected into the active region 23 and recombine there under the emission of radiation.
  • the device region 21 preferably has a thickness of between 2 ym inclusive and 8 ym inclusive, more preferably between 4 ym inclusive and
  • Semiconductor device 1 but can also larger or
  • Substrate 3 may be between the active region 21 and the
  • Substrate 3, in particular on the intermediate region 25 facing side of the device region 21 may be formed a Bragg mirror which reflects in operation in the direction of the substrate radiated radiation.
  • the semiconductor layers of the intermediate region 25 serve primarily to increase the quality of the
  • the intermediate region 25 has a nucleation
  • Buffer layer 26 a transition layer 27 and a
  • Bracing region 28 which are sequentially deposited on the substrate.
  • Buffer layer 26 is formed on the basis of A1N. This layer serves for embossing the substrate 3 and has a thickness between 50 nm and 300 nm, for example 200 nm.
  • the downstream transition layer is based on AlGaN and is to, for example, gradual or continuous, increase the gallium content provided.
  • the bracing region 28 is for forming a compressive strain at the deposition temperature
  • a GaN layer is suitable, into which one or more AlGaN layers, for example 2 to 3 AlGaN layers
  • the thickness of the bracing region is preferably between 2 ⁇ m and 3 ⁇ m, for example 2.5 ⁇ m.
  • the strain is preferably at most 10%, more preferably at most 5%, most preferably at most 1%.
  • the intermediate region 25 is largely independent of the subsequent component region and can therefore also be used for other optoelectronic or electronic components
  • the semiconductor device of the present disclosure is a semiconductor device of the present disclosure.
  • described embodiment may also be designed as an electronic semiconductor device, such as a semiconductor device for high frequency technology or for power electronics.
  • a semiconductor device for high frequency technology or for power electronics for example, that can
  • the functional layers are thus formed outside the substrate 3.
  • the impurities 4 can therefore be introduced into the substrate to increase the upper yield point and thus bring about improved homogeneity of the deposition of the semiconductor layers, without the impurities having a negative influence on the functionality of the semiconductor components.
  • FIG. 2A to 2D Semiconductor devices is further processed, is shown in Figures 2A to 2D.
  • the method is described by way of example with reference to the production of a thin-film light-emitting diode chip, wherein for the sake of simplicity, only the region of the semiconductor layer sequence is shown, from which a semiconductor body emerges for a semiconductor component.
  • a substrate 3 which is specifically provided with impurities 4, provided.
  • the substrate can be produced for example by means of a Czochralski method or by means of a floating zone method.
  • a substrate 3 produced in the floating zone process can be distinguished by improved crystal quality.
  • the material provided for the formation of the impurity can be offered in the production so that it in the
  • Crystal of the substrate is installed on the lattice sites or between lattice sites.
  • a semiconductor layer sequence 20 is epitaxially deposited with an intermediate region 25 and a device region 21, these regions as in
  • the impurities 4 are preferably introduced with a concentration such that the deposition of the
  • the substrate holds by means of the impurities 4 during the deposition, ie at temperatures of about
  • connecting layer 6 for example, a solder or an electrically conductive adhesive layer on a
  • the support 8 does not have to satisfy the high crystalline properties of a growth substrate and can be chosen for other properties, for example in the
  • a semiconductor material such as silicon, germanium or gallium arsenide, or a suitable
  • a mirror layer 7 is formed between the carrier 8 and the semiconductor layer sequence 2.
  • the mirror layer is provided for the reflection of the radiation generated during operation in the active region 23.
  • Mirror layer preferably contains a metal with a high reflectivity for those generated in the active region
  • Radiation or a metallic alloy In the visible spectral range, for example, aluminum, silver, rhodium, palladium, nickel or chromium is suitable.
  • the carrier 8 serves for the mechanical stabilization of
  • the substrate 3 is no longer necessary for this purpose and can be removed, for example wet-chemically (Figure 2C).
  • Figure 2C wet-chemically
  • a surface of the semiconductor layer sequence facing away from the carrier 8 is provided with a structuring 29, for example a roughening.
  • Radiation can be increased in this way.
  • material of the intermediate region 25 is partially removed.
  • Transition layer 27 are completely removed, so that the structuring 29 can be formed in the bracing 29.
  • a first contact 91 and a second contact 92 are formed, for example by means of vapor deposition or sputtering.
  • One Completed thin-film semiconductor device is shown in Figure 2D.
  • Semiconductor layer sequence 20 itself can take place as described in connection with FIG. 2A.
  • Recesses 55 are formed facing away from each other, extending through the active region 23 into the first
  • Semiconductor layer 22 extend into it.
  • the first semiconductor layer 22 is electrically contacted with a first connection layer 51.
  • the second semiconductor layer 24 is provided with a second
  • Terminal layer 52 contacted electrically.
  • Connecting layer extends partially between the
  • the second connection layer 32 is in operation
  • Connection layer is particularly suitable for one of
  • connection layers 51, 52 can be applied by means of vapor deposition or sputtering.
  • the first insulation layer extends in regions between the first connection layer 51 and the second connection layer 52, so that these layers are electrically insulated from one another.
  • an oxide such as silicon oxide or a nitride, such as silicon nitride, is suitable for the insulating layer.
  • a carrier 8 is fixed by means of a bonding layer 6.
  • Connecting layer may be as described in connection with the first embodiment described in Figures 2A to 2D.
  • the substrate 3 As shown in Fig. 3C, the substrate 3, the
  • a radiation exit surface 200 of the semiconductor body 2 facing away from the carrier 8 is provided with a structuring 29 for increasing the coupling-out efficiency. This can be done before or after the exposure of the second connection layer 52.
  • a first contact 91 which is electrically conductively connected to the first semiconductor layer 22 via the first connection layer 51
  • a second contact 92 which is electrically conductively connected to the second semiconductor layer 24 via the second connection layer 52, is formed.
  • the second contact 92 is in the lateral direction of the
  • the radiation exit surface 200 is thus free of external electrical contact. The emerging from the radiation exit surface
  • Radiation power can be increased.
  • the contacts 91, 92 are arranged on different sides of the carrier 8.
  • contacts can also be arranged on the same side.
  • FIG. 4 shows results of measurements of the curvature C (in km -1 ) as a function of the deposition time t (in s) for
  • Curves 401 and 402 show the shape of the curvature C for two silicon substrates produced by the floating zone method, which differ in the concentration of impurities.
  • the curve 302 is a
  • Pollution is characterized by nitrogen.
  • concentration of the nitrogen impurity is about 10 14 cm -3 .
  • a curve 403 refers to a substrate deposited by the Czochralski method with an oxygen impurity concentration of about 10 17 cm -3 .
  • the curve 403 shows in the range between 4500 s and 9000 s a largely linear course with a substantially constant slope.
  • the slope suddenly increases by more than 7000 s.
  • the curvature can be reduced so that the deposition on the substrates in the lateral direction can be particularly homogeneous.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne un composant semi-conducteur (1) comportant un corps semi-conducteur (2) à base d'un matériau semi-conducteur de liaison au nitrure et un substrat (3) sur lequel est disposé le corps semi-conducteur. Des impuretés sont formées de manière ciblée dans le substrat. L'invention concerne en outre un substrat et un procédé de fabrication d'une succession (20) de couches semi-conductrices pour un composant semi-conducteur (1).
EP11745713.5A 2010-07-15 2011-07-07 Composant semi-conducteur, substrat et procédé de fabrication d'une succession de couches semi-conductrices Withdrawn EP2593963A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010027411A DE102010027411A1 (de) 2010-07-15 2010-07-15 Halbleiterbauelement, Substrat und Verfahren zur Herstellung einer Halbleiterschichtenfolge
PCT/EP2011/061523 WO2012007350A1 (fr) 2010-07-15 2011-07-07 Composant semi-conducteur, substrat et procédé de fabrication d'une succession de couches semi-conductrices

Publications (1)

Publication Number Publication Date
EP2593963A1 true EP2593963A1 (fr) 2013-05-22

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EP11745713.5A Withdrawn EP2593963A1 (fr) 2010-07-15 2011-07-07 Composant semi-conducteur, substrat et procédé de fabrication d'une succession de couches semi-conductrices

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Country Link
US (1) US20130200432A1 (fr)
EP (1) EP2593963A1 (fr)
KR (1) KR20130044324A (fr)
CN (1) CN103003917A (fr)
DE (1) DE102010027411A1 (fr)
TW (1) TW201205647A (fr)
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CN103003917A (zh) 2013-03-27
US20130200432A1 (en) 2013-08-08
TW201205647A (en) 2012-02-01
KR20130044324A (ko) 2013-05-02
WO2012007350A1 (fr) 2012-01-19

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