EP2286470A1 - Composant émetteur de rayonnement et procédé de fabrication d'un composant émetteur de rayonnement - Google Patents

Composant émetteur de rayonnement et procédé de fabrication d'un composant émetteur de rayonnement

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Publication number
EP2286470A1
EP2286470A1 EP09765426A EP09765426A EP2286470A1 EP 2286470 A1 EP2286470 A1 EP 2286470A1 EP 09765426 A EP09765426 A EP 09765426A EP 09765426 A EP09765426 A EP 09765426A EP 2286470 A1 EP2286470 A1 EP 2286470A1
Authority
EP
European Patent Office
Prior art keywords
layer
contact
semiconductor chip
radiation
contact layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09765426A
Other languages
German (de)
English (en)
Inventor
Matthias Sabathil
Siegfried Herrmann
Bernd Barchmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2286470A1 publication Critical patent/EP2286470A1/fr
Withdrawn legal-status Critical Current

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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73267—Layer and HDI connectors
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    • H01L33/58—Optical field-shaping elements

Definitions

  • the present invention relates to a
  • Radiation-emitting component with a carrier and at least one semiconductor chip. Furthermore, the invention relates to a method for producing a radiation-emitting component.
  • semiconductor chips have a first contact layer, a semiconductor layer sequence arranged thereon, and a second contact layer arranged on the side of the semiconductor layer sequence opposite the first contact layer.
  • the surface of the semiconductor chip on which the second contact layer is applied forms a radiation exit surface for the radiation emitted by the semiconductor chip.
  • the second contact layer can be arranged in regions on the radiation exit surface.
  • the second contact layer is formed as a 'contact structure with webs and a bond pad.
  • areas of the radiation exit surface, on which the ' contact structure is applied usually no radiation extraction takes place, since the contact structure is conventionally radiation-absorbing.
  • the actually to Radiation decoupling used surface of the semiconductor chip is therefore limited by the contact structure. This reduction depends on the area of the contact structure in relation to the radiation exit area. The reduced radiation exit area disadvantageously reduces the efficiency of the semiconductor chip.
  • electrical bonding techniques between the chip and a carrier are predominantly wire bonding and soldering or chip mounting with conductive adhesive.
  • By contacting the semiconductor chip via bonding wires on bonding pads adversely affects a chip near arrangement of optical elements to the semiconductor chip.
  • the invention has for its object to provide a radiation-emitting device, which in particular has improved efficiency and at the same time a low height. It is another object of the invention to provide a method for producing such
  • a radiation-emitting component which has a carrier and at least one semiconductor chip arranged on the carrier.
  • the Semiconductor chip has an active layer for generating electromagnetic radiation and a first contact layer.
  • the carrier has at least one first and one second contact structure for electrical contacting of the at least one semiconductor chip.
  • the semiconductor chip is electrically conductively connected to the first contact structure via the first contact layer.
  • a passivation layer is arranged on at least one side surface of the semiconductor chip.
  • a second contact layer, which leads from the surface of the semiconductor chip facing away from the carrier over the passivation layer, preferably along the side surface of the semiconductor chip, to the second contact structure is arranged on at least one partial region of the passivation layer.
  • the semiconductor chip has no growth substrate.
  • the semiconductor chip is designed as a so-called substrateless semiconductor chip.
  • a semiconductor chip is considered a substrateless semiconductor chip, during its manufacture the growth substrate on which a semiconductor layer sequence has been grown, for example epitaxially, has been completely detached.
  • Substrate-less semiconductor chips advantageously results in a particularly low overall height of the component.
  • the dimension of the radiation-emitting component can thus be almost in the region of the thickness of the epitaxial layer sequence.
  • the contacting of the semiconductor chip is not carried out by bonding wires, but by the second contact layer.
  • the second contact layer is guided planar. Under a planar leadership is to understand a chip near arrangement. That means that no bonding wires or others Conducting structures, which are arranged at a distance from the semiconductor chip, find use.
  • the second contact layer is arranged along the side surface of the semiconductor chip on a passivation layer.
  • the passivation layer is preferably electrically insulating in order to avoid a short circuit of the semiconductor chip.
  • planar contacting of the semiconductor chip results in a particularly low overall height of the component.
  • a chip-near arrangement of, for example, optical elements is possible with advantage.
  • the second contact layer of the semiconductor chip is for electrically contacting the semiconductor chip to the second
  • the second contact layer leads laterally beyond the surface of the semiconductor chip, preferably along the side surface of the semiconductor chip onto the surface of the carrier facing the semiconductor chip, and in particular to the second contact structure. This means that the second contact layer preferably leads, inter alia, over the side surface of the semiconductor chip provided with the passivation layer.
  • the second contact layer is preferably arranged such that it covers only a partial region of the surface of the semiconductor chip, in particular only an edge region of the surface. Preferably, less than 20%, more preferably less than 10%, of the surface has a second contact layer.
  • the second contact layer for the radiation emitted by the active layer is at least partially radiation-transmissive.
  • the passivation layer is particularly preferably at least partially transparent to radiation for the radiation emitted by the active layer.
  • An absorption of the radiation emitted by the semiconductor chip in the second contact layer and / or in the passivation layer can thereby advantageously be minimized, so that the efficiency of the component advantageously increases.
  • the absorption of the radiation emitted by the semiconductor chip in the second contact layer and / or in the passivation layer is preferably less than 40%, particularly preferably less than 20%.
  • the second contact Chicht is arranged on the surface facing away from the carrier surface of the semiconductor chip frame-shaped.
  • the surface on which the second contact layer is guided is preferably the radiation exit surface of the semiconductor chip.
  • the second contact layer may preferably completely surround the region of the radiation exit surface of the semiconductor chip, wherein the outline of the frame-shaped contact structure is guided, for example, rectangular, round, oval or in another geometric shape on the surface of the semiconductor chip.
  • the frame-shaped arrangement of the second contact layer on the surface of the semiconductor chip advantageously improves the current spreading of the semiconductor chip, as a result the efficiency of radiation generation improved with advantage.
  • the frame-shaped contact geometry of the second contact layer is particularly suitable for chips with a side length of less than 400 microns.
  • the second contact layer has contact webs which are arranged on the surface of the semiconductor chip facing away from the carrier.
  • the second contact layer is arranged on the surface of the semiconductor chip frame-shaped, wherein in this frame contact contact webs are arranged, which preferably do not intersect on the surface of the semiconductor chip and particularly preferably parallel to each other.
  • the contact webs are partially in direct contact with the frame contact.
  • the contact webs improve the current spreading of the semiconductor chip, whereby larger chip dimensions are possible.
  • Such a contact structure is particularly advantageous for chips with a side length of greater than 400 microns.
  • a metal layer is arranged on the second contact layer.
  • Metal webs are particularly preferably guided on the second contact layer, wherein the metal webs are preferably narrower than the second contact layer.
  • the metal webs thus preferably have a smaller width than the second contact structure. That means the second one
  • the metal layer laterally projects beyond the metal webs in plan view of the component.
  • the metal layer may be incorporated in the second contact layer. This means that the metal layer is embedded in the second 'contact layer.
  • the metal layer is thus preferably enclosed at least on the side surfaces of the second contact layer.
  • One of the electrical leads of the semiconductor chip may thus comprise two different materials, the second contact layer and the metal layer.
  • the metal layer can be arranged on the second contact layer or embedded in the second contact layer.
  • the metal layer thereby improves the conductivity of the electrical supply.
  • this can be used one, compared 'to a conventionally used for contact metal layer, narrower metal layer.
  • An additional metal layer improves the conductivity, while at the same time the absorption of the radiation emitted by the semiconductor chip in the metal layer is reduced by the smallest possible width of the metal layer.
  • both the second contact layer and the metal layer each have contact webs, wherein the contact webs of the metal layer are arranged on or in the contact webs of the second contact layer, particularly preferably, the metal layer has contact webs, which have a smaller width than the contact webs of the second contact layer.
  • first and second plated-through holes are guided by the carrier, wherein in each case the first plated-through hole is connected to the first contact structure and in each case the second plated-through hole is electrically conductively connected to the second contact structure.
  • the radiation-emitting component By contacting the semiconductor chip via plated-through holes, which pass through the carrier, the radiation-emitting component can be surface-mountable.
  • Surface-mountable components or so-called SMT components (SMT: Surface Mount Technology), are characterized in that they can be soldered directly to a printed circuit board, for example, by means of solderable contact areas. As a result, very dense assemblies are possible, which reduces the space required. This allows a high packing density.
  • the second contact layer is preferably a TCO layer (TCO: Transparent Conductive Oxide).
  • TCO Transparent Conductive Oxide
  • the second contact layer particularly preferably comprises IZO (indium zinc oxide), ITO (indium tin oxide) or ZnO (zinc oxide).
  • the carrier preferably contains a ceramic, silicon or aluminum nitride.
  • the carrier may be an intermetallic ceramic, a metal or a metal alloy having an electrically insulating layer disposed thereon, for example.
  • Dielectric include.
  • At least one optical element is arranged on the surface of the semiconductor chip facing away from the carrier.
  • the optical element of the radiation exit surface of the semiconductor chip is arranged downstream.
  • optical components are to be understood as meaning components which have jet-forming properties for the radiation emitted by the active layer of the semiconductor chip, and thus specifically influence in particular the emission characteristic and / or the directionality of the emitted radiation.
  • the semiconductor chip is followed by a mirrored prism, which effects a 90 ° deflection of the radiation emitted by the semiconductor chip.
  • a page emitter can be generated.
  • one or more layers with a conversion element contained therein, so-called conversion layers may be disposed downstream of the radiation exit surface.
  • the conversion element absorbs of 'the semiconductor chip emitted radiation is at least partially and emits radiation in another wavelength range.
  • angle or edge filters can be arranged downstream of the semiconductor chip.
  • the second contact layer has a thickness in a range between 50 nm inclusive and 300 nm inclusive.
  • the semiconductor chip preferably has a height of less than 40 ⁇ m.
  • Passivation layer leads to the second contact structure.
  • Advantageous embodiments of the method are analogous to the advantageous embodiments of the radiation-emitting device and vice versa.
  • a radiation-emitting component described here can be produced. This means that the features disclosed in connection with the component also apply to the method and are therefore not explained again.
  • a metal layer is preferably applied to the second contact layer or introduced into the second contact layer, for example by means of an etching process. This improves the conductivity of the contacting of the semiconductor chip.
  • the carrier is added with semiconductor chips arranged thereon
  • Isolated radiation-emitting components each having at least one semiconductor chip.
  • the component is not restricted to just one semiconductor chip.
  • Component may be in terms of the intended use of
  • Component vary.
  • FIG. 1A shows a schematic cross section of a first exemplary embodiment of a device according to the invention
  • Figure IB is a schematic plan view of the
  • Figure 2 is a schematic plan view of a second
  • FIG. 3A is a schematic plan view of a third
  • FIG. 3B shows a schematic cross section of the semiconductor chip of the third exemplary embodiment of FIG. 3A with a second contact layer and metal layer arranged thereon, FIG.
  • Figure 4A is a schematic cross section of a fourth
  • Figure 4B is a schematic plan view of the embodiment of the invention.
  • FIGS. 5A to 5C each show a schematic cross-section of an exemplary embodiment of a device according to the invention.
  • FIGS. 6A to 6F each show a schematic view of one
  • FIG. 1A shows a radiation-emitting component which has a carrier 1 and a semiconductor chip 2 arranged thereon.
  • the semiconductor chip 2 has an active layer for generating electromagnetic radiation and a first contact layer 21.
  • the active layer of the semiconductor chip 2 has a pn junction, a double heterostructure, a single quantum well structure (SQW) or a multiple quantum well structure (MQW) for generating radiation.
  • SQW single quantum well structure
  • MQW multiple quantum well structure
  • the semiconductor chip 2 is preferably based on a nitride, a phosphite or an arsenide compound semiconductor.
  • the semiconductor chip 2 of the radiation-emitting component has no growth substrate.
  • the semiconductor chip 2 is thus designed as a substrateless semiconductor chip.
  • the semiconductor chip 2 results in a particularly low height of the device with advantage.
  • the semiconductor chip 2 has a height of less than 100 .mu.m, particularly preferably less than 40 .mu.m.
  • the dimension of the component can thus be almost in the region of the thickness of the Epitaxie WegenUSD.
  • the carrier 1 For the electrical contacting of the semiconductor chip 2, the carrier 1 has a first contact structure 4a and a second contact structure 4b.
  • the semiconductor chip 2 is arranged in regions on the first contact structure 4a.
  • the semiconductor chip 2 is electrically conductively connected to the first contact structure 4a via the first contact layer 21.
  • the first contact structure 4a and the second contact structure 4b are arranged on the carrier 1 so as to be electrically insulated from each other.
  • the first contact structure 4a and the second contact structure 4b are arranged on the carrier 1 at a distance from one another.
  • the semiconductor chip 2 has a radiation exit surface 3, which is arranged on the side of the semiconductor chip 2 opposite the carrier 1.
  • a passivation layer 5 is arranged on the side surfaces of the semiconductor chip 2 and partially on the radiation exit surface 3 of the semiconductor chip 2.
  • a passivation layer 5 is arranged on the entire side surfaces and the region of the radiation exit surface 3, which at the side surfaces of the Semiconductor chip 2 is adjacent, so in particular the edge region of the radiation exit surface 3, a passivation layer 5 on.
  • the passivation layer 5 is preferably arranged in the shape of a frame on the radiation exit surface 3, the passivation layer 5 projecting laterally beyond the semiconductor chip 2 in a plan view of the semiconductor chip 2. The passivation layer 5 is thus partially arranged next to the semiconductor chip 2.
  • the passivation layer 5 is arranged at least partially between the first contact structure 4a and the second contact structure 4b.
  • the passivation layer 5 may also extend to the second contact structure 4b.
  • the passivation layer 5 is electrically insulating.
  • a second contact layer 6 is arranged on at least a portion of the passivation layer 5.
  • the second contact layer 6 leads from the radiation exit surface 3 on the passivation layer 5 along the side surface of the semiconductor chip 2 to the second contact structure 4b.
  • the second contact layer 6 thus represents an electrical connection between the semiconductor chip 2 and the second contact structure 4b.
  • the electrically insulating passivation layer 5 thus electrically insulates the second contact layer 6 from the region
  • Semiconductor chip 2 in particular from the side surfaces of the semiconductor chip. 2
  • the second contact layer 6 is arranged on the radiation exit surface 3 of the semiconductor chip 2 in the form of a frame. A portion of the second contact layer 6 is in direct contact with the radiation exit surface 3 of the semiconductor chip 2 '.
  • the second Contact layer 6 laterally projects beyond the passivation layer 5, which is preferably likewise arranged in the shape of a frame.
  • the geometry of the second contact layer 6, which is designed as a frame contact, is shown in FIG. 1B.
  • the radiation exit surface 3 is shown, which is enclosed by the second contact layer 6 'like a frame.
  • the radiation exit surface 3 is preferably largely free of the passivation layer 5 and of the second contact rail 6. This means that preferably less than 20%, particularly preferably less than 10%, of the radiation exit surface 3 has a passivation layer 5 arranged thereon and / or a second one arranged thereon Contact layer 6 has.
  • the second contact layer 6 is at least partially transparent to radiation for the radiation emitted by the active layer. This means that the absorption coefficient of the second contact layer 6 in the wavelength range of the emitted radiation of the semiconductor chip 2 is preferably less than 40%, particularly preferably less than 20%.
  • the second contact layer 6 is preferably a TCO layer, particularly preferably the second contact layer 6 comprises IZO, ITO or ZNO.
  • the second contact layer 6 preferably has a thickness in a range between 50 nm inclusive and 300 nm inclusive.
  • the carrier 1 preferably contains a ceramic, silicon or aluminum nitride.
  • the carrier 1 may be an intermetallic ceramic, a metal, or a metal alloy with an electric one disposed thereon.
  • insulating layer for example a dielectric.
  • FIG. 2 shows a plan view of a further exemplary embodiment of a component.
  • the second contact layer 6 has contact webs 61 which are arranged on the radiation exit surface 3 of the semiconductor chip 2.
  • the contact webs 61 are preferably arranged so that they do not intersect on the radiation exit surface 3.
  • the contact webs 61 are particularly preferably arranged so that they extend parallel to at least one side surface of the second contact layer 6 arranged in the manner of a frame.
  • the contact webs 61 are partially in direct contact with the second contact layer 6.
  • the embodiment shown in Figure 3A differs from the embodiment shown in Figure 2 in that on the second contact layer 6 and on the contact webs 61, a metal layer 7 is arranged. Accordingly, one of the electrical leads of the semiconductor chip is composed of two layers, the second contact layer 6 and the metal layer 7 arranged thereon. The metal layer 7 can furthermore be embedded in the second contact layer 6 (not illustrated).
  • the metal layer 7 preferably has contact webs which are arranged on the contact webs 61 of the second contact layer 6. Particularly preferably, the contact webs of the metal layer 7 are narrower than the contact webs 61 of the second Contact layer 6. This means that the contact webs of the metal layer 7 preferably have a smaller thickness than the contact webs 61 of the second contact layer 6.
  • the metal layer 7 may preferably be formed particularly narrow. This advantageously reduces the proportion of the emitted radiation which is absorbed by the metal layer 7, whereas the conductivity of the component advantageously improves with the metal layer 7.
  • FIG. 3B shows a cross section of the semiconductor chip 2 with a second contact layer 6 arranged thereon and a metal layer 7 arranged on the second contact layer 6.
  • the second contact layer 6 laterally projects beyond the metal layer 7.
  • the second contact layer 6 preferably projects laterally beyond the metal layer 7 on both sides.
  • the metal layer 7 is preferably designed to be particularly narrow.
  • the metal layer 7 is laterally enclosed by the second contact layer 6 in this case.
  • FIG. 4 shows a further exemplary embodiment of a radiation-emitting component.
  • FIG. 4A shows a cross-section of the component
  • FIG. 4B shows a plan view of the associated component.
  • FIG. 1A by virtue of the fact that first and second plated-through holes 8a, 8b are guided through the carrier 1.
  • the first via 8a is connected to the first contact structure 4a electrically connected.
  • the second via 8b is electrically connected to the second contact structure 4b.
  • the first and the second contact structure 4a, 4b have a different structuring.
  • the first contact structure 4 a preferably has substantially the same base area as the semiconductor chip 2. Accordingly, the first contact structure 4a overhangs the
  • Semiconductor chip 2 in plan view of the semiconductor chip 2 is not lateral.
  • the electrical connection of the semiconductor chip 2 takes place by means of plated-through holes 8a, 8b through the carrier 1.
  • the second contact structure 4b is preferably arranged in an electrically insulated manner at a distance from the first contact structure 4a on the carrier.
  • Semiconductor chip 2 is electrically conductively connected via the second contact structure 6 to the second contact structure 4b.
  • the component shown in Figure 4 is preferably formed by means of the first and the second via 8a, 8b as a surface mountable device.
  • optical elements can be arranged close to the chip on the semiconductor chip 2.
  • the semiconductor chip 2 for example, is followed by a mirrored prism as the optical element 9.
  • the prism deflects the radiation emitted by the semiconductor chip 2 by approximately 90 °.
  • a side emitter can be realized. This means that preferably radiation is decoupled laterally out of the component. Due to the chip-near arrangement of the prism a compact side emitter can be realized with advantage.
  • the prism points away from the semiconductor chip 2
  • the semiconductor chip 2 facing away from the surface of the prism is preferably completely mirrored. As a result, the radiation emitted by the semiconductor chip 2 can be deflected at the mirror surface 91 such that the radiation emits laterally out of the component.
  • a compensation layer 15 is preferably arranged between the semiconductor chip 2 and the prism, which allows a nearly planar surface.
  • a conversion layer is arranged downstream of the semiconductor chip 2 as an optical element 9 in the emission direction.
  • the conversion layer preferably contains at least one conversion element which at least partially absorbs the radiation emitted by the semiconductor chip 2 and emits in a different wavelength range.
  • the concentration of the conversion element in the conversion layer can be determined such that the radiation emitted by the semiconductor chip 2 is almost completely absorbed.
  • the concentration of the conversion element may be lower, so that only part of the radiation emitted by the semiconductor chip 2 is absorbed, in this case, preferably, a mixed radiation emitted by the component is formed, which comprises the radiation emitted by the semiconductor chip and the radiation re-emitted by the conversion element.
  • the semiconductor chip 2 is arranged in the emission direction as an optical element 9, downstream of an angle filter, or an edge filter, close to the chip.
  • a compensation layer 15 is arranged between the semiconductor chip 2 and the filter for the planar arrangement of the filters.
  • FIGS. 6A to 6F respectively show process steps for producing a plurality of radiation-emitting components.
  • a semiconductor layer sequence 20 for example epitaxially, is grown on a growth substrate 10.
  • a first contact layer 21 is applied on the semiconductor layer sequence 20.
  • semiconductor layer sequence 20 and arranged thereon first contact layer 21 structured, preferably by means of etching. This structuring results in semiconductor chips 2, each having a semiconductor layer sequence 20 and a first contact layer 21 arranged thereon.
  • a carrier 1 is provided, the first contact structures 4a and second Having contact structures 4b.
  • the carrier 1 and the growth substrate 10 are arranged relative to each other such that the semiconductor chips 2 face the first contact structures 4a.
  • the first contact structure 4a is accordingly structured on the carrier 1 in such a way that a partial region of the first contact structure 4a is approximately as large as the base surface of a semiconductor chip 2.
  • Semiconductor chip 2 with the first contact layer 21 on a portion of the first contact structure of the carrier 1 is arranged.
  • the first contact layer 21 is facing the carrier 1.
  • the semiconductor chips 2 can be positioned on the carrier 1 by means of an automatic pick and place process and subsequently electrically and / or thermally connected (not shown).
  • the first contact layer 21 not only serves for the electrical contacting of the semiconductor chip 2, but may also assume the puncture of an optical mirror. This means that the first contact layer 21 that of the
  • Semiconductor chip 2 emitted radiation which is emitted in the direction of the carrier 1, preferably in the direction of Radiation exit surface 3 of the semiconductor chip 2 is reflected back.
  • a passivation layer 5 applied at least on each of the side surfaces of a semiconductor chip 2.
  • the passivation layer 5 preferably covers a partial area of the radiation exit area 3, in particular the edge area of the radiation exit area 3.
  • the passivation layer 5 is preferably applied in regions to the carrier 1 and to the first and second contact structures 4a, 4b.
  • the passivation layer 5 is accordingly arranged on the semiconductor chip 2 and the carrier 1 such that it extends over the edge region of the radiation exit surface 3 and over the side surfaces of the semiconductor chip 2.
  • the carrier 1 at least partially on a passivation layer 5 arranged thereon.
  • 0 guides the first contact structure 4a and the second contact structure
  • a second contact layer 6 is applied to at least one subregion of the 0 passivation layer 5.
  • the second contact layer 6 is preferably arranged in the form of a frame on a partial region of the radiation exit surface 3 of the semiconductor chip 2. A part of the second contact layer 6 is in direct contact with the radiation exit surface 3.
  • the frame-shaped arrangement of the second contact layer 6 is preferably carried out a current expansion in the semiconductor chip 2, whereby the efficiency increases with advantage.
  • the second contact layer 6 is preferably at least partially transparent to radiation for the radiation emitted by the semiconductor chip 2.
  • the largest possible partial surface of the radiation exit surface 3 is free of passivation layer 5 and second contact layer 6.
  • each a passivation layer 5 and a second contact layer 6 are arranged.
  • the second contact layer 6 preferably represents the second 'contact of the semiconductor chips. 2 That is, the second contact layer 6, both the second contact of the semiconductor chips 2, for example the n-contact, and the electrical supply from the semiconductor chip 2 to the second contact structure 4b , It is therefore not necessary, as conventionally, to arrange a second contact of the semiconductor chip and additionally an electrical supply to the second contact.
  • the radiation-emitting components produced in the majority can now be singulated by means of cuts 12.
  • the carrier 1 is arranged with semiconductor chips 2 arranged thereon in such a way that in each case one radiation-emitting component has at least one semiconductor chip 2.
  • the number of semiconductor chips of a component may vary, depending in each case on the intended use of the component.
  • the invention is not limited by the description based on the embodiments of this, but includes each new feature and any combination of features, which in particular includes any combination of features in the claims, even if this feature or this combination itself is not explicitly in the claims or embodiments is given.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un composant émetteur de rayonnement qui possède un support (1) et au moins une puce de semiconducteur (2) placée dessus. La puce de semiconducteur (2) présente une couche active destinée à produire un rayonnement électromagnétique et une première couche de contact (21). Le support (1), pour le contactage électrique de ladite ou desdites puces de semiconducteur (2), possède au moins une première et une deuxième structure de contact (4a, 4b). La puce de semiconducteur (2) est reliée de manière électriquement conductrice à la première structure de contact (4a), via la première couche de contact (21). Une couche de passivation (5) est placée au moins partiellement sur l'une des surfaces latérales de la puce de semiconducteur (2). Une deuxième couche de contact (6) est placée sur au moins une partie de la couche de passivation (5) et réalise la conduction entre la surface de la puce de semiconducteur (2) opposée au support (1) et la deuxième structure de contact (4b), via la couche de passivation (5). La puce de semiconducteur (2) ne possède pas de substrat de croissance (10). L'invention concerne en outre un procédé pour la fabrication d'un tel composant.
EP09765426A 2008-06-18 2009-05-08 Composant émetteur de rayonnement et procédé de fabrication d'un composant émetteur de rayonnement Withdrawn EP2286470A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008028886.1A DE102008028886B4 (de) 2008-06-18 2008-06-18 Strahlungsemittierendes Bauelement und Verfahren zur Herstellung eines strahlungsemittierenden Bauelements
PCT/DE2009/000647 WO2009152790A1 (fr) 2008-06-18 2009-05-08 Composant émetteur de rayonnement et procédé de fabrication d'un composant émetteur de rayonnement

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EP2286470A1 true EP2286470A1 (fr) 2011-02-23

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EP (1) EP2286470A1 (fr)
KR (1) KR20110020225A (fr)
CN (1) CN101971374B (fr)
DE (1) DE102008028886B4 (fr)
WO (1) WO2009152790A1 (fr)

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KR100999733B1 (ko) * 2010-02-18 2010-12-08 엘지이노텍 주식회사 발광 소자, 발광 소자 제조방법 및 발광 소자 패키지
US8338317B2 (en) 2011-04-06 2012-12-25 Infineon Technologies Ag Method for processing a semiconductor wafer or die, and particle deposition device
DE102011010503A1 (de) * 2011-02-07 2012-08-09 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip
DE102011010504A1 (de) * 2011-02-07 2012-08-09 Osram Opto Semiconductors Gmbh Optoelektrischer Halbleiterchip
CN102368527A (zh) * 2011-10-27 2012-03-07 华灿光电股份有限公司 一种无需打线的发光二极管芯片及其制备方法
JP5913955B2 (ja) * 2011-12-19 2016-05-11 昭和電工株式会社 発光ダイオード及びその製造方法
JP5865695B2 (ja) * 2011-12-19 2016-02-17 昭和電工株式会社 発光ダイオード及びその製造方法
CN105938862A (zh) * 2016-05-24 2016-09-14 华灿光电(苏州）有限公司 一种GaN基发光二极管芯片及其制备方法

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CN101971374B (zh) 2013-03-13
KR20110020225A (ko) 2011-03-02
DE102008028886A1 (de) 2009-12-24
CN101971374A (zh) 2011-02-09
DE102008028886B4 (de) 2024-02-29
WO2009152790A1 (fr) 2009-12-23

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