WO2021165098A1 - Puce semi-conductrice optoélectronique et son procédé de fabrication - Google Patents

Puce semi-conductrice optoélectronique et son procédé de fabrication Download PDF

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Publication number
WO2021165098A1
WO2021165098A1 PCT/EP2021/053077 EP2021053077W WO2021165098A1 WO 2021165098 A1 WO2021165098 A1 WO 2021165098A1 EP 2021053077 W EP2021053077 W EP 2021053077W WO 2021165098 A1 WO2021165098 A1 WO 2021165098A1
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WIPO (PCT)
Prior art keywords
carrier
semiconductor chip
electrically conductive
contact
front side
Prior art date
Application number
PCT/EP2021/053077
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German (de)
English (en)
Inventor
Massimo DRAGO
Luca HAIBERGER
Original Assignee
Osram Opto Semiconductors Gmbh
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Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2021165098A1 publication Critical patent/WO2021165098A1/fr

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Definitions

  • An optoelectronic semiconductor chip, a semiconductor component and a method for producing an optoelectronic semiconductor chip are specified.
  • One problem to be solved consists in specifying an optoelectronic semiconductor chip which can be designed to be particularly compact. Further objects to be solved consist in specifying a semiconductor component with such an optoelectronic semiconductor chip and a method for producing such an optoelectronic semiconductor chip.
  • the optoelectronic semiconductor chip is specified.
  • the optoelectronic semiconductor chip comprises a carrier with a front side and a rear side opposite the front side.
  • the carrier preferably forms the stabilizing component of the semiconductor chip.
  • the front and the rear preferably run parallel within the scope of the manufacturing tolerance.
  • a thickness of the carrier measured from the Front to back is, for example, at least 50 mpi or at least 100 pm.
  • the thickness of the carrier can be a maximum of 500 ⁇ m or a maximum of 250 ⁇ m or a maximum of 150 ⁇ m.
  • the rear side of the carrier forms in particular at least part of the rear side of the semiconductor chip, which is exposed in the unmounted state of the semiconductor chip.
  • the optoelectronic semiconductor chip comprises one
  • Semiconductor layer sequence with an active layer for generating or absorbing electromagnetic radiation is arranged on the front side of the carrier.
  • the semiconductor layer sequence is based, for example, on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material, such as Al n In ] __ nm Ga m N, or a phosphide compound semiconductor material, such as Al n In ] __ nm Ga m P, or an arsenide
  • Compound semiconductor material such as Al n In ] __ nm Ga m As or Al n In ] __ nm Ga m AsP, where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and m + n ⁇ 1 in each case.
  • the semiconductor layer sequence can have dopants and additional components. For the sake of simplicity, however, only the essential components of the crystal lattice are shown in FIG.
  • the semiconductor layer sequence is preferably based on AlInGaN.
  • the active layer of the semiconductor layer sequence contains in particular at least one pn junction and / or at least one quantum well structure in the form of a single quantum well, SQW for short, or in the form of a multi-quantum well structure, MQW for short.
  • the semiconductor chip preferably comprises one, in particular precisely one, contiguous active layer. Alternatively, the active layer can also be segmented.
  • the active layer can, for example, generate electromagnetic radiation in the blue or green or red spectral range or in the UV range or in the IR range during normal operation.
  • a semiconductor chip is understood here and below to mean an element that can be handled separately and electrically contacted.
  • a semiconductor chip is created in particular by separation from a composite wafer. In particular, side surfaces of such a semiconductor chip then have, for example, traces from the singulation process of the wafer assembly.
  • a semiconductor chip preferably comprises exactly one originally contiguous region of the semiconductor layer sequence grown in the wafer assembly.
  • the semiconductor layer sequence of the semiconductor chip is preferably formed contiguously.
  • the lateral dimensions of the semiconductor chip in the x and y directions, measured perpendicular to one another and parallel to the front side of the carrier, are, for example, at most 1% or at most 5% or at most 10% greater than the lateral dimensions of the active layer or the semiconductor layer sequence in x- and y-direction.
  • the semiconductor chip also includes, for example Growth substrate on which the entire semiconductor layer sequence has grown.
  • Lateral dimensions of the semiconductor chip in the x and y directions are, for example, at least 10 gm and at most 500 gm, for example at most 350 ⁇ m.
  • the lateral dimensions of the semiconductor layer sequence in the x and y directions correspond in particular essentially to the lateral dimensions of the carrier in the x and y directions, for example with a maximum deviation of 10% or 5%.
  • the optoelectronic semiconductor chip comprises a first and a second contact surface on outer surfaces of the carrier for external electrical contacting of the semiconductor chip. In the unassembled state, the contact surfaces are therefore exposed on the outer surfaces of the carrier.
  • the first contact surface has a different electrical potential than the second contact surface.
  • the first contact area forms, for example, an anode, the second contact area a cathode of the semiconductor chip, or vice versa.
  • the first contact area is electrically conductively connected to an n-doped or p-doped layer of the semiconductor layer sequence and the second contact area is connected to an oppositely doped, that is to say p-doped or n-doped, layer.
  • the first and the second contact area are in particular made of metal.
  • electrically conductive connections from the contact surfaces to the front side of the wearer.
  • the electrically conductive connections are preferably led, starting from the contact surfaces, through the carrier to the front.
  • the electrically conductive connections are preferably also made of metal.
  • the semiconductor layer sequence is electrically connected to the electrically conductive connections on the front side via its side facing the carrier.
  • a side of the semiconductor layer sequence facing away from the carrier is preferably free of electrical connection regions.
  • Semiconductor layer sequence thus preferably only supplied charge carriers via the side facing the carrier.
  • the region of the semiconductor layer sequence that lies on a side of the active layer facing away from the carrier can be electrically contacted via vias that extend through the active layer from the side of the semiconductor layer sequence facing the carrier.
  • the semiconductor layer sequence has contact structures both for the supply of electrons and for the supply of holes.
  • the contact structures of the semiconductor layer sequence has contact structures both for the supply of electrons and for the supply of holes.
  • Semiconductor layer sequences are on the one hand each connected in an electrically conductive manner to a semiconductor layer of the semiconductor layer sequence.
  • the contact structures are on the front side of the carrier each connected to one of the electrically conductive connections to the contact surfaces.
  • At least the first contact surface is formed on a transverse side of the carrier running transversely to the front side.
  • the transverse side of the carrier runs in particular perpendicular or substantially perpendicular to the front and / or rear of the carrier.
  • the transverse side connects the front with the back.
  • the second contact surface can also be formed on a transverse side of the carrier or on the rear side of the carrier.
  • the carrier is created in particular from a larger carrier in a composite by a separation process.
  • the transverse sides of the carrier can therefore have traces of physical or chemical material removal, for example saw grooves.
  • the optoelectronic semiconductor chip comprises a carrier with a front side and a rear side opposite the front side and a semiconductor layer sequence with an active layer for generating or absorbing electromagnetic radiation on the front side of the carrier. Furthermore, the semiconductor chip comprises a first and a second contact area on outer surfaces of the carrier for external electrical contacting of the semiconductor chip. Electrically conductive connections are made from the contact surfaces to the front of the carrier.
  • Semiconductor layer sequence is electrically connected to the electrically conductive connections on the front side via its side facing the carrier.
  • At least the first Contact surface is formed on a transverse side of the carrier running transversely to the front side.
  • the present invention is based in particular on the knowledge that in many semiconductor chips, in particular in flip chips, the contact areas for external electrical contacting are formed on the rear side of a carrier. In order to avoid short circuits, however, there must be a certain minimum distance between the contact surfaces. As a result, a minimum size of the semiconductor chips is specified. However, there is a desire for ever smaller semiconductor chips.
  • one of the contact surfaces is formed on a transverse side of the carrier running transversely to the rear side.
  • the second contact surface is also formed on a transverse side of the carrier running transversely to the front side.
  • the second contact surface is preferably formed on a different transverse side of the carrier than the first contact surface.
  • the two contact surfaces are formed on opposite transverse sides of the carrier.
  • the carrier has, for example, the geometric shape of a cuboid with four transverse sides, which each connect the front to the back of the carrier.
  • a rear side of the semiconductor chip is at least partially, preferably largely or almost completely, formed by the back of the carrier. For example, at least 90% or at least 95% of the rear side of the semiconductor chip is formed by the rear side of the carrier.
  • the back of the semiconductor chip is exposed in the unmounted state of the semiconductor chip.
  • the semiconductor chip also comprises a front side which is opposite the rear side and via which, for example, the radiation generated is coupled out during operation of the semiconductor chip.
  • the rear side of the carrier is free from the first contact surface.
  • the first contact surface is therefore not drawn onto the rear side of the carrier and does not cover any areas of the rear side of the carrier.
  • the rear side of the carrier is preferably also not interrupted by contact areas which are electrically conductively connected to the first contact area.
  • the first contact area can, however, terminate flush with the rear side of the carrier on the rear side of the semiconductor chip.
  • the rear side of the carrier is preferably also free of the second contact surface.
  • the rear side of the carrier is preferably also not interrupted by contact areas which are electrically conductively connected to the second contact area.
  • the electrically conductive connections each have a first section in the form of a contact pin which, starting from the front side, extends into the carrier in the direction towards the rear side.
  • the contact pins are in particular elongated, with a longitudinal axis that runs transversely, especially perpendicular to the front.
  • the contact pins are preferably spaced apart from the transverse sides of the carrier. At least the contact pin of the electrically conductive connection, which is connected to the first contact surface, does not extend to the rear of the carrier, but ends inside the carrier.
  • the contact pins are laterally completely surrounded by the material of the carrier. “Lateral” refers to directions parallel to the front side. That is, the contact pins are not exposed on any of the transverse sides of the carrier. In other words, the contact pins run in the interior of the carrier.
  • the electrically conductive connection to the first contact surface has a second section which extends parallel to the front side and electrically connects the contact pin to the first contact surface.
  • the second section preferably also runs in the interior of the carrier, that is to say between the rear side and the front side of the carrier.
  • the second section is therefore spaced apart from the rear and preferably also from the front.
  • a distance of the second section from the front side and / or from the rear side is between 30% and 90%, inclusive, of the thickness of the carrier.
  • the second section is formed in particular as a layer, the main plane of extent of which runs parallel to the front side.
  • the electrically conductive connection to the second contact surface preferably also has a second section which extends parallel to the front side and electrically conductively connects the associated contact pin to the second contact surface. All features that are disclosed in connection with the electrically conductive connection to the first contact surface are also disclosed for the electrically conductive connection to the second contact surface.
  • the rear side of the carrier is electrically insulated from the semiconductor layer sequence.
  • the entire rear side of the carrier can then preferably be fastened to the connection carrier via an adhesive with high thermal conductivity. This enables a particularly high shear value to be achieved.
  • an improved thermal connection of the semiconductor chip to the connection carrier can also be achieved.
  • the rear side of the carrier is formed from dielectric material.
  • the rear side of the carrier is a simply coherent area made of dielectric material. The back of the carrier is therefore not pierced or interrupted by electrically conductive surfaces.
  • the dielectric material of the rear side of the carrier can, for example, be an inorganic material such as silicon dioxide or silicon nitride or silicon carbide or aluminum oxide or aluminum nitride.
  • the rear side of the carrier is formed from an organic, dielectric material.
  • the dielectric material of the rear side has a thermal conductivity of at least 10 W / (mK) or at least 30 W / (mK) or at least 100 W / (m ⁇ K).
  • the semiconductor chip is a flip chip.
  • the semiconductor chip can also comprise the growth substrate for the semiconductor layer sequence or the growth substrate of the semiconductor layer sequence can be completely detached. If the semiconductor chip also includes the growth substrate, this is arranged on a side of the semiconductor layer sequence facing away from the carrier.
  • the semiconductor chip is then a volume emitter. If the growth substrate is detached, the semiconductor chip is a surface emitter.
  • the carrier consists of dielectric material.
  • the carrier preferably comprises or consists of an epoxy.
  • the carrier comprises a first region between the front side and the second section or sections of the electrically conductive connections. This first region is preferably formed by a shaped body, for example made of organic, dielectric material, in particular epoxy. This molded body laterally surrounds the contact pins.
  • the carrier can comprise a second region which is formed between the rear side of the carrier and the second section or sections of the electrically conductive connections.
  • This second area can be formed from a different material than the first area.
  • this second area is formed by an inorganic, dielectric material.
  • the electrically conductive connections to the contact surfaces, which can run through the carrier, are not considered to be part of the carrier.
  • a height of the first contact surface measured as the extent of the first contact surface in a direction from the rear of the carrier to the front of the carrier, is between 30% and 100% inclusive, preferably between 50% and 100% inclusive, particularly preferably between including 50% and 90% of the distance between the front and back of the wearer.
  • the first contact surface can cover a large part, that is to say at least 50%, of the assigned transverse side.
  • the first contact surface preferably extends to the rear of the carrier, that is to say is flush with the rear of the carrier.
  • the first contact surface is preferably withdrawn from the front side of the carrier, for example by at least 10 ⁇ m or at least 30 ⁇ m.
  • the second contact surface is also formed on a transverse side of the carrier, the information just given regarding the height and size of the first contact surface and the distance to the front or rear also apply accordingly to the second contact surface.
  • the semiconductor component comprises an optoelectronic semiconductor chip described here.
  • the semiconductor component further comprises a connection carrier.
  • the connection carrier has connection areas.
  • the semiconductor chip is attached to the connection carrier.
  • the first contact surface is wetted with an electrically conductive connecting means, which is an electrical Establishes connection between a first connection area and the first contact surface.
  • the second contact area is electrically conductively connected to a second connection area.
  • connection carrier can be a ceramic carrier or a printed circuit board or an encapsulated lead frame.
  • a lateral extension of the connection carrier, measured parallel to the front side of the semiconductor chip, is preferably greater than that of the semiconductor chip.
  • a lateral extension of the connection carrier is at least twice as large as that of the semiconductor chip.
  • the back side of the semiconductor chip is attached to the connection carrier.
  • the connection areas of the connection carrier are preferably metallic surfaces of the connection carrier.
  • the electrically conductive connecting means between the first contact surface and the first connection area is, for example, a solder material.
  • the second contact area is preferably electrically conductively connected to the second connection area via a solder material.
  • the rear side of the carrier is connected to the connection carrier via a further connecting means, in particular an adhesive.
  • the further connecting means preferably covers the entire rear side of the carrier.
  • the further connecting means between the rear side and the connection carrier is based on a silicone.
  • the further connecting means can be electrically insulating.
  • the further connecting means comprises a matrix material and thermally conductive filler particles embedded therein.
  • the matrix material can be a silicone.
  • the filler particles can be metallic filler particles, for example made of silver, or filler particles made of a dielectric, inorganic material such as silicon nitride, or silicon carbide or aluminum oxide or aluminum nitride. In particular, the filler particles have a higher thermal conductivity than the matrix material.
  • a particularly good thermal connection between the semiconductor chip and the connection carrier is achieved through the use of such a connecting means. Because at least the first contact area, but preferably also the second contact area, are not formed on the rear side of the semiconductor chip, but rather on transverse sides, the entire rear side of the carrier can be covered with the further connecting means and thus a large-area thermal connection to the connection carrier can be realized . A large-area connection between the rear side and the connection carrier is also advantageous with regard to the stability of the semiconductor component.
  • the semiconductor chip and / or the semiconductor component can be used, for example, in a headlight of a motor vehicle or in a screen or in a mobile phone.
  • the method comprises a step A) in which an electrically conductive layer, in particular a metal layer, is applied to a substrate.
  • a step B) a carrier is formed on the substrate.
  • trenches are produced which extend into the carrier and through the electrically conductive layer.
  • step D) transverse sides of the carrier that are exposed within the trenches are coated with electrically conductive material, the electrically conductive material being connected in an electrically conductive manner to the electrically conductive layer.
  • a semiconductor layer sequence which comprises an active layer is connected in an electrically conductive manner to the electrically conductive layer.
  • the carrier and / or the semiconductor layer sequence are severed in the region of the trenches, as a result of which an optoelectronic semiconductor chip is produced.
  • the substrate is preferably a wafer.
  • the electrically conductive layer and the carrier are formed on the same side of the substrate.
  • the trenches are in particular made in the carrier from a side facing away from the substrate.
  • the transverse sides within the trenches run transversely, in particular perpendicularly, to the
  • steps A) and B) are preferably carried out before step C).
  • the shape and size of the semiconductor chip are preferably also defined.
  • step C) a network of trenches is produced which surrounds at least a section of the carrier in a frame-like manner.
  • an optoelectronic semiconductor chip is produced.
  • This semiconductor chip comprises, as a carrier, part of the severed carrier and the severed semiconductor layer sequence.
  • the electrically conductive material applied in the area of the trenches forms the contact areas which are exposed on the transverse sides of the carrier of the semiconductor chip.
  • a first and a second electrically conductive contact pin are produced on the substrate before step A).
  • the contact pins are preferably produced galvanically.
  • an initial layer is first applied, which defines the shape of the contact pins.
  • the contact pins are then lengthened on this starting layer by means of galvanic waxing.
  • the contact pins each have, for example, an aspect ratio of at least 2 or at least 5 or at least 10.
  • the contact pins can be cylindrical.
  • the formation of the carrier comprises reshaping the contact pins with a molded body.
  • the shaped body preferably consists of a dielectric material, in particular an organic, dielectric material, for example epoxy.
  • the shaped body is applied laterally completely around the contact pins, so that the contact pins are embedded in the shaped body.
  • the molded body forms at least part of the carrier.
  • the electrically conductive layer is applied to a side of the shaped body facing away from the substrate. For example, the electrically conductive layer is first applied flatly to the shaped body and then structured photolithographically.
  • the contact pins are connected to the electrically conductive layer.
  • the contact pins are exposed on a side of the molded body facing away from the substrate.
  • the contact pins are flush with the shaped body before the electrically conductive layer is applied.
  • the electrically conductive layer is preferably structured in such a way that the first contact pin and the second contact pin are connected to different sections of the electrically conductive layer, the different sections of the electrically conductive layer being separated from one another and electrically insulated .
  • step E) the semiconductor layer sequence is conductively connected to the ends of the contact pins facing away from the electrically conductive layer.
  • the substrate comprises the semiconductor layer sequence.
  • Step E) is then carried out together or simultaneously with step A).
  • the substrate is a growth substrate with the one epitaxially grown thereon Semiconductor layer sequence.
  • the growth substrate can be partially or completely detached after the carrier has been formed.
  • step E) is carried out after step A) or after step B).
  • the substrate on which the carrier is formed then does not include the semiconductor layer sequence and is detached, for example, before or after the singulation.
  • the molded body initially covers the contact pins. This means that the contact pins are completely embedded in the molded body. The shaped body is then removed until the ends of the contact pins facing away from the substrate are exposed. For example, the shaped body is ground off for this purpose.
  • a dielectric layer is applied to the side of the electrically conductive layer facing away from the molded body.
  • the dielectric layer can be formed from an organic or inorganic material.
  • the dielectric layer is preferably applied to the electrically conductive layer before the trenches are formed. The trenches are then formed through the dielectric layer. The dielectric layer then forms part of the carrier.
  • the method is used to produce a plurality of semiconductor chips. These are initially connected to one another and are separated in step G).
  • the trenches introduced preferably form a Network that surrounds a multiplicity of meshes, each mesh being assigned a semiconductor chip.
  • FIG. 1 shows an exemplary embodiment of the optoelectronic semiconductor chip in a cross-sectional view
  • FIG. 2 shows an exemplary embodiment of the semiconductor component in cross-sectional view
  • FIGS. 3A to 31 different positions in an exemplary embodiment of the method for producing an optoelectronic semiconductor chip.
  • FIG. 1 shows an exemplary embodiment of the optoelectronic semiconductor chip 100 in a cross-sectional view.
  • the semiconductor chip 100 is a flip chip.
  • the semiconductor chip 100 comprises a semiconductor layer sequence 1 with an active layer 10 for generating or absorbing electromagnetic radiation.
  • the semiconductor layer sequence 1 is based, for example, on a nitride compound semiconductor material.
  • a growth substrate for the semiconductor layer sequence 10 has been replaced in the present case.
  • the semiconductor layer sequence 1 is applied to the front side 20 of a carrier 2.
  • the semiconductor layer sequence 1 is electrically contacted via the side facing the front side 20.
  • a rear side 22 of the carrier 2 opposite the front side 20 also forms almost the entire rear side of the semiconductor chip 100.
  • the front side 20 and the rear side 22 of the carrier 2 are connected to one another via transverse sides 21 of the carrier 2.
  • the transverse sides 21 and the rear side 22 form outer surfaces of the carrier 2.
  • the carrier 2 comprises a molded body 25 and a dielectric layer 26.
  • the molded body 25 consists, for example, of epoxy
  • the dielectric layer 26 consists, for example, of an inorganic material such as SiN.
  • a first contact surface 31a and a second contact surface 32a are arranged on the transverse sides 21 of the carrier 2.
  • the contact areas 31a, 32a are exposed in the shown, unmounted state of the semiconductor chip 100 and are used for external electrical contacting of the semiconductor chip 100.
  • Electrically conductive connections 31, 32 are routed from the contact areas 31a, 32a to the front side 20 of the carrier 2.
  • the electrically conductive connections 31, 32 each comprise a first section 31b, 32b in the form of contact pins, which extend from the front side 20 in FIG Extend towards the rear 22.
  • the contact pins 31b, 32b are arranged in an inner region of the carrier 2 and laterally completely surrounded by the molded body 25.
  • second sections 31c, 32c of the electrically conductive connections 31, 32 are guided from the contact pins 31b, 32b to the contact surfaces 31a, 32a.
  • the second sections 31c, 32c run parallel to the front side 20 and are spaced apart from the rear side 22.
  • the contact surfaces 31a, 32a extend to the rear side 22 of the carrier 2 and are flush with the rear side 22.
  • the contact surfaces 31a, 32a are spaced from or withdrawn from the front side 20.
  • the contact surfaces 31a, 32a and the electrical connections 31, 32 are preferably made of metal, for example aluminum.
  • FIG. 2 shows an exemplary embodiment of the semiconductor component in a cross-sectional view.
  • the semiconductor chip 100 shown in FIG. 1 is mounted with the rear side 22 first on a connection carrier 200.
  • the connection carrier 200 is, for example, a printed circuit board.
  • the connection carrier 200 comprises a first connection area 201a and a second connection area 202a.
  • the connection areas 201a, 202a are, for example, metallic surfaces of the connection carrier 200.
  • the lateral contact surfaces 31a, 32a of the semiconductor chip 100 are wetted with an electrically conductive connecting means 8, for example a solder material, and are electrically conductive to the via this connecting means 8 Connection areas 201a, 202a connected.
  • a further connecting means 9 is arranged between the rear side of the semiconductor chip 100 and the connection carrier 200. In the present case, this completely covers the rear side 22 of the carrier 2 and produces a large-area mechanical connection between the connection carrier 200 and the semiconductor chip 100.
  • the further connecting means 9 can be electrically insulating. For example, it is an adhesive, such as a silicone adhesive. In the further connecting means 9, filler particles can be embedded to increase the thermal conductivity.
  • a substrate 4 which comprises a semiconductor layer sequence 1.
  • the substrate 4 comprises, for example, the growth substrate on which the semiconductor layer sequence 1 has grown epitaxially.
  • Contact pins 31b, 32b which are electrically conductively connected to the semiconductor layer sequence 1, are applied to the substrate 4.
  • the contact pins 31b, 32b were produced by electroplating, for example.
  • the first contact pins 31b are, for example, connected in an electrically conductive manner to an n-doped layer of the semiconductor layer sequence 1.
  • the second contact pins 32b are connected to a p-doped layer of the semiconductor layer sequence 1, for example.
  • a pair of a first contact pin 31b and a second contact pin 32b is clearly assigned to each semiconductor chip to be produced.
  • FIG. 3B shows a second position in the method in which a molded body 25, for example made of a dielectric material such as epoxy, is placed on the substrate 4. is upset. The molded body 25 reshapes the contact pins 31b, 32b and covers them.
  • FIG. 3C A third position of the method is shown in FIG. 3C, in which part of the previously applied molded body 25 is removed so that the contact pins 31b, 32b are exposed at the ends facing away from the substrate 4. On the side of the molded body 25 facing away from the substrate 4, the contact pins 31b, 32b are thus flush with the molded body 22.
  • the part of the shaped body 25 was removed, for example, by grinding.
  • FIG. 3D shows a fourth position in the method in which an electrically conductive layer 33 is applied to the side of the molded body 25 facing away from the substrate 4.
  • the electrically conductive layer 33 is, for example, a metal layer.
  • the electrically conductive layer 33 is first applied over the entire surface and thereby brought into electrical contact with the contact pins 31b, 32b. Through the electrically conductive layer 33, the contact pins 31b,
  • FIG. 3E shows a fifth position in which the electrically conductive layer 33 is structured, so that pairs each consisting of a first contact pin 31b and a second contact pin 32b that are no longer short-circuited via the electrically conductive layer 33 are formed.
  • FIG. 3F A sixth position in the method is shown in FIG. 3F, in which a dielectric layer 26 is applied to the side of the electrically conductive layer 33 facing away from the molded body 25.
  • the dielectric layer 26 is made of an inorganic material, for example educated.
  • the dielectric layer 26 and the molded body 25 together form a carrier 2.
  • the dielectric layer 26 initially completely covers the electrically conductive layer 33.
  • FIG. 3G shows a seventh position of the method in which trenches 5 are introduced in the area between adjacent pairs of contact pins 31b, 32b.
  • the trenches 5 are led from a side facing away from the substrate 4 through the dielectric layer 26, the electrically conductive layer 33 and into the molded body 25. This is where the trenches 5 end within the molded body 25.
  • the trenches 5 define the shape and size of the semiconductor chips that are created later.
  • FIG. 3H An eighth position in the method is shown in FIG. 3H, in which transverse sides 21 of the carrier 2 that are exposed within the trenches 5 are coated with an electrically conductive material 34, in particular a metal.
  • the electrically conductive material 34 is connected to the electrically conductive layer 33 in an electrically conductive manner.
  • FIG. 31 A ninth position of the method is shown in FIG. 31, in which the carrier 2 in the region of the trenches 5 and also the semiconductor layer sequence 1 are completely severed, as a result of which individual optoelectronic semiconductor chips are produced.
  • the previously applied, electrically conductive material 34 on the transverse sides 21 of the carrier 2 exposed in the region of the trenches 5 then forms the contact areas of the semiconductor chips.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)

Abstract

La présente invention concerne, selon au moins un mode de réalisation, une puce semi-conductrice optoélectronique (100) qui comprend un support (2) ayant un côté avant (20) et un côté arrière (22) opposé au côté avant, ainsi qu'une séquence de couches semi-conductrices (1) ayant une couche active (10) destinée à produire ou absorber un rayonnement électromagnétique sur le côté avant du support. En outre, la puce semi-conductrice comprend un premier plot de contact (31a) et un second plot de contact (32a) sur des surfaces externes du support destinées à entrer en contact électrique externe avec la puce semi-conductrice. Des connexions électroconductrices (31, 32) sont guidées depuis les plots de contact vers le côté avant du support. La séquence de couches semi-conductrices, par son côté faisant face au support, est électriquement connectée aux connexions électroconductrices sur le côté avant. Au moins le premier plot de contact est formé sur un côté transversal (21) du support s'étendant de manière transversale par rapport au côté avant.
PCT/EP2021/053077 2020-02-19 2021-02-09 Puce semi-conductrice optoélectronique et son procédé de fabrication WO2021165098A1 (fr)

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WO2008062767A1 (fr) * 2006-11-22 2008-05-29 Shinkawa Ltd. Puce semi-conductrice comportant une électrode de surface latérale, procédé de fabrication de la puce semi-conductrice, et module de montage tridimensionnel dans lequel est stratifiée la puce
EP2110866A1 (fr) * 2007-02-15 2009-10-21 Panasonic Electric Works Co., Ltd Boîtier de del et structure pour le montage d'un composant de circuit tridimensionnel
US20150162497A1 (en) * 2013-12-10 2015-06-11 Advanced Optoelectronic Technology, Inc. Light emitting diode package and method for manufacuring the same
US20170133557A1 (en) * 2014-09-30 2017-05-11 Xiamen Sanan Optoelectronics Technology Co., Ltd. Flip-chip Light Emitting Device and Fabrication Method
WO2017167792A1 (fr) * 2016-03-31 2017-10-05 Osram Opto Semiconductors Gmbh Procédé de fabrication d'un grand nombre de puces de semi-conducteur, puce de semi-conducteur et module équipé d'une puce de semi-conducteur
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DE102017113020B4 (de) 2017-06-13 2021-07-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Herstellung von Halbleiterbauelementen
DE102018119538A1 (de) 2018-08-10 2020-02-13 Osram Opto Semiconductors Gmbh Optoelektronisches halbleiterbauteil und herstellungsverfahren für optoelektronische halbleiterbauteile

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WO2008062767A1 (fr) * 2006-11-22 2008-05-29 Shinkawa Ltd. Puce semi-conductrice comportant une électrode de surface latérale, procédé de fabrication de la puce semi-conductrice, et module de montage tridimensionnel dans lequel est stratifiée la puce
EP2110866A1 (fr) * 2007-02-15 2009-10-21 Panasonic Electric Works Co., Ltd Boîtier de del et structure pour le montage d'un composant de circuit tridimensionnel
US20150162497A1 (en) * 2013-12-10 2015-06-11 Advanced Optoelectronic Technology, Inc. Light emitting diode package and method for manufacuring the same
US20170133557A1 (en) * 2014-09-30 2017-05-11 Xiamen Sanan Optoelectronics Technology Co., Ltd. Flip-chip Light Emitting Device and Fabrication Method
WO2017167792A1 (fr) * 2016-03-31 2017-10-05 Osram Opto Semiconductors Gmbh Procédé de fabrication d'un grand nombre de puces de semi-conducteur, puce de semi-conducteur et module équipé d'une puce de semi-conducteur
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