WO2017167792A1 - Procédé de fabrication d'un grand nombre de puces de semi-conducteur, puce de semi-conducteur et module équipé d'une puce de semi-conducteur - Google Patents

Procédé de fabrication d'un grand nombre de puces de semi-conducteur, puce de semi-conducteur et module équipé d'une puce de semi-conducteur Download PDF

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Publication number
WO2017167792A1
WO2017167792A1 PCT/EP2017/057378 EP2017057378W WO2017167792A1 WO 2017167792 A1 WO2017167792 A1 WO 2017167792A1 EP 2017057378 W EP2017057378 W EP 2017057378W WO 2017167792 A1 WO2017167792 A1 WO 2017167792A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
carrier
semiconductor
connection
recesses
Prior art date
Application number
PCT/EP2017/057378
Other languages
German (de)
English (en)
Inventor
Daniel Richter
Konrad Wagner
Original Assignee
Osram Opto Semiconductors Gmbh
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Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2017167792A1 publication Critical patent/WO2017167792A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body

Definitions

  • Destination can be mounted and are characterized by a particularly good heat dissipation during operation.
  • Another object to be solved is to provide a module with a plurality of semiconductor chips, which is particularly compact.
  • a method for producing a multiplicity of semiconductor chips is specified.
  • the semiconductor chips are in particular optoelectronic semiconductor chips.
  • the semiconductor chips can be used in operation for example for
  • Detection or to be provided for the emission of electromagnetic radiation may be at the
  • the method comprises a step in which an arrangement comprising a carrier and a semiconductor body is provided.
  • the arrangement may be, for example, a wafer in which the semiconductor body is epitaxially deposited on the carrier.
  • the carrier is then
  • a substrate wafer which may be formed with materials such as silicon, SiC or sapphire or consists of at least one of these materials.
  • the carrier is a sapphire growth substrate on which the semiconductor layers of the semiconductor body are epitaxially deposited.
  • the arrangement is formed by connecting the semiconductor body to the carrier.
  • connection can be produced by soldering or "direct bonding."
  • the support is not the growth substrate used to make the semiconductor body, for example, with materials such as silicon, SiC, sapphire , Glass, ceramics or consist of one of these materials.
  • the carrier and the semiconductor body are preferably arranged one above the other in a type of layer structure, the semiconductor body in particular in the direction of a
  • the support may in particular be a substrate or an auxiliary substrate, to which the
  • Arrangement consisting of carrier and semiconductor body can then for producing a module, for example on a
  • connection material arranged or connected.
  • the method comprises a step in which a multiplicity of recesses are formed in the arrangement, wherein a portion of the carrier is removed in the region of a recess.
  • Recesses can be made by chemical methods such as
  • Etching mechanical processes such as drilling or physical processes such as evaporation, for example by means of
  • Laser radiation or be generated by combinations of such methods.
  • a plurality of similar recesses is produced in the arrangement, which have the same geometric dimensions within the manufacturing tolerance.
  • the recesses are, for example, on a major surface of the arrangement at the grid points of
  • the recesses may be formed as trenches extending along a major part or the entire major surface of the assembly from which they originate
  • the method comprises a step in which at least partial filling of the recesses takes place with an electrically conductive contact material. That is, a majority, for example, at least 50% of the plurality of recesses, is at least partially associated with the electrically conductive
  • the recesses are at least partially with the
  • the contact material may fill the recesses completely or in part. It is possible, for example, that the recesses next to the electrically conductive
  • the electrically conductive contact material is in particular a material comprising at least one metal, several metals or a metal alloy.
  • the electrically conductive contact material can, for example, with application methods such as sputtering, chemical
  • the method comprises a step in which separating the
  • cylindrical or cuboid For example, cylindrical or cuboid
  • Semiconductor chips are generated, each comprising a part of the carrier and a part of the semiconductor body.
  • the separation takes place in places by the electrically conductive
  • Recess is present in a semiconductor chip and another part of the contact material of a recess in another, adjacent semiconductor chip is present.
  • the recesses are formed as trenches, for example, along the entire recesses
  • Dividing lines run along the recesses.
  • the recesses at the grid points of a regular grid for example in the form of holes with
  • each dividing line passes through a plurality of recesses.
  • the method comprises the following steps:
  • each of the contact points locally forms a side surface of the semiconductor chip, and each of the contact points extends in places on a bottom surface of the semiconductor chip.
  • Dividing lines in the plurality of semiconductor chips are separated by the contact material. This creates Side surfaces of the generated semiconductor chip, which are formed at least in places by the contact material. The exposed on the side surfaces contact material then forms a contact point, so that a side surface of the
  • the side surfaces are those surfaces that the bottom surface and a top surface of the semiconductor chip
  • the bottom surface and the top surface are transverse or perpendicular to one another
  • the side surface could then be parallel or substantially parallel to, for example
  • the recesses are formed, for example, as trenches in the arrangement, it is possible that a
  • subsequent upper part of the side surface is or is formed by material of the carrier and / or the semiconductor body.
  • material of the carrier and / or the semiconductor body For example, the part of the contact material which is exposed at the opening of the recess forms in
  • each contact point then extends in places on a side surface of the semiconductor chip and on the
  • Contact point can in this way be part of at least one Side surface and part of the bottom surface of the
  • the recesses are produced when the plurality of recesses are formed from the side of the semiconductor body facing away from the carrier. In this embodiment, the recesses then extend in a direction perpendicular to the
  • Semiconductor body and penetrate from there into the material of the carrier.
  • the manufactured semiconductor layers can act. Further, in this embodiment, the active area of the
  • the recesses are formed when the plurality of recesses are formed generated from the semiconductor body side facing away from the carrier forth and the recesses extend into the
  • This embodiment has the advantage that the recesses do not extend into the semiconductor body
  • Semiconductor body extend completely through the carrier, which can complicate the production of the vias, as an adjustment effort is greater than for
  • a multiplicity of plated-through holes are produced, which extend in places through the semiconductor body, and the plated-through holes are electrically conductively connected to the electrically conductive contact material.
  • Through-holes serve, for example, for contacting doped layers of the semiconductor body.
  • Through-contacts can then be operated, for example, an active layer arranged between the doped layers of the semiconductor body.
  • the vias make it possible to contact the semiconductor chip from a single side, for example, from its bottom surface. It is possible that the plated-through holes extend only in the semiconductor body. In this case, the recesses are produced on the side of the assembly which faces away from the carrier. Furthermore, it is possible that the Vias extend completely through the carrier. In this case, the recesses are produced on the side of the carrier facing away from the semiconductor body and do not extend into the semiconductor body.
  • Semiconductor chip can be produced by a method described here. That is, all features disclosed for the method are also for the semiconductor chip
  • the semiconductor chip comprises a carrier and a semiconductor body, a first contact point and a second contact point, which are used for electrical contacting of the semiconductor chip
  • each contact point locally forms a side surface of the semiconductor chip and each contact point in places on a bottom surface of the semiconductor chip
  • the semiconductor chip is based inter alia on the following considerations. It is possible to form radiation-emitting semiconductor chips in a so-called flip-chip design, in which the semiconductor chips can be contacted from a single side of the semiconductor chip.
  • the light extraction for radiation-emitting semiconductor chips takes place through the carrier, for which purpose it must be transparent.
  • the emission of electromagnetic radiation takes place directly at the top of the semiconductor chip and the electromagnetic radiation does not need the carrier
  • the chip can be particularly easily mounted at the destination, without further wiring technologies such as wire bonding or metallized tracks are necessary.
  • the contact points on the mounting side of the semiconductor chip must have the largest possible area.
  • the distance between the contact points can not be reduced arbitrarily, since otherwise threatening short circuits or mounting on standardized circuit boards is not possible. It is therefore not possible to provide single-sided contacted semiconductor chips having side surfaces of a lateral extent of less than 300 ym.
  • the semiconductor chip can be formed. In this way, the contact area of the semiconductor chip can be increased without the distance between the
  • edge lengths of less than 250 ym.
  • the contact points Due to the fact that the contact points locally form a side surface of the semiconductor chip and not only extend to the bottom surface of the semiconductor chip, the contact points have an enlarged
  • the first contact point and the second contact point on its outer surface facing away from the carrier in the region of the side surface of the semiconductor chip, which form the contact points in places, traces of a separation process.
  • the contact points as described in connection with the method, for example, be generated by the separation by the electrically conductive material in the recesses.
  • this separation which can be done for example via sawing, cutting or laser cutting, are at the contact points in the area of the side surfaces of
  • These tracks may be, for example, grooves, roughening or the like.
  • the traces of the separation process may increase the area of the pads on the side surfaces of the chip at least at the microscopic level, for example, improving the adhesion of a lead material, such as a solder or an electrically conductive adhesive, to the pads in that region. This may, for example, to an improved wetting of the lead material, such as a solder or an electrically conductive adhesive, to the pads in that region. This may, for example, to an improved wetting of the
  • the first contact point and the second one close
  • Semiconductor chips can be formed by the same separation process, with which also the carrier and the
  • the metallic contact points on the side surfaces of the semiconductor body are not on the carrier and / or the
  • the lateral dimensions of the semiconductor chip are not increased by the laterally arranged contact points, which in particular enables particularly compact semiconductor chips.
  • At least two plated-through holes which are themselves
  • Contact material are connected. That is to say, in the case of a semiconductor chip electrically contacted via the contact points, a current injection first takes place via the contact points to the plated-through holes and from there, for example, to an active layer of the semiconductor chip.
  • the plated-through holes extend completely through the carrier, in which case the bottom surface of the semiconductor chip is arranged on the side of the carrier facing away from the semiconductor body.
  • the module can in particular a semiconductor chip described here
  • the module comprises a semiconductor chip described here as well as a connection carrier, the first connection points and the second connection
  • connection material which in places between the
  • connection material has a mechanical and electrically conductive connection between the contact points of the semiconductor chip and the connection carrier.
  • connection material is, for example, a
  • connection material with the contact points is located on an underside of the contact points facing the connection carrier and on the side surfaces which form the contact points
  • connection material which may be, for example, a solder material or an electrically conductive adhesive, wets the contact points both at its the connection carrier
  • the module comprises a sheath which places the semiconductor chip in places on its side surfaces, the connection material on its side facing away from the semiconductor chip and the connection carrier
  • the sheath may be, for example, a plastic material such as a silicone or an epoxy resin.
  • the cladding may be radiation absorbing, radiation scattering, or radiation reflective
  • Additives for example particles, which impart the casing with desired mechanical and optical properties.
  • the envelope may be formed, for example, colored, black or white reflective.
  • the envelope may terminate flush with its upper side facing away from the connection carrier with the upper side of the semiconductor chip facing away from the connection carrier or laterally thereof overtop.
  • the top of the semiconductor chip facing away from the connection carrier is preferably free of the envelope.
  • the cladding laterally surrounds not only the chip but also the terminal material, the cladding also provides one in addition to its optical properties and its protective properties for the semiconductor chip
  • the enclosure can therefore also the
  • the module comprises a plurality of semiconductor chips, wherein the
  • Connection carrier at least two Verschaltungse
  • connection points of the connection carrier are electrically isolated from the connection points of the connection carrier. At least two of the
  • Connection elements must be connected in series. Furthermore, the interconnection elements in another level of
  • Connection carrier may be arranged as the connection points.
  • the connection carrier may in particular be a multilayer connection carrier, in which interconnection elements are arranged in a different plane than the connection points of the connection carrier.
  • the connection points can, for example, via
  • connection elements which are arranged in a position or plane of the Connection carrier are arranged below the position or level of the connection points.
  • Connection points and the interconnection element is then at least one insulation layer, which with a
  • electrically insulating material is formed.
  • the levels can be parallel or as part of the
  • modules with a large number of semiconductor chips can be realized in a particularly compact manner, in which the semiconductor chips can be controlled in the sense of a passive matrix display. Due to the fact that the semiconductor chips described here can be made particularly small, particularly compact modules can be realized with these semiconductor chips.
  • Figures 1A to 1H show process steps of a first embodiment of a method described herein in schematic sectional views.
  • the figure IG shows a schematic sectional view of an embodiment of a semiconductor chip described here.
  • an arrangement 12 comprising a carrier 1 and a semiconductor body 2 is provided.
  • the semiconductor body 2 is epitaxially grown on the carrier 1, for example.
  • the carrier 1 is then, for example, a sapphire substrate which is transparent in the spectral range of visible light.
  • Semiconductor body 2 may include, for example, an active layer 21.
  • the active layer 21 is in operation of the
  • the semiconductor body 2 may be a first doped layer 22, which is, for example, n-doped, and a second doped layer 23, which may be p-doped, for example is, include.
  • the semiconductor body 2 may be based on, for example, a III-V compound semiconductor material.
  • the provision of the arrangement 12 shown in connection with FIG. 1A can be achieved by epitaxially depositing the structure
  • Semiconductor body carried on the carrier.
  • doped layer 23 are produced in the semiconductor body 2.
  • To generate the vias 24, 25 can be
  • openings are produced in the semiconductor body 2, which in places with an electrically insulating passivation material and an electrically conductive
  • Figure IC are in the region of dividing lines 11, along which later
  • Dicing is done in individual semiconductor chips, recesses 4 generated by material removal.
  • the present case the
  • Trenches can extend.
  • the recesses 4 can then be along straight lines over the entire main surface of the
  • Arrangement 12 extend where they are generated.
  • the recesses for example, at the intersections of the dividing lines 11 and thus at the grid points of a
  • the recesses can be formed with a particularly large diameter, without, for example, that too much material of the semiconductor body must be removed per semiconductor chip. After separating each one becomes
  • Diameter is not lost too much chip area. Passivation and metallization of the recesses is particularly easy with large recesses.
  • the recesses therefore each extend over the entire length of a side surface; in the case of FIG. 1E, the recesses are formed only at the corners of the semiconductor chips to be produced.
  • Passivation 5 generated on the inner surfaces of the recess, which extends to the carrier 1 remote from the surface of the semiconductor body 2 to the plated-through holes 24, 25.
  • the passivation can be formed, for example, with an electrically insulating material such as silicon dioxide or silicon nitride.
  • the passivation will be in advance Area of the plated-through holes 24, 25 is open or there has an opening, so that an electrically conductive
  • Pads 61, 62 places a side surface 10c of the semiconductor chip is formed. Another area of
  • Side surface 10 c of the semiconductor chip 10 is formed, for example, by a part of the carrier 1. In this way, the contact points 61, 62 extend along
  • each of the recesses extends
  • Dividing lines 11 formed so in particular the corners of the semiconductor chip 10 in places by the contact points 61, 62 are formed. As can be seen in FIG. 1H, the distance B between the contact points 61, 62 may be as described herein
  • Semiconductor chip are chosen to be particularly large without the total contact area AI + A2 of the contact points is reduced. This is achieved by being part of the
  • outside surface of the contact surface is arranged on the side surface of the chip and therefore on the bottom surface 10b of the chip, a region of larger area for the formation of the distance between the contact points is available, without the cooling of the semiconductor chip or the adhesion of the contact points is deteriorated on a connection material ,
  • FIG. 2G shows a second embodiment of a described here
  • Semiconductor body 2 is provided. Again, can be any type of semiconductor material.
  • the semiconductor body 2 may be epitaxially deposited on the carrier 1.
  • Material removal are generated in the carrier and not in this embodiment in the semiconductor body. 2
  • the recesses 4 can extend as trenches along the parting lines 11 or are formed at intersections of the parting lines 11, for example with a round cross section. Due to the formation of the recesses 4 at the intersections of the dividing lines 11, the recesses with a particularly large
  • each recess with the contact material 6 therein is used to a quarter of each chip, so that per chip even with a large diameter recess is not lost too much chip area. Also a passivation and
  • Metallization of the recesses is particularly easy with large recesses.
  • the carrier is formed with an electrically insulating material, such as sapphire
  • a passivation 5 may be omitted in the next method step. This is shown in connection with Figure 2F, after which the recesses 4 with the electrically conductive
  • the distance between the contact points 61, 62 are particularly large, without the
  • Total area AI plus A2 of the contact points 61, 62 must be reduced.
  • Recesses 4 formed such that they extend through the entire assembly 12 of the carrier 1 and the semiconductor body 2. As a result, the contact points 61, 62 extend from the carrier 1 to the semiconductor body 2 along the entire side surface 10 c of the semiconductor chip 10
  • the passivation 5 is arranged.
  • the plated-through holes 24, 25 are formed only in the semiconductor body 2.
  • the module comprises the semiconductor chip 10, as explained in greater detail in connection with FIGS. 1H, 2G or 3, for example. Furthermore, the module 100 comprises a connection carrier 7, which has a Insulation layer 74 made of an electrically insulating
  • connection material 8 is arranged, which may be, for example, a solder material. As can be seen from FIG. 4, the connection material 8 wets the contact points 61, 62 both in the
  • Connection carrier 7 realized.
  • the module comprises a sheath 9.
  • the sheath 9 encloses the semiconductor chip 10 at its
  • the wrapping material 9 may be, for example, a silicone material filled with reflective titanium dioxide particles.
  • the envelope 9 is flush with the carrier 1 facing away from the outer surface of the
  • connection carrier 7 of FIG. 5 in conjunction with FIG.
  • the described module comprises insulating layers 74, 78, through which different circuit levels of the module are formed.
  • the insulating layer 74 separates the first and second terminals 71, 72 from the Interconnection elements 73a and 73b.
  • the insulating layer 78 separates the interconnection elements 73a, 73b from the
  • connection carrier 7 individual conductive elements of the connection carrier 7 are produced by plated-through holes 75a, b and 79a, b.
  • the multi-layer connection carrier can be, for example, ceramic insulation layers 74, 78
  • connection carrier 7 is a multilayer printed circuit board in which the
  • Insulating layers 74, 78 are formed by plastic materials.
  • red, green and blue light-emitting semiconductor chips can be connected to one another, whereby a particularly cost-effective and compact RGB light-emitting diode can be specified
  • Matrix interconnections of semiconductor chips can be realized. This is explained in greater detail for example in connection with FIGS. 6A and 6B.
  • FIG. 6A shows a module with a plurality of
  • FIG. 6B shows a schematic sectional representation.
  • a trained module may, for example, as part of a
  • semiconductor chips 10 can be connected via the
  • Connection points 72 of the connection carrier 7 is isolated.
  • the second connection locations 72 via the interconnection element 73a in the plane that pass through the insulation layer 74 from the first connection locations 71 and the second connection locations
  • This plane can via the junction 76 b, which through the via 79 b through the insulating layer 78 with the through
  • Connection points 71 of the semiconductor chips 10 are connected via a not shown Verschaltungselement 73a to the connection point 76a.
  • the semiconductor chips 10 of the module 100 can be controlled in this way in the sense of a passive matrix display.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un grand nombre de puces de semi-conducteur (10), une puce de semi-conducteur et un module équipé d'une puce de semi-conducteur. Le procédé comprend les étapes consistant à : - produire un ensemble (12) comprenant un support (1) et un corps de semi-conducteur (2), - former une pluralité d'évidements (4) dans l'ensemble (12), une partie du support (1) étant retirée au niveau des évidements (4), - remplir au moins partiellement les évidements (4) avec une matière de contact (6) et - séparer l'ensemble (12) le long d'une pluralité de lignes de séparation (11) ménagées dans la pluralité de puces de semi-conducteur (10), la séparation se faisant par endroits à travers la matière de contact (6) électriquement conductrice.
PCT/EP2017/057378 2016-03-31 2017-03-29 Procédé de fabrication d'un grand nombre de puces de semi-conducteur, puce de semi-conducteur et module équipé d'une puce de semi-conducteur WO2017167792A1 (fr)

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DE102016205308.6 2016-03-31
DE102016205308.6A DE102016205308A1 (de) 2016-03-31 2016-03-31 Verfahren zur herstellung einer vielzahl von halbleiterchips, halbleiterchip und modul mit einem halbleiterchip

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WO2020064943A1 (fr) * 2018-09-27 2020-04-02 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique à éléments de contact et son procédé de fabrication
WO2021165098A1 (fr) * 2020-02-19 2021-08-26 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique et son procédé de fabrication
US11201258B2 (en) 2018-11-15 2021-12-14 Nichia Corporation Method for manufacturing light emitting device

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JP2001044498A (ja) * 1999-07-28 2001-02-16 Nichia Chem Ind Ltd 窒化物半導体発光素子
US20050087884A1 (en) 2003-10-24 2005-04-28 Stokes Edward B. Flip-chip light emitting diode
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EP2360748A2 (fr) * 2010-02-11 2011-08-24 LG Innotek Co., Ltd. Dispositif électroluminescent et conditionnement de dispositif électroluminescent
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020064943A1 (fr) * 2018-09-27 2020-04-02 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique à éléments de contact et son procédé de fabrication
US11201258B2 (en) 2018-11-15 2021-12-14 Nichia Corporation Method for manufacturing light emitting device
WO2021165098A1 (fr) * 2020-02-19 2021-08-26 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique et son procédé de fabrication

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